Central points: chapter 7: Memory Hierarchies

7.1 Introduction 
- There are two types of locality: temporal and spatial
- There are three primary technologies used in building memory hierarchies: SRAM, DRAM, magnetic disk
- Every pair of levels in the memory hierarchy can be thought of as having an upper and lower level. Important terms include: 
	block - the unit of data moved between levels
	hit- the data is in the upper level (hit time)
	miss-the data is not in the upper level and must be retrieved from the lower level (miss penalty)
- In the memory hierarchy, smaller and faster memory technologies are placed cloaser to the processor

7.2 The basics of caches
- In a direct mapped cache, the address of the word in memory determines the location in the cache where   the data might be found.
- The cache contents include the data as well as valid and tag bits
- To take advantage of spatial locality, larger block sizes are used
- The memory system can be designed to help support caches 

7.3 Measuring and Improving cache performance
- Simple equations can be used to determine performance in the presence of caches
- At the other extreme of the direct mapped cache is the fully associative cache which often decreases miss rates at the expense of hit times
- In between direct-mapped and fully associative caches is the set associative cache
- Multi-level caches can be used to help reduce the miss penalty

7.4 Virtual Memory
- Virtual memory allows a single program to expand its address space beyond the limits of main memory
- The page table maps each page in virtual memory to either a page in main memory or a page stored on disk, which is the next level in the memory hierarchy (page, page faults)
- Virtual memory relies on translation from virtual addresses to physical addresses, and fast translation is accomplished by using a TLB
- One of the important functions for virtual memory is to allow sharing of a single main memory by multiple processes, while providing memory protection among these processes and the operating system

7.5 A Common Framework for Memory Hierarchies
- Four key question can be used to explain and examine common operational characteristics of the memory hierarchy:
	- Where can a block be placed on a miss ?
	- How is a block found ? 
	- Which block should be replaced ? 
	- What happens on a write ? 
- Misses can be classified into one of three types (compulsory, capacity, conflict)
- Improving the miss rate can have a negative performance effect and thus designing memory hierarchies is a challenge.

7.6 Real Stuff: The Pentium Pro and the PowerPC 604 Memory Hierarchies*
- Modern processors offer support for secondary caches located off of the main CPU die
- Additional optimizations are used to improve performance (eg: non-blocking caches).
- A significant design effort is required to keep the gap between processor cycle times and the memory cycle times under control

7.7 Fallacies and Pitfalls:
- Pitfall: Forgetting to account for byte addressing or the cache block size in simulating a cache
- Pitfall: Using miss rate as the only metric for evaluating a memory hierarchy
- Pitfall: Ignoring memory system behavior in writing programs or in generating code in a compiler
- Pitfall: Extending an address space by adding segments on top of an unsegmented address space