Processor: Datapath and Control

9/21/98


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Table of Contents

Processor: Datapath and Control

PPT Slide

The Processor: Datapath & Control

Implementation Details

Building blocks: combinatorial and sequential logic

Building Blocks: Register File

Building blocks: Register File (contd)

Simple Implementation

PPT Slide

Building the Datapath

Control

Control

Control

PPT Slide

Control implementation

Single Cycle Implementation

Where we are headed

Multicycle Approach

Review: finite state machines

Multicycle Approach

Multicycle Approach

Five Execution Steps

Step 1: Instruction Fetch

Step 2: Instruction Decode and Register Fetch

Step 3 (instruction dependent)

Step 4 (R-type or memory-access)

Write-back step

Summary:

Simple Questions

Implementing the Control

Graphical Specification of FSM

Finite State Machine for Control

PLA Implementation

Microprogramming

Microinstruction format

Microprogram Implementation

The Big Picture for control

Summary

Author: Shivkumar Kalyanaraman

Email: shivkuma@ecse.rpi.edu

Home Page: http://www.ecse.rpi.edu/Homepages/shivkuma