GaAs FRISC Test Wafer
Fast-RISC (FRISC) & SiGe Home Page |
[M. LeRoy] [S. Liu] [R. Clarke]
[T. Neogi (graduated 7/11)]
[P. Jacob (graduated 8/10)] [A. Zia (graduated 8/09)] [M. Chu (graduated 7/09)]
[J.-W. Kim (graduated 7/09)] [P. Belemjian (graduated 7/08)] [P. Jin (graduated 12/07)]
[O. Erdogan (graduated 12/06)] [J. Diao (graduated 12/06)] [Y. Yim (graduated 12/06)]
[J.-R. Guo (graduated 11/05)] [P. Curran (graduated 8/05)] [Y. Chao (graduated 5/05)]
[K. Zhou (graduated 8/04)] [R. Heikaus (graduated 8/04)] [J. Mayega (graduated 12/02)]
[M. Ernest (graduated 5/03)] [S. Steidl (graduated 5/01)] [B. Goda (graduated 5/01)]
[T. Krawczyk (graduated 12/00)] [S. Carlough (graduated 5/00)] [X. Ma (graduated 5/99)]
[A. Garg (graduated 8/97)] [P. M. Campbell (graduated 5/97)] [C. Maier (graduated 8/96)]
[K.-S. Nah (graduated 8/94)] [R. Philhower (graduated 12/93)] [J. Loy (graduated 8/93)]
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Since 1998 all SiGe designs, simulations, layouts, and verifications have been done using Cadence tools. Starting with the fall 1999 semester, the Cadence packages have been the primary IC design tools utilized in the Introduction to VLSI Design and the VLSI Design Automation classes offered by the Electrical, Computer, & Systems Engineering Dept. at Rensselaer. (More Cadence tools are used in other ECSE classes.)
Cadence Design System's homepage
Facilities & Equipment: Sun, Tektronix & more
 Introduction to FRISC Project
 Semiannual Reports
 Interim Reports
 Final Reports
 3-D Reports
 Slides
 Theses
 Teaching Reports
 Publications and Patents
 Clockless Asynchronous Logic Interests (CLASS)
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