Robert Philhower's Design Automation Manual

Conversion to HTML by Cliff Maier

This manual is a proper starting point to understand the COMPASS design automation tools (These tools were called VLSItools until COMPASS Design Automation split off from VLSI Technology, Inc.) as used by the F-RISC/G group at Rensselaer. An overview of the whole process will be given as well as references to manuals which provide more detailed information about each area. This manual assumes a thorough knowledge of CML circuits and techniques.

Volumes

Introduction
Naming Conventions
[cp] File Format
Netlist Extractor
Testing: Done by Atul. Yes, yes, yes, no, no, yes

Introduction

To use the COMPASS design tools to design a HBT chip requires many steps. These steps are interrelated and a knowledge of the whole process is necessary to understand the details of each step. The primary references are the COMPASS design automation tools manuals and the companion documents written at Rensselaer. These documents give many rules and conventions. These conventions should generally be followed unless there is a clear reason not to. If changes are needed in the future, a consistant set of schematics will aid in automatic conversion. Refer to figure {fig-overview} for an overview of the design process. FIGURE TO BE INCLUDED{Overview of the design process}

Setting Up a New Account

There are a few tasks which must be performed before your new Sun account is ready to use the F-RISC/G Design Automation Tool Suite.

You will need a CIE UNIX account. It is the same as your ULTRIX and RS/6000 account.
Your account must be in group ``vtitools''. Check by signing on to the account and typing: groups If the response does not include the word ``vtitools'' then you are not in the proper group; see Dave King about being added to the group.
You will have to edit the file ``.cshrc'' in your Sun account to attach to the Design Automation Tool Suite.
- Find the line switch ($arch)
- Duplicate everything from the case sun*: line down to the following breaksw. Make one of the cases ``sun3'' and the other ``sun4''.
- Add /cie3/frisc/bin to both of thse path statements.
- Add /cie2/vtitools/vlsi/v8r3/bin to the path statement for the ``sun3'' case.
- Add /cie3/vtitools/vlsi/v8r3/bin to the path statement for the ``sun4'' case.
- If your account does not run OpenWindows or suntools then you will have to add this environment to your account. Under the ``sun4'' case, add the following: setenv OPENWINHOME /usr/openwin setenv FONT1 6x10 setenv FONT2 8x13 setenv FONT3 9x15
  Also, add $OPENWINHOME/bin /usr/local/X11 to your path. If you want to add the ``openwin'' command to your .login file, you must be sure that it is only executed if you are sitting at the system console.
Close the current window and open a new one. This will cause your changes to .cshrc to take effect.
Create a directory in which to run the COMPASS design automation tools. This should never be run from your main directory. Enter this directory using the cd command.
If you run suntools, type vlsi to begin the tools; if you use OpenWindows, type xvlsi. (If your account doesn't start up either of these when you sign on, then see someone who uses OpenWindows to get set up.) When the window appears, select ``hbt'' from the menu, and type your account name as the library name.

COMPASS Design Automation Tools

The COMPASS design automation tools are an integrated set of tools which can perform most chip making functions for VLSI Technology's CMOS processes. The tools can perform logic synthesis, standard cell design, simulation, timing extraction, placement and routing, back-annotation, and bonding diagram editing. In addition, they can help design by adding self-test features and grading fault detection.

However, for the Rockwell HBT process, we have implemented only a subset of the available features. This subset is described below and in the referenced documents. Performing activities outside this subset may jeapordize the correctness of your design.

Libraries and Cells

A good overview of the operation of the COMPASS design automation tools is found in Manual_Overview. It is assumed that the reader has at least some familiarity with this manual. The COMPASS design automation tools implemented their own directory structure on top of the UNIX file system. Each file, called a cell, is stored as a separate UNIX file. These files are grouped into a UNIX directory or library. A library may have an internal tree structure not directly visible from UNIX. The libraries provide a convenient way to organize and manipulate cells. Each user has a private library in their working directory. In addition, they may access many shared or public libraries. Cells may be checked-out from public libraries to be modified. The tool maintains the status of each cell and does not allow multiple users to check-out the same cell. A partial list of the public libraries used by the F-RISC/G group is in the following table:

Library Name       Contents


cswsim              Digital simulation models, digital level & standard cells, timing models
cswchk              Voltage level checking models
hbtb1               Standard cell artwork, register file
diffpr              Standard cell phantoms for routing,  various router
                    and technology support files, (Standard dif-
                    ferential technology) 
fatpr               Standard cell phantoms for routing, various router
                    and technology support files, (Fat-wire technology)
cutpr               Standard cell phantoms for routing, various router
                    and technology support files, (Post-cutting tech-
                    nology)

Each cell has a type identifier associated with it. This type identifier, which appears as an extention to the UNIX file, determines how the tools react to the cell. In standard form, the type identifier is in square brackets preceeding the cell name. A few of the basic types are shown in the following table. ( E.G. [nls]alu would be the ALU netlist, [cc]dpchip would be the ChipCompiler output for the datapath chip.)

Type   Primary Tool   Description

[mds]  VLSImodel      Behavioral model source 
[mde]  VLSImodel      Behavioral model executable 
[mdi]  VLSImodel      Behavioral model interface file 
[tpl]  CellCompiler   Parametric model template cell 
[pcl]  CellCompiler   Parametric model parameter cell 
[la]   LogicAssistant Schematic, icon, standard cell 
[nls]  LogicAssistant Netlist derived from schematic 
[lad]  LogicAssistant Color definition file 
[wvd]  Wave           Waveform definition 
[sim]  Sim            Simulator command file 
[trc]  Sim            Simulator trace file 
[pmd]  TimingVerifier Primitive Model Definition 
[cp]   Compose        Layout information w/wires
[err]  Compose/DRC    DRC errors cell 
[ly]   Layout         Layout information, like CIF 
[scp]  ChipComp       Standard cell phantom 
[mcp]  ChipComp       Macro-cell phantom 
[tch]  ChipComp       Technology definition files 
[xch]  ChipComp       Product definition file 
[flr]  ChipComp       Floorplan 
[pkg]  ChipComp       Package definition 
[cc]   ChipComp       ChipCompiler output file 
[nle]  Extractors     Netlist extracted from layout 
[psp]  Extractors     SPICE sub-circuit file 
[seg]  Extractors     Wire segment file 
[spi]  Extractors     Extracted SPICE file 

awk    AWK            Program in the AWK language 
fs     Assembler      F-RISC assembler input 
dat    Assembler      Data memory listing 
ins    Assembler      Instruction memory listing 
lst    Assembler      Assembler output listing 
inv    Splicer        Inversion listing 
cir    Extractors     PSpice input file 
out    Extractors     PSpice output file 
io     Extractors     I/O signal definitions 
cir    PRESAGE        PSpice input file 
out    PRESAGE        PSpice output file 
pm     PRESAGE        Power Map 
segs   PRESAGE        Segment Map

Your Library Directory

The design tools will create files in your library directory. Most, but not all, of these files will correspond to cells in your library. The other files are control files which affect the execution of the design tools and contain state information about your library. These files are described in the COMPASS manuals, and will be briefly mentioned here.

vlsi.boo: This file contains boot commands for the design tools. These commands are executed when the tools start up. This file contains some settings for various options and your search path. See the ``Using VLSI.BOO'' section of the ``FUNDAMENTALS II'' manual for details on the options. Some of these options may be given values in the shared VLSI.BOO file for our group. Modification of these options may cause portions of the design tools to function improperly in our environment. To change your search path, use the VLSImanager program within the design tools.
vlsi.log: This file contains a log of all disk operations that have occurred in your library. You can delete this file to save space.
vlsi.atr: This file contains attributes of the library. The attributes include the date and time that the library was created; who is allowed to modify the library; the type of library (working, controlled, or read-only); and the number of versions of each cell that are kept. To modify information in this file, use the VLSImanager program within the design tools.
vlsi.idx: This file contains the name of the library and cross-references for cells that are given non-standard filenames. It should be mostly empty for our work.
vlsi.cko: This file contains a list of cells that have been checked out of this library. The name of the user and the time that the cell was checked out is also recorded. (A file that has been checked out by a user cannot be modified until it is checked back in.) To examine the list of cells checked-out of a library, use the VLSImanager program within the design tools. The working library in your account will not include this control file, as cells cannot be checked out of your library.
library.db: This file contains the name of each cell in the library and a description of the hierarchy (categories) within your library.

Logic-level Design

Each gate and circuit is represented at two levels, the logic level and the physical level. The logic representation captures the functionality of the circuit at the digital level. It consists primarily of schematics and digital models. The physical level contains the various mask levels and resistor values necessary to actually implement the circuit.

In comparison, the logic level contains less information, but can be processed more quickly and easily by both the tools and the human user.

Digital Modeling

Each of the basic circuits on the chip is modeled digitally using the VLSImodel behavioral modeling language as described in Manual_Model The currently available models are listed in the following table. Special models have been developed for checking the voltage levels of lines in the circuit. These models are described in a later section.


Model         Circuit Modeled    

dcsmo     Basic current switch 
emfmo     Emitter-follower (levels 1-3) 
sbmo      Super-buffer circuit 
ph4mo     4-Phase clock generation 
rfmo      Register file 
dfdmo     Differential I/O driver 
dfrmo     Differential I/O receiver 
sedmo     Single-Ended (ECL) I/O driver 
sermo     Single-Ended (ECL) I/O receiver 
bidmo     Bidirectional ECL drive/receiver

Differential pairs of wires are implemented as buses in the COMPASS tools. The convention is that in a bus such as S[1:0], S[1] is the ``true'' or ``positive'' line and S[0] is the ``inverted'' or ``negative'' line. These signals can be grouped larger buses, each containing twice the number of lines as there are signals in the circuit. Odd numbered lines are ``positive'' and even numbered lines are ``negative''.

Only three combinations of values are permitted on a differential pair of lines. Using these combinations, either of the two lines contains all of the information. It is sufficient to examine only one (usually S[1]) for proper output.

S[1]  S[0]  Description

0   1   Value 0 
1   0   Value 1 
U   U   Value Unknown

Standard Cell Logic Circuits

Using the models presented above, the LogicAssistant tool is used to design the logic circuit for each standard cell.

Schematic Entry

The LogicAssistant tool is used to connect gates into higher circuits.

Voltage Level Checking

Simulation

Physical-level Design

PSpice

Standard Cell Artwork

Many rules must be followed so the router will accept the cell.

Router Support Files

The placement and routing tools do not use the whole cell for placement. Instead, they use a standard cell phantom, or [scp] cell, as a place holder. The [scp] cell contains information about the placement and orientation of all standard cell connectors. The ChipCompiler generates [scp] cells in a text window using the drawn [cp] file. It checks the placement of connectors and the size of the cell to determine whether the cell is acceptable to the standard cell router. If the cell is not acceptable, it calls it a macro-cell and generates an [mcp] cell. [mcp] cells cannot be included in a standard cell area.

Placement and Routing

Talk about fat-wire routing

Router Support File Conversion

Netlist Conversion

To do fat-wire routing, a flattened netlist must be converted to fat-wire format. In this conversion, differential signals are converted into single lines for routing.