Current Research Areas/Topics:

Circuits & systems for data storage:
  1. Signal processing and coding algorithms and VLSI architectures for various data storage technologies (e.g., hard disk drive, NAND flash memory, holographic storage, phase-change memory);
  2. Data storage device and system co-design for data-intensive computing, data centers, and archival;
  3. 3D integrated solid-state drive circuits and architectures.
Circuits & systems for signal processing and computing:
  1. 3D logic-memory integration for general-purpose, embedded, and reconfigurable computing;
  2. Computing system memory hierarchy design with emerging digital memory technologies (e.g., MRAM and phase-change memory);
  3. High-performance and low-power signal processing circuits and architectures.

We always look for well-motivated students to join our group. Because of the inter-disciplinary nature and practical importance of our research, students will have excellent opportunities to pursue creative and rewarding research. This will put our students in very good positions for their future careers. Please send your resume to Professor Zhang if you are interested in joining us.

We gratefully acknowledge the support from the following funding agencies and companies.

           
         

Related Conferences

Journal Papers:

  1. W. Xu, H. Sun, X. Wang, Y. Chen, and T. Zhang, Design of Last-Level On-Chip Cache Using Spin-Torque Transfer RAM (STT RAM), IEEE Transactions on Very Large Scale Integration (VLSI) Systems, accepted
  2. N. Xie, T. Zhang, and E. F. Haratsch, Improving Burst Error Tolerance of LDPC-Centric Coding Systems in Read Channel, IEEE Transactions on Magnetics, accepted
  3. N. Xie, T. Zhang, and E. F. Haratsch, Exploration of Using Embedded DRAM to Reduce Energy Consumption of Magnetic Recording Read Channel, IEEE Transactions on Magnetics, accepted
  4. S. Li and T. Zhang, Improving Multi-Level NAND Flash Memory Storage Reliability Using Concatenated BCH-TCM Coding, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, accepted
  5. Y. Liu, T. Zhang, and K. K. Parhi, Computation Error Analysis in Digital Signal Processing Systems with Overscaled Supply Voltage, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, accepted
  6. W. Xu, T. Zhang, and Y. Chen, Design of Spin-Torque Transfer Magnetoresistive RAM and CAM/TCAM with High Sensing and Search Speed, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, accepted
  7. H. Sun, J. Liu, R. Anigund, N. Zheng, J.-Q. Lu, K. Rose, and T. Zhang, Design of 3D DRAM and Its Application in 3D Integrated Multi-Core Computing Systems, IEEE Design & Test, vol. 26, issue 5, pp. 36-47, Oct. 2009
  8. H. Sun, N. Zheng, and T. Zhang, Leveraging Access Locality for the Efficient Use of Multi-bit Error Correcting Codes in L2 Cache, IEEE Transactions on Computers, vol. 58, issue 10, pp. 1297-1306, Oct. 2009
  9. Y. Liu, T. Zhang, and J. Hu, Design of Voltage Overscaled Low-Power Trellis Decoders in Presence of Process Variations, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 17, issue 3, pp.439-443, March 2009
  10. T. Zhang, R. Micheloni, J.-Q. Lu, and Z. R. Huang, 3D Storage, Power Delivery and RF/Optical Transceiver - Case Studies of 3D Integration from System Design Perspectives, Proceedings of the IEEE (special issue on 3D Integration Technology), invited, vol. 97, issue 1, pp.161-174, Jan. 2009
  11. N. Xie, W. Xu, T. Zhang, E. F. Haratsch, and J. Moon, Concatenated LDPC and BCH Coding System for Magnetic Recording Read Channel with 4K-Byte Sector Format, IEEE Transactions on Magnetics, vol. 44, no. 12, pp. 4784-4789, Dec. 2008
  12. Y. Xin, A. Mujitaba, T. Zhang, and J. Jiang, Bypass Decoding -- A Reduced Complexity Decoding Technique for LDPC Coded MIMO-OFDM Systems, IEEE Transactions on Vehicular Technology, vol. 57, issue 4, pp. 2319-2333, July 2008
  13. S. Li and T. Zhang, Hybrid resistor/FET-logic demultiplexer architecture design for hybrid CMOS/nanodevice circuits, Nanotechnology, 19 (2008) 185202
  14. F. Sun and T. Zhang, Use of Parity Checks Inherent in LDPC Codes for Dominant Error Events Detection and k-Constraint Enforcement, IEEE Transactions on Magnetics, vol. 43, issue 12, pp. 4113-4116, 2007 (PDF)
  15. H. Zhong, W. Xu, N. Xie, and T. Zhang, Area-Efficient Min-Sum Decoder Design for High-Rate QC-LDPC Codes in Magnetic Recording, IEEE Transactions on Magnetics, vol. 43, issue 12, pp. 4117-4122, 2007 (PDF)
  16. F. Sun and T. Zhang, Quasi-Reduced-State Soft-Output Viterbi Detector for Magnetic Recording Read Channel, IEEE Transactions on Magnetics, vol. 43, issue 10, pp. 3921-3924, 2007 (PDF)
  17. F. Sun, L. Feng, and T. Zhang, Run-Time Data-Dependent Defect Tolerance for Hybrid CMOS/Nanodevice Digital Memories, IEEE Transactions on Nanotechnology, vol. 6, issue 3, pp. 341-351, 2007 (PDF)
  18. F. Sun, S. Devarajan, K. Rose, and T. Zhang, Design of On-Chip Error Correction Systems for Multilevel NOR and NAND Flash Memories, IET Circuits, Devices & Systems, vol. 1, issue 3, pp. 241-249, June 2007 (PDF)
  19. F. Sun and T. Zhang, Low-Power State-Parallel Relaxed Adaptive Viterbi Decoder, IEEE Transactions on Circuits and Systems I, vol. 54, no. 5, pp. 1060-1068, May 2007 (PDF)
  20. F. Sun and T. Zhang, Defect and Transient Fault Tolerant System Design for Hybrid CMOS/Nanodevice Digital Memories, IEEE Transactions on Nanotechnology, vol. 6, no. 3, pp. 341-351, May 2007 (PDF)
  21. S. Chen, T. Zhang, and Y. Xin, Relaxed K-best MIMO Signal Detector Design and VLSI Implementation, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 15, issue 3, pp. 328-337, March 2007 (PDF)
  22. H. Zhong, T. Zhang, and E. F. Haratsch, Quasi-Cyclic LDPC Codes for the Magnetic Recording Channel: Code Design and VLSI Implementation, IEEE Transactions on Magnetics, vol. 43, issue 3, pp. 1118-1123, March 2007 (PDF)
  23. F. Sun and T. Zhang, Parallel High-Throughput Limited Search Trellis Decoder VLSI Design, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 13, number 9, pp. 1013-1022, September 2005 (PDF)
  24. S. Chen and T. Zhang, Self-Timed Dynamically Pipelined Adaptive Signal Processing System: A Case Study of DLMS Equalizer for Read Channel, IEEE Transactions on Circuits and Systems I, vol. 52, issue 7, pp. 1338-1347, July 2005 (PDF)
  25. H. Zhong and T. Zhang, Block-LDPC: A practical LDPC coding system design approach, IEEE Transactions on Circuits and Systems I, vol. 52, issue 4, pp. 766-775, April 2005 (PDF)
  26. T. Zhang and K. K. Parhi, Joint (3,k)-Regular LDPC Code and Decoder/Encoder Design, IEEE Transactions on Signal Processingvol. 52, no. 4, pp. 1065-1079, April 2004 (PDF)(PS)
  27. T. Zhang and K. K. Parhi, An FPGA Implementation of (3,6)-Regular Low-Density Parity-Check Code Decoder, EURASIP Journal on Applied Signal Processing, special issue on Rapid Prototyping of DSP Systems vol. 2003, no. 6, pp. 530-542, May 2003 (PDF)(PS)
  28. T. Zhang and K. K. Parhi, Systematic Design of Original and Modified Mastrovito Multipliers for General Irreducible Polynomials, IEEE Transactions on Computers, vol. 50, pp. 734-749, July 2001 (PDF)(PS)

Conference Papers:

  1. W. Xu and T. Zhang, Using Time-Aware Memory Sensing to Address Resistance Drift Issue in Multi-Level Phase Change Memory, IEEE International Symposium on Quality Electronic Design (ISQED), March 2010
  2. Y. Liu, J. Liu, and T. Zhang, Design of Low-Power Variation Tolerant Signal Processing Systems with Adaptive Finite Word-length Configuration, IEEE International Symposium on Quality Electronic Design (ISQED), March 2010
  3. Y. Pan and T. Zhang, DRAM-Based FPGA Enabled by Three-Dimensional (3D) Memory Stacking, ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), Feb. 2010
  4. J. Lee, J. Moon, T. Zhang, and E. Haratsch, New PLL Design: Understanding the Impact of a Phase-Tracking Channel Detector, The Magnetic Recording Conference (TMRC), Oct. 2009
  5. Q. Wu, K. Rose, J.-Q. Lu, and T. Zhang, Impacts of Though-DRAM Power Vias in 3D Processor-DRAM Integrated Systems, IEEE 3D System Integration Conference, Sept. 2009
  6. A. Beece, K. Rose, T. Zhang, and J.-Q. Lu, Impact of Model Accuracy on 3D Design, IEEE 3D System Integration Conference, Sept. 2009
  7. Z. Xu, A. Beece, K. Rose, T. Zhang, and J.-Q. Lu, Modeling and Evaluation for Electrical Characteristics of Through Strata Vias (TSVs) in Three-Dimensional Integration, IEEE 3D System Integration Conference, Sept. 2009
  8. W. Xu, J. Liu, and T. Zhang, Data Manipulation Techniques to Reduce Phase Change Memory Write Energy, International Symposium on Low Power Electronics and Design (ISLPED), August 2009
  9. Y. Pan and T. Zhang, Improving VLIW Processor Performance using Three-Dimensional (3D) DRAM Stacking, IEEE Application-specific Systems, Architectures and Processors (ASAP), July 2009
  10. Q. Wu, K. Rose, J.-Q. Lu, and T. Zhang, On the Impact of Though-DRAM Power Vias in 3D Processor-DRAM Integrated Systems, SRC TECHCON, Sept. 2009
  11. S. Li and T. Zhang, Let CNT and Metal Cooperate other than Compete in Future Integrated Circuits, SRC TECHCON, Sept. 2009
  12. S. Li and T. Zhang, Using Carbon Nanotubes in Digital Memories, IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), July 2009
  13. W. Xu, X. Wang, Y. Chen, and T. Zhang, Improving STT MRAM Storage Density through Smaller-Than-Worst-Case Transistor Sizing, Design Automation Conference (DAC), July 2009
  14. H. Li, H. Xi, Y. Chen, X. Wang, and T. Zhang, Thermal-Assisted Spin Transfer Torque Memory (STT-RAM) Cell Design Exploration, IEEE Computer Society Annual Symposium on VLSI, May 2009
  15. S. Li and T. Zhang, Approaching the Information Theoretical Bound of Multi-Level NAND Flash Memory Storage Efficiency, International Memory Workshop, May 2009
  16. Q. Wu, J.-Q. Lu, K. Rose, and T. Zhang, Efficient Implementation of Decoupling Capacitors in 3D Processor-DRAM Integrated Computing Systems, ACM Great Lakes Symposium on VLSI, May 2009
  17. S. Li and T. Zhang, Improving Multi-Level NAND Flash Memory Storage Reliability Using Concatenated TCM-BCH Coding, ACM Great Lakes Symposium on VLSI, May 2009
  18. R. Anigundi, H. Sun, J. Lu, K. Rose, and T. Zhang, Architecture Design Exploration of Three-Dimensional (3D) Integrated DRAM, IEEE International Symposium on Quality Electronic Design (ISQED), March 2009
  19. S. Li and T. Zhang, Exploratory Study on Circuit and Architecture Design of Very High Density Diode-Switch Phase Change Memories, IEEE International Symposium on Quality Electronic Design (ISQED), March 2009
  20. H. Sun, J. Liu, N. Zheng, J.-Q. Lu, K. Rose, and T. Zhang, Multi-Core Computer Memory Hierarchy Design using Heterogeneous Three-Dimensional (3D) Stacked DRAM , Workshop of 3D integration and interconnect-centric architectures in conjunction with International Symposium on High-Performance Computer Architecture (HPCA), Feb. 2009
  21. H. Sun, N. Zheng, and T. Zhang, Realization of L2 Cache Defect Tolerance Using Multi-bit ECC, IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Oct. 2008
  22. Y. Liu, T. Zhang, and K. K. Parhi, Analysis of Voltage Overscaled Computer Arithmetics in Low Power Signal Processing Systems, IEEE Asilomar Conference on Signals, Systems, and Computers, Oct. 2008
  23. H. Sun, N. Zheng, and T. Zhang, Algorithm and VLSI Architecture Design for Variable Block Size Motion Compensated De-interlacing, IEEE Asilomar Conference on Signals, Systems, and Computers, Oct. 2008
  24. S. Li and T. Zhang, Decoder and Sensing Circuit Design Approaches for High-Density Diode-Switch Phase Change RAM, SRC TECHCON, Sept. 2008
  25. W. Xu, T. Zhang and Y. Chen, Spin-Transfer Torque Magnetoresistive Content Addressable Memory (CAM) Cell Structure Design with Enhanced Search Noise Margin, IEEE Int. Symp. on Circuits and Systems (ISCAS), May 2008 (PDF)
  26. Y. Liu, F. Sun and T. Zhang, Energy-Efficient Soft-Output Trellis Decoder Design Using Trellis Quasi-Reduction and Importance-Aware Clock Skew, IEEE Int. Symp. on Circuits and Systems (ISCAS), May 2008 (PDF)
  27. R. Dani, T. Zhang and J. Woods, Image Processing Assisted Voltage Overscaling for Energy Efficient IC Realization of Motion Estimation, Visual Communications and Image Processing (VCIP), Jan. 2008 (PDF)(invited)
  28. S. Li and T. Zhang, Hybrid Resistor/FET-Logic Demultiplexer Architecture Design for Hybrid CMOS/Nanodevice Circuits, IEEE International Conference on Computer Design (ICCD), Oct. 2007 (PDF)
  29. Y. Xin, A. Mujitaba, and T. Zhang, Turbo- and LDPC-Coded MIMO-OFDM Systems: A Comparative Study, International Symposium on Personal Indoor and Mobile radio Communications (PIMRC), Sept. 2007
  30. Y. Liu and T. Zhang, On the Selection of Arithmetic Unit Structure in Voltage Overscaled Soft Digital Signal Processing, International Symposium on Low Power Electronics and Design (ISLPED), Aug. 2007 (PDF)
  31. S. Chen and T. Zhang, Low Power Soft-Output Signal Detector Design for Wireless MIMO Communication Systems, International Symposium on Low Power Electronics and Design (ISLPED), Aug. 2007 (PDF) (Nominated for Best Paper Award)
  32. Y. Liu, T. Zhang, and J. Hu, Soft Clock Skew Scheduling for System-Level Variation Tolerance in Digital Signal Processing Circuits, IEEE International Symposium on Quality Electronic Design (ISQED), March 2007
  33. F. Sun, K. Rose, and T. Zhang, On the Use of Strong BCH Codes for Improving Multilevel NAND Flash Memory Storage Capacity, IEEE Workshop on Signal Processing Systems (SiPS): Design and Implementation, Oct. 2006 (PDF)
  34. Y. Liu, T. Zhang, and J. Hu, Low Power Trellis Decoder with Overscaled Supply Voltage, IEEE Workshop on Signal Processing Systems (SiPS): Design and Implementation, Oct. 2006 (PDF)
  35. S. Chen, F. Sun, and T. Zhang, Nonlinear Soft-Output Signal Detector Design and Implementation for MIMO Communication Systems with High Spectral Efficiency, IEEE Custom Integrated Circuits Conference (CICC), Sept. 2006 (PDF)
  36. H. Zhong, T. Zhang, and E. F. Haratsch, VLSI Design of High-Rate Quasi-Cyclic LDPC Codes for Magnetic Recording Channel, IEEE Custom Integrated Circuits Conference (CICC), Sept. 2006
  37. F. Sun and T. Zhang, Two Fault Tolerance Design Approaches for Hybrid CMOS/Nanodevice Digital Memories, IEEE International Workshop on Defect and Fault Tolerant Nanoscale Architectures (Nanoarch), June 2006 (PDF)
  38. S. Chen, T. Zhang, and M. Goel, Relaxed Tree Search MIMO Signal Detection Algorithm Design and VLSI Implementation, IEEE Int. Symp. on Circuits and Systems (ISCAS), May 2006 (PDF)
  39. F. Sun, S. Devarajan, K. Rose, and T. Zhang, Multilevel Flash Memory On-Chip Error Correction Based on Trellis Coded Modulation, IEEE Int. Symp. on Circuits and Systems (ISCAS), May 2006 (PDF)
  40. F. Sun and T. Zhang, Low Power State-Parallel Relaxed Adaptive Viterbi Decoder, IEEE Int. Symp. on Circuits and Systems (ISCAS), May 2006 (PDF)
  41. H. Zhong, T. Zhang, and E. F. Haratsch, High-Rate Quasi-Cyclic LDPC Codes for Magnetic Recording Channel with Low Error Floor, IEEE Int. Symp. on Circuits and Systems (ISCAS), May 2006 (PDF)
  42. K. Zhou, Y. Luo, S. Chen, A. Drake, J. McDonald, and T. Zhang, Triple-Rail MOS Current Mode Logic for High-Speed Self-Timed Pipeline Applications, IEEE Int. Symp. on Circuits and Systems (ISCAS), May 2006
  43. S. Chen, T. Zhang, and Y. Xin, Breadth-First Tree Search MIMO Signal Detector Design and VLSI Implementation, Military Communications Conference (MILCOM), Oct. 2005 (PDF)
  44. H. Zhong and T. Zhang, Iterative Max-Log-MAP and LDPC Detector/Decoder Hardware Implementation for Magnetic Read Channel, SRC TECHCON, Oct. 2005
  45. F. Sun and T. Zhang, Low-Power State-Parallel Relaxed Adaptive Viterbi Decoder Design and Implementation, Design Contest winner entry, International Symposium on Low Power Electronics and Design (ISLPED), Aug. 2005
  46. K. Zhou, S. Chen, A. Rucinski, J. McDonald, and T. Zhang, Self-timed triple-rail MOS current mode logic pipeline for power-on-demand design, IEEE Midwest Symposium on Circuits and Systems, Aug. 2005
  47. T. Zhang, Y. Xin, and S. Chen, Parallelism/Regularity-Driven MIMO Detection Algorithm Design, IEEE Int. Symp. on Circuits and Systems (ISCAS), May 2005 (PDF)
  48. S. Chen and T. Zhang, Run-time Reconfigurable Adaptive Signal Processing System with Asynchronous Dynamic Pipelining: A Case Study of DLMS ADFE, IEEE Workshop on Signal Processing Systems (SiPS): Design and Implementation, Oct. 2004 (PDF)
  49. T. Zhang, A High Throughput Limited Search Trellis Decoder for Convolutional Code Decoding, IEEE Int. Symp. on Circuits and Systems (ISCAS), May 2004 (PDF)
  50. H. Zhong and T. Zhang, Joint Code-Encoder-Decoder Design for LDPC Coding System VLSI Implementation, IEEE Int. Symp. on Circuits and Systems (ISCAS), May 2004 (PDF)
  51. T. Zhang, J. Wu and G. J. Saulnier, Efficient Coherent Detector VLSI Design for Continuous Phase Modulation, IEEE Asilomar Conference on Signals, Systems, and Computers, Nov. 2003 (PDF)
  52. H. Zhong and T. Zhang, Design of VLSI Implementation-Oriented LDPC Codes, IEEE Semiannual Vehicular Technology Conference (VTC), Oct. 2003 (PDF)
  53. T. Zhang and K. K. Parhi, A 54 Mbps (3,6)-Regular FPGA LDPC Decoder, Proc. of the 2002 IEEE Workshop on Signal Processing Systems (SiPS): Design and Implementation, Oct. 2002 (PDF)(PS)
  54. T. Zhang and K. K. Parhi, On the High-Speed VLSI Implementation of Errors-and-Erasures Correcting Reed-Solomon Decoders, Proc. of the 12th Great Lakes Symposium on VLSI, April 2002 (PDF)(PS)
  55. T. Zhang and K. K. Parhi, Joint Code and Decoder Design for Implementation-Oriented (3,k)-regular LDPC codes, Proc. of IEEE Asilomar Conference, Nov. 2001 (PDF)(PS)
  56. T. Zhang and K. K. Parhi, High-Performance, Low-Complexity Decoding of Generalized Low-Density Parity-Check Codes, Proc. of Globecom’01, San Antonio, TX, Nov. 2001 (PDF)(PS)
  57. T. Zhang and K. K. Parhi, VLSI Implementation-Oriented (3,k)-regular Low-Density Parity-Check Codes, Proc. of the 2001 IEEE Workshop on Signal Processing Systems (SiPS): Design and Implementation, pp. 25-36, Antwerp, Belgium, Sept. 2001 (PDF)(PS)
  58. T. Zhang, Z. Wang and K. K. Parhi, On Finite Precision Implementation of Low-Density Parity-Check Codes Decoder, Proc. of the 2001 IEEE Int. Symp. on Circuits and Systems (ISCAS), vol. 4, pp. 202-205, Sydney, Australia, May 2001 (PDF)(PS)
  59. T. Zhang and K. K. Parhi, A Class of Efficient-Encoding Generalized Low-Density Parity-Check Codes, Proc. of 2001 IEEE Int. Conf. on Acoustics, Speech, and Signal Processing (ICASSP), vol. 4, pp. 2477-2480, Salt Lake City, Utah, May 2001 (PDF)(PS)
  60. T. Zhang and K. K. Parhi, A Novel Systematic Design Approach of Mastrovito Multipliers over GF(2^m), Proc. of the 2000 IEEE Workshop on Signal Processing Systems (SiPS): Design and Implementation, pp. 507-516, Lafayette, LA, Oct. 2000 (PDF)(PS)

The more you know, the more you learn;

The more you learn, the more you can do;

The more you can do, the more opportunity!

--- Richard W. Hamming