The CMOS inverter is composed of one NMOS and one PMOS, with their gates connected together as the input, and their drains connected together as the output. The transfer I-V characteristics are measured by a applying staircase sweep voltage to the input, (Vi) and applying a current source to the output (Io) while monitoring the output voltage. The source (Vdd) and substrate (Vb) of the PMOS are set to a constant positive voltage, and the source and substrate of the NMOS are grounded.

The experimental parameters to be entered in the Source Setup pop-up panel include the start, stop, and step voltages for the input sweep voltage. You may also select the compliance current for protection. The input voltage is limited to (0, 5V).

The NMOSFET and the PMOSFET of which the CMOS is composed are two of the devices integrated on a chip named AIM-Spice Test Chip.

To run the experiment, go back to Remote Lab Homepage.