The PMOS Id-Vd characteristics are measured by applying a staircase sweep voltage to the drain (Vd) of the PMOS and monitoring the drain current. A constant voltage is applied to the gate (Vg) during each sweep, and a group of Id-Vd data curves can be acquired by varying the gate voltage between sweeps. A bias voltage can also be applied to the substrate contact.(Vb) The source is grounded.
The experimental parameters include the start, stop, and step voltages for the sweep, the start voltage, step voltage and the number of steps of the gate voltages as well as the bias voltage of the substrate. You may also select the compliance current for protection. Both the drain voltage and gate voltage are limited to (-5.0V, 5.0V), and the substrate bias is limited to (-3.0V, 0.3V).
The PMOSFET under test is one of the devices integrated on a chip named AIM-Spice Test Chip.
To run the experiment, go back to Remote Lab Homepage.