#1 "def21020.h"

{-------------------------------------------------------------------------------
def21020.h - STATUS REGISTER BIT DEFINITIONS FOR ADSP-21020

This include file contains a list of "defines" to enable the programmer to 
use symbolic names for all of the system register bits for the ADSP-21020.
-------------------------------------------------------------------------------}
 





































































































#2 "proj1"




{.GLOBAL         lms_init, lms_alg;}


.SEGMENT/DM     dm_sram;
.VAR            state[5    ];
.ENDSEG;


.SEGMENT/DM     hip_regs;
.PORT           in_audio_l;     { ADSP-2111 HDR0 = left input from AD1849 }
.PORT           in_audio_r;     { ADSP-2111 HDR1 = right input from AD1849 }
.PORT           out_audio_l;    { ADSP-2111 HDR2 = left output to AD1849 }
.PORT           out_audio_r;    { ADSP-2111 HDR3 = right output to AD1849 }
.PORT           control_0;      { ADSP-2111 HDR4 = AD1849 input and gain }
.PORT           control_1;      { ADSP-2111 HDR5 = ad1849 sample rate select }
.ENDSEG;


.SEGMENT/PM     rst_svc;
		call init_21k;
		jump main;
.ENDSEG;


.SEGMENT/PM     irq3_svc;
		jump irq3_asserted;
.ENDSEG;


.SEGMENT/PM     pm_sram;
.VAR            weights[5    ];
main:           bit set mode1 0x00001000 ;         { enable global int.}
		idle;
		nop;
		nop;


{___________________________initialize the chip___________________________}
init_21k:
		{ pgsz=32K,pmwtstates=0,sw.wtstates only}
		pmwait  = 0x1c21;   
		
		{ pgsz=32K,bank2_dmwtstates=1,sw.wtstates only}
		dmwait  = 0x70a421;  
		
		{ clear any pending interrupts}
		irptl = 0;         
		
		{clr cache}
		bit set mode2 0x10; nop; read cache 0; bit clr mode2 0x10; 
		
		{ irq3 enable, timer enable high priority}
		bit set imask 0x00000020 ;
			    
		{ irq3 edge sens, flag 1,2,3,outputs}
		bit set mode2 0x00000008 |0x00010000 |0x00020000 |0x00040000 ;
		
		{ turn flag LEDs off}
		bit clr astat 0x00100000 |0x00200000 |0x00400000 ;
	
		r0 = 0x10000000;
		dm(control_0) = r0;
		r0 = 0x80060000;
		dm(control_1) = r0;
		
{lms_init:       b0 = state;
		m0 = -1;
		l0 = 5    ;
		b8 = weights;
		b9 = b8;
		m8 = 1;
		l8 = 5    ;
		l9 = l8;}
		f7 = 1.0;
		f0 = -1.0;
		{lcntr = 5    , do clear_bufs until lce;
clear_bufs:             dm(i0, m0) = f0, pm(i8, m8) = f0;}
		rts;
		nop;
		nop;
      

{__________________________IRQ3 Interrupt Vector____________________________}
{irq3_asserted:
		r2 = dm(in_audio_l);       get AD1849 left value 
		r4 = dm(in_audio_r);
		r8 = 30;
		f0 = float r4 by r8;
		f2 = float r2 by r8;
		f1 = f0 + f2;
		{r12 = -30;
		r4 = fix f1 by r12;
		dm(out_audio_r) = r4;      output AD1849 left value 
		
lms_alg:        dm(i0, m0) = f0, f4 = pm(i8, m8);        
		f8 = f0*f4, f0 = dm(i0, m0), f4 = pm(i8, m8);
		f12 = f0*f4, f0 = dm(i0, m0), f4 = pm(i8, m8);
		lcntr = 5     - 3, do macs until lce;
macs:                   f12 = f0*f4, f8 = f8 + f12, f0 = dm(i0, m0), f4 = pm(i8, m8);
		f12 = f0*f4, f8 = f8 + f12;
		f13 = f8 + f12;            f13 = y(n)
		f6 = f1 - f13;             f6 = e(n) 
		f1 = f6*f7, f4 = dm(i0, m0);
		f0 = f1*f4, f12 = pm(i8, m8);
		lcntr = 5     - 1, do update_weights until lce;
			f8 = f0 + f12, f4 = dm(i0, m0), f12 = pm(i8, m8);
update_weights:         f0 = f1*f4, pm(i9, m8) = f8;
		f8 = f0 + f12, f0 = dm(i0, 1);
		pm(i9, m8) = f8;}
irq3_asserted:                
		nop;
		nop;
		nop;
		{pop sts;
		bit tgl astat 0x00100000 ;
		push sts;}

		f7 = f7 * f0;

		r12 = 32;
		r4 = fix f7 by r12;
		dm(out_audio_l) = r4;     { output AD1849 left value }
		rti;
		nop;
		nop;
.ENDSEG;