/* @(#)dma.h	1.0 1/26/95 1 */

#ifndef __DMA_DEFINED
#define __DMA_DEFINED

struct __dma_control_word
{
  /* unused bits */
  unsigned int const volatile ubits:16;

  /* External Port buffer status bits */
  unsigned int const volatile fs:2;

  /* Flush External Port buffer to empty status */
  unsigned int volatile flsh:1;

  /* Handshake DMA to external Memory */
  unsigned int volatile hextern:1;

  /* Interrupt enable for External port buffer */
  unsigned int volatile intio:1;

  /* Use ~DMAR(x) pin to initiate DMA */
  unsigned int volatile hshake:1;

  /* Enable DMA Master */
  unsigned int volatile master:1;

  /* Most significant word first during packing */
  unsigned int volatile mswf:1;

  /* Packing mode (00=none, 01=16/32, 10=16/48, 11=32/48) */
  unsigned int volatile pmode:2;

  /* Data type:  0=data, 1=instruction */
  unsigned int volatile dtype:1;

  /* Pack Status - generated by hardware */
  unsigned int const volatile ps:2;

  /* DMA channel direction */
  unsigned int volatile tran:1;

  /* DMA chaining enable */
  unsigned int volatile chen:1;

  /* External Port DMA Enable */
  unsigned int volatile den:1;
}

#define dma6_iop (*(volatile struct __dma_control_word *)0x001c)
#define dma7_iop (*(volatile struct __dma_control_word *)0x001d)
#define dma8_iop (*(volatile struct __dma_control_word *)0x001e)
#define dma9_iop (*(volatile struct __dma_control_word *)0x001f)

/* Prototypes */

int dma_status  (int DMA_CHANNEL);
int dma_setup   (int DMA_CHANNEL, struct dma_control_word);
int dma_enable  (int DMA_CHANNEL);
int dma_disable (int DMA_CHANNEL);

#define PACKDEFAULT  0x00
#define PACK16_TO_32 0x01
#define PACK16_TO_48 0x10
#define PACK32_TO_48 0x11


#define dma_status (DMA_CHANNEL) \
  ({ int ___ret_val; \
       switch (DMA_CHANNEL) \
        {\
	 case 6: ret_val = dma6_iop.den; break; \
	 case 7: ret_val = dma7_iop.den; break; \
	 case 8: ret_val = dma8_iop.den; break; \
	 case 9: ret_val = dma9_iop.den; break; \
	 default: ret_val=-1;}\
   ___ret_val;})

#define dma_setup (DMA_CHANNEL, DMA_CONTROL_WORD) \
({ int ___ret_val=1; \
       switch (DMA_CHANNEL) \
        {\
	 case 6: dma6_iop = DMA_CONTROL_WORD; break; \
	 case 7: dma7_iop = DMA_CONTROL_WORD; break; \
	 case 8: dma8_iop = DMA_CONTROL_WORD; break; \
	 case 9: dma9_iop = DMA_CONTROL_WORD; break; \
	 default: ret_val=-1;}\
   ___ret_val;})
})

#define int dma_enable (DMA_CHANNEL) \
({ int ___ret_val; \
       switch (DMA_CHANNEL) \
        {\
	 case 6: ret_val = dma6_iop.den = 1; break; \
	 case 7: ret_val = dma7_iop.den = 1; break; \
	 case 8: ret_val = dma8_iop.den = 1; break; \
	 case 9: ret_val = dma9_iop.den = 1; break; \
	 default: ret_val=-1;}\
   ___ret_val;})

#define int dma_disable (DMA_CHANNEL) \
({ int ___ret_val; \
       switch (DMA_CHANNEL) \
        {\
	 case 6: ret_val = !(dma6_iop.den = 0); break; \
	 case 7: ret_val = !(dma7_iop.den = 0); break; \
	 case 8: ret_val = !(dma8_iop.den = 0); break; \
	 case 9: ret_val = !(dma9_iop.den = 0); break; \
	 default: ret_val=-1;}\
   ___ret_val;})


#endif /*  __DMA_DEFINED  */