/*  This program configures the processor for proper operation		*/
/*									*/
/*	Updated on 5/94 by AS						*/
/*									*/

#include "lib_glob.h"

.SEGMENT/CODE	    Code_Space_Name;
.FILE RTL_FILENAME;

.EXTERN	    ___inits;
.GLOBAL	    ___lib_setup_processor;
.GLOBAL	    ___lib_setup_hardware;

___lib_setup_processor:	CALL (PC, ___lib_setup_registers);
			CALL (PC, ___lib_setup_modes);
			CALL (PC, ___lib_setup_memory);	
			RTS;

___lib_clear_irptl:	RTS (DB);
			IRPTL = 0;	/* Clear interrupt latch for hardware*/
			nop;

/* IMPORTANT NOTE: The cache MUST be cleared before ANY PMDA accesses are made! */
___lib_clear_cache:	BIT SET MODE2 0x10; /* Clear cache for rev 0 hardware*/
                        	                /* MODE2 is a latent write */
			RTS (DB);
       			READ CACHE 0;
        		BIT CLR MODE2 0x10;

___lib_setup_registers:	LCNTR=2, do (PC, end_setup) until LCE;
			 M15=-1;
			 M7=-1;
			 M14=1;
			 M6=1;
			 M13=0;
			 M5=0;
			 L0=0;
			 L1=0;
			 L2=0;
			 L3=0;
			 L4=0;
			 L5=0;
			 L6=0;
			 L7=0;
			 L8=0;
			 L9=0;
			 L10=0;
			 L11=0;
			 L12=0;
			 L13=0;
			 L14=0;
			 L15=0;
end_setup:		 BIT SET MODE1 0x78;	/* setup secondary dags too*/

			RTS (DB);
			BIT CLR MODE1 0x78;	/* reset to primary dags*/
			nop;

___lib_setup_modes:	BIT SET MODE1 0x10000;	/*Set to 32-bit mode*/
			RTS (DB);
			BIT SET MODE1 0x01000;	/*Set global interrupt enable*/
			BIT SET MODE1 0x00800;	/*Set interrupt nesting enable*/

___lib_setup_memory:	PX=PM(___inits);	/*Read address of table*/
			R0=PX2;			/*B'cse seg_init is 48 bits*/
			R0=PASS R0, I8=R0;	/*Test no inits, pts to init_seg*/
			IF EQ RTS (DB);		/*Return now from no inits*/
			
zero_dm:		PX=PM(I8,M14);		/*Read number of DM zero inits*/
			R0=PX2;			/*B'cse seg_init is 48 bits*/
			R0=PASS R0;		/*Test for no DM zero inits*/
			IF EQ JUMP (PC, zero_pm); /*No DM zero inits*/
			LCNTR=R0, DO zero_inits_dm UNTIL LCE;
				PX=PM(I8,M14);	/*Read zero init block*/
				I0=PX2;		/*Load pointer to block begin*/
				LCNTR=PX1, DO zero_blk_dm UNTIL LCE;
zero_blk_dm:				DM(I0,M6)=0;
zero_inits_dm:			NOP;		/*Dead instruction*/

zero_pm:		PX=PM(I8,M14);		/*Read number of PM zero inits*/
			R0=PX2;
			R0=PASS R0;             /*Test for no PM zero inits*/ 
                        IF EQ JUMP (PC, init_dm); /*No PM zero inits*/
                        LCNTR=R0, DO zero_inits_pm UNTIL LCE; 
                                PX=PM(I8,M14);  /*Read zero init block*/ 
                                I9=PX2;         /*Load pointer to block begin*/ 
                                LCNTR=PX1, DO zero_blk_pm UNTIL LCE; 
zero_blk_pm:                            PM(I9,M14)=0; 
zero_inits_pm:			NOP;            /*Dead instruction*/ 
init_dm:		PX=PM(I8,M14);		/*Read number of DM blk inits*/
			R0=PX2;
			R0=PASS R0;		/*Check for no DM blk inits*/
			IF EQ JUMP (PC, init_pm); /*Do PM inits*/
			LCNTR=R0, DO blk_inits_dm UNTIL LCE;
				PX=PM(I8,M14);	/*Read address and count */
                         	I0=PX2;		/*Set beginning address*/
				LCNTR=PX1, DO init_blk_dm UNTIL LCE;
					PX=PM(I8,M14);
					R0=PX2;
init_blk_dm:				DM(I0,M6)=R0;
blk_inits_dm:			NOP;		/*Dead instruction*/

init_pm:		PX=PM(I8,M14);		/*Read number of PM blk inits*/
			R0=PX2;
			R0=PASS R0;		/*Check for no PM blk inits*/
			IF EQ JUMP (PC, finish_inits); /*Jump to clean up*/
			LCNTR=R0, DO blk_inits_pm UNTIL LCE;
				PX=PM(I8,M14);	/*Read address and count*/
				I9=PX2;		/*Point to blk begin*/
				LCNTR=PX1, DO init_blk_pm UNTIL LCE;
					PX=PM(I8,M14);
init_blk_pm:				PM(I9,M14)=PX;
blk_inits_pm:			NOP;

finish_inits:		RTS;			/*Just return for now*/

/* IMPORTANT NOTE: The cache MUST be cleared before ANY PMDA accesses are made! */
___lib_setup_hardware:	CALL (PC, ___lib_clear_cache);
                        CALL (PC, ___lib_clear_irptl);
			RTS (DB);
			pm_1=1;
			pm_lnt=0;

.ENDSEG;