{___________________________________________________________________________
EZTEST.ASM		ADSP-21020 EZLAB test program

Selftest program for the ADSP-21020 EZLAB.

 * All LEDs will blink. Press flag0 to go to the memory test.

 * Memory test on all 32K of DM and PM
 	Writes 0x5555555555 and 0xAAAAAAAAAA to every location. If both DM
 	and PM pass the test then the LEDs display a 101 pattern. If DM fails
 	the LEDs will alternate between 100 and 011. If PM fails the LEDs
 	will alternate between 001 and 110. If this passes the program will
 	go to the loopback test
 	 
 * DAC ADC loopback test
 	VINB must be connected to VOUTB. If this test fails the outter LEDS
 	will blink, i.e. an X1X pattern will appear. If this passes the
 	program will go on to the calibration

 * AD28msp02 test and calibration
 	VOUTA must be connected to the left microphone input. To calibrate
 	the input amplifier for 100mV PP, turn R5 until only the middle 
 	LED is on.

Author:	18-Oct-91, Ronnin Yee, Analog Devices Inc. DSP group
	12-Feb-91, Steve Cox, Fix Cache clear code
____________________________________________________________________________}
#include "def21020.h"

#define  OPURNG		0x7e		/* upper target range of input signal */
#define  OPLRNG		0x7a		/* lower target range of input signal */
#define  SPURNG		0x30		/* upper target range of input signal */
#define  SPLRNG		0x28		/* lower target range of input signal */

#define	 ADCMRG		4		/* adc conv. margin of error	      */
#define  PMTSRT		0x1f0		/* indicates PM memtst start address */
						/* must be even */
#define  PMCAP		0x8000		/* size of PM memory starting at 0x0 */
#define  DMCAP		0x8000		/* size of DM memory starting at 0x0 */


.SEGMENT/PM	pm_sram;
.VAR tstpat1 = 0x5555555555;
.VAR tstpat2 = 0xaaaaaaaaaa;
.VAR tstwave[8] = 0x8000000000, 0x8200000000, 0x8400000000, 0x8100000000,
		  0x7f00000000, 0x7d00000000, 0x7b00000000, 0x7e00000000;
.ENDSEG;

.SEGMENT/PM   rst_svc;
        pmwait  =0x1c21;    { pgsz=32K,pmwtstates=0,sw.wtstates only}
        dmwait  =0x70a421;  { pgsz=32K,bank2_dmwtstates=1,sw.wtstates only}

	bit set mode2 0x10; { initialize the cache}
        nop;
	read cache 0;
	bit clr mode2 0x10;

	jump main;
.ENDSEG;

.SEGMENT/PM   irq2_svc;
	rti;
	nop;
	nop;

.ENDSEG;

.SEGMENT/PM   irq3_svc;
	jump irq3_rnt;
	nop;
	nop;
.ENDSEG;

.SEGMENT/PM   tmzh_svc;
	rti;
	nop;
	nop;
.ENDSEG;

.SEGMENT/DM   hip_regs;
.PORT         in_audio_l;
.PORT         in_audio_r;
.PORT         out_audio_l;
.PORT         out_audio_r;
.PORT         status_2111;
.PORT         command_2111;
.ENDSEG;

.SEGMENT/DM   dac_a;
.PORT         dac_a;
.ENDSEG;

.SEGMENT/DM   dac_b;
.PORT         dac_b;
.ENDSEG;

.SEGMENT/DM   adc_a;
.PORT         adc_a;
.ENDSEG;

.SEGMENT/DM   adc_b;
.PORT         adc_b;
.ENDSEG;

{___________________________________________________________________________}
.SEGMENT/PM   pm_sram;

main:   bit set mode2 IRQ2E|IRQ3E|FLG1O|FLG2O|FLG3O;
        nop;
	bit clr astat FLG1|FLG2|FLG3;
	mode1=ALUSAT;			{set saturation mode}

    {test flag0 button & LEDs}
	do wait until flag0_in;
	    lcntr = 0x400000;
	    do (pc,1) until lce;
		if flag0_in jump (pc,1) (la);
	    bit tgl astat FLG1|FLG2|FLG3;
wait:	    nop;

    {test 21020 memory}
	call memtest;

   {Wow, the memory passed sucessfully}
	bit clr astat FLG1|FLG2|FLG3;
	bit set astat FLG1|FLG3;	

	bit set imask IRQ2I;
	irptl=0x0;
	bit set mode1 IRPTEN;

    {test irq2 button}
	idle;

    {test DAC_B, ADC_B}
	call dactest;

    {init for irq3 service routine}
	b8=tstwave;
	m8=1;
	l8=8;

	irptl=0x0;
	imask=IRQ3I;

	r13=0;			{clear max and min}
	r14=0;
	r15=256;		{average over 256 samples}

    {wait around and let irq3_svc routine do the work}
	idle;
	jump (pc,-1);
	nop;
	nop;

{___________________________________________________________________________}
{Test the AD7769 dual DACs and ADC}
dactest:
    {test adc_b and dac_b}
	r0=0x80000000;			{dac input}
	r1=0x80;			{adc expected result}
	call dac_cnv;

	r0=0xe0000000;			{dac input}
	r1=0xba;			{adc expected result}
	call dac_cnv;

	r0=0x10000000;			{dac input}
	r1=0x3e;			{adc expected result}
	call dac_cnv;

	rts;

{___________________________________________________________________________}
{ set dac_b to level r0, and compare r1 with the adc_b answer}
dac_cnv:
	dm(dac_b)=r0;			{write dac_b}
	lcntr=200, do (pc,1) until lce;
	    nop;			{wait for output to settle}

	dm(adc_b)=r1;			{dummy write to start conversion}
	lcntr=200, do (pc,1) until lce;
	    nop;			{wait for conversion to finish}
	r4=dm(adc_b);			{read data from converter}
	
    {check result}
	r3=ADCMRG;			{margin of adc error}
	r4=lshift r4 by -24;
	r5=r4-r1;
	r5=abs r5;
	comp(r5,r3);
	if ge jump dac_err;

	rts;

{___________________________________________________________________________}
dac_err:
	bit clr astat FLG1|FLG2|FLG3;
	r0=pass r0;	
	if eq jump deadend;

err2:	bit set astat FLG2;

deadend:
	lcntr=0x100000;
	do (pc,1) until lce;
	    nop;
	bit tgl astat FLG1|FLG3;
	jump deadend;

{___________________________________________________________________________}
{Test the 21020 memory spaces by writing and reading *tstpat1*,*tstpat2* and
 then writing and reading *tstpat2*,*tstpat1* to both pm and dm.}
memtest:
	r8=pm(tstpat1);
	r9=pm(tstpat2);

   {check the integrity of *tstpat1*}	
	r2=0x55555555;
	f1=f8-f2;
	r0=0x48aa0000;
	comp(r0,r1);
	if ne call memfail;

   {check the integrity of *tstpat2*}	
	r2=0xaaaaaaaa;
	f1=f9-f2;
	r0=0x9eaa0000;
	comp(r0,r1);
	if ne call memfail;

    {proceed with memory testing}
    {test dm}
	r4=0x0;			{flag dm test}
	call dmtst;

	r10=r8;			{switch *tstpat1* and *tstpat2*}
	r8=r9;
	r9=r10;
	call dmtst;

   {test pm}
	r4=0x1;			{flag pm test}
	call pmtst;

	r10=r8;			{switch *tstpat1* and *tstpat2*}
	r8=r9;
	r9=r10;
	call pmtst;

	rts;
	nop;
	nop;

{___________________________________________________________________________}
{failure, give error location}
memfail: 
	bit clr astat FLG1|FLG2|FLG3;
	r4=pass r4;			{test which memory space}
	if ne jump pmfail;		{if r2<>0, then pm failure}

dmfail:	bit set astat FLG1;		{   else it is a dmfail}
	r0=i0;
	jump fcont;

pmfail:	bit set astat FLG3;
	r0=i8;
	
fcont:	do (pc,5) until forever;
	    lcntr = 0x200000;
	    do (pc,1) until lce;
		nop;
	    bit tgl astat FLG1|FLG2|FLG3;
	    nop;

	nop;		{add code here if want location}
	nop;

{___________________________________________________________________________}

{dm test subroutine, takes patterns in r8, r9}
dmtst:	b0=0x0;
	l0=DMCAP;
	m0=1;
	lcntr=DMCAP/2;
	do dmwrite until lce;
	    dm(i0,m0)=r8;		{write first pattern}
dmwrite:    dm(i0,m0)=r9;		{write second pattern}

	lcntr=DMCAP/2;
	do dmtstlp until lce;
	    f10=dm(i0,m0);
	    comp(f8,f10);		{note that this is a fp compare}
	    if ne call memfail;
	    f11=dm(i0,m0);
	    comp(f9,f11);		{note that this is a fp compare}
dmtstlp:    if ne call memfail;

	rts;
	nop;
	nop;

{___________________________________________________________________________}
{tests pm memory, puts in patterns from r8 & r9}
pmtst:	b8=PMTSRT;
	l8=PMCAP-PMTSRT;
	m8=1;
	lcntr=(PMCAP-PMTSRT)/2;

    {write the patterns into pm memory}
	do pmwrite until lce;
	    px1=r8;
	    px2=r8;
	    pm(i8,m8)=px;
	    px1=r9;
	    px2=r9;
pmwrite:    pm(i8,m8)=px;

    {test patterns in pm memory}
	r10=0x0000ffff;			{mask for lower 16 bits}
	r14=r8 and r10;			{generate patterns for lower 16 bits}
	r15=r9 and r10;
	lcntr=(PMCAP-PMTSRT)/2;
	do pmtstlp until lce;
	    px=pm(i8,m8);
	    r10=px2;
	    r11=px1;
	    comp(r8,r10);		{note this is a fixed compare}
	    if ne call memfail;
	    comp(r14,r11);		{note this is a fixed compare}
	    if ne call memfail;

	    px=pm(i8,m8);
	    r10=px2;
	    r11=px1;
	    comp(r9,r10);		{note this is a fixed compare}
	    if ne call memfail;
	    comp(r15,r11);		{note this is a fixed compare}
pmtstlp:    if ne call memfail;

	rts;
	nop;
	nop;

{___________________________________________________________________________}
{Tests DAC, ADC, OPAMP, power-amp and msp02.  Also facilitates tuning of pots}
irq3_rnt:
	r0=dm(in_audio_l);	{feed data through the MSP02}
	dm(out_audio_l)=r0;

    {data output from DAC A into left_mic_in}
	r1=pm(i8,m8);
	dm(dac_a)=r1;

    {get adc_a input}
	r2=dm(adc_a);
	dm(adc_a)=r2;		{start next conversion}

    {get adc_a max and min}
	r11=min(r2,r11);
	r12=max(r2,r12);

    {get MSP02 max and min}
	r13=min(r0,r13);
	r14=max(r0,r14);

	r15=r15-1;
	if ne rti;		{is it min, max over 512 sample yet?}

tune:	pop sts;		{pop sts stack so we can have flag changes}
	bit clr astat FLG1|FLG2|FLG3;

	r6=r11;
	r7=r12;
	if flag0_in jump maxi (db);  {if flag0, adjust speaker}
	    r4=SPURNG;
	    r5=SPLRNG;

	r6=r13;
	r7=r14;
	r4=OPURNG;
	r5=OPLRNG;

mini:	r0=abs r6;		{set flags based on min sample}	
	r0=lshift r0 by -24;
	comp(r0,r4);
	if le jump (pc,3);
	bit set astat FLG1;		{too much gain on opamp}
	jump maxi;

	comp(r0,r5);
	if lt jump (pc,3);
	bit set astat FLG2;		{target hit}
	jump maxi;

	bit set astat FLG3;		{not enough gain}

maxi:	r0=lshift r7 by -24;
	comp(r0,r4);		{set flags based on max sample}
	if le jump (pc,3);
	bit set astat FLG1;		{too much gain on opamp}
	jump cln_up;

	comp(r0,r5);
	if lt jump (pc,3);
	bit set astat FLG2;		{target hit}
	jump cln_up;

	bit set astat FLG3;		{not enough gain}

cln_up:	push sts;		{push sts stack to keep FLAG changes}
	r11=0;			{clear max and min}
	r12=0;
	r13=0;
	r14=0;
	r15=256;		{average over 256 samples}
	rti;
	nop;
	nop;

.ENDSEG;