/*------------------------------------------------------------------------------ sreg_bits.h - STATUS REGISTER BIT DEFINITIONS This include file contains a list of "defines" to enable the programmer to use symbolic names for all of the system register bits for the 21020. ------------------------------------------------------------------------------*/ /* MODE1 register */ #define BR0 0x00000002 /* Bit 1: Bit-reverse for I0 (uses DMS0- only ) */ #define SRCU 0x00000004 /* Bit 2: Alt. register select for comp. units */ #define SRD1H 0x00000008 /* Bit 3: DAG1 alt. register select (7-4) */ #define SRD1L 0x00000010 /* Bit 4: DAG1 alt. register select (3-0) */ #define SRD2H 0x00000020 /* Bit 5: DAG2 alt. register select (15-12) */ #define SRD2L 0x00000040 /* Bit 6: DAG2 alt. register select (11-8) */ #define SRRFH 0x00000080 /* Bit 7: Register file alt. select for R(15-8) */ #define SRRFL 0x00000400 /* Bit 10: Register file alt. select for R(7-0) */ #define NESTM 0x00000800 /* Bit 11: Interrupt nesting enable */ #define IRPTEN 0x00001000 /* Bit 12: Global interrupt enable */ #define ALUSAT 0x00002000 /* Bit 13: Enable ALU fixed-pt. saturation */ #define TRUNC 0x00008000 /* Bit 15: 1=fltg-pt. truncation 0=Rnd to nearest */ #define RND32 0x00010000 /* Bit 16: 1=32-bit fltg-pt.rounding 0=40-bit rnd */ /* MODE2 register */ #define IRQ0E 0x00000001 /* Bit 0: IRQ0- 1=edge sens. 0=level sens. */ #define IRQ1E 0x00000002 /* Bit 1: IRQ1- 1=edge sens. 0=level sens. */ #define IRQ2E 0x00000004 /* Bit 2: IRQ2- 1=edge sens. 0=level sens. */ #define IRQ3E 0x00000008 /* Bit 3: IRQ3- 1=edge sens. 0=level sens. */ #define CADIS 0x00000010 /* Bit 4: Cache disable */ #define TIMEN 0x00000020 /* Bit 5: Timer enable */ #define FLG0O 0x00008000 /* Bit 15: FLAG0 1=output 0=input */ #define FLG1O 0x00010000 /* Bit 16: FLAG1 1=output 0=input */ #define FLG2O 0x00020000 /* Bit 17: FLAG2 1=output 0=input */ #define FLG3O 0x00040000 /* Bit 18: FLAG3 1=output 0=input */ #define CAFRZ 0x00080000 /* Bit 19: Cache freeze */ /* ASTAT register */ #define AZ 0x00000001 /* Bit 0: ALU result zero or fltg-pt. underflow */ #define AV 0x00000002 /* Bit 1: ALU overflow */ #define AN 0x00000004 /* Bit 2: ALU result negative */ #define AC 0x00000008 /* Bit 3: ALU fixed-pt. carry */ #define AS 0x00000010 /* Bit 4: ALU X input sign (ABS and MANT ops) */ #define AI 0x00000020 /* Bit 5: ALU fltg-pt. invalid operation */ #define MN 0x00000040 /* Bit 6: Multiplier result negative */ #define MV 0x00000080 /* Bit 7: Multiplier overflow */ #define MU 0x00000100 /* Bit 8: Multiplier fltg-pt. underflow */ #define MI 0x00000200 /* Bit 9: Multiplier fltg-pt. invalid operation */ #define AF 0x00000400 /* Bit 10: ALU fltg-pt. operation */ #define SV 0x00000800 /* Bit 11: Shifter overflow */ #define SZ 0x00001000 /* Bit 12: Shifter result zero */ #define SS 0x00002000 /* Bit 13: Shifter input sign */ #define BTF 0x00040000 /* Bit 18: Bit test flag for system registers */ #define FLG0 0x00080000 /* Bit 19: FLAG0 value */ #define FLG1 0x00100000 /* Bit 20: FLAG1 value */ #define FLG2 0x00200000 /* Bit 21: FLAG2 value */ #define FLG3 0x00400000 /* Bit 22: FLAG3 value */ /* STKY register */ #define AUS 0x00000001 /* Bit 0: ALU fltg-pt. underflow */ #define AVS 0x00000002 /* Bit 1: ALU fltg-pt. overflow */ #define AOS 0x00000004 /* Bit 2: ALU fixed-pt. overflow */ #define AIS 0x00000020 /* Bit 5: ALU fltg-pt. invalid operation */ #define MOS 0x00000040 /* Bit 6: Multiplier fixed-pt. overflow */ #define MVS 0x00000080 /* Bit 7: Multiplier fltg-pt. overflow */ #define MUS 0x00000100 /* Bit 8: Multiplier fltg-pt. underflow */ #define MIS 0x00000200 /* Bit 9: Multiplier fltg-pt. invalid operation */ #define CB7S 0x00020000 /* Bit 17: DAG1 circular buffer 7 overflow */ #define CB15S 0x00040000 /* Bit 18: DAG2 circular buffer 15 overflow */ #define PCFL 0x00200000 /* Bit 21: PC stack full */ #define PCEM 0x00400000 /* Bit 22: PC stack empty */ #define SSOV 0x00800000 /* Bit 23: Status stack overflow (MODE1 and ASTAT) */ #define SSEM 0x01000000 /* Bit 24: Status stack empty */ #define LSOV 0x02000000 /* Bit 25: Loop stack overflow */ #define LSEM 0x04000000 /* Bit 26: Loop stack empty */ /* IRPTL and IMASK and IMASKP registers */ #define EMUI 0x00000001 /* Bit 0: Address: 00: Emulator (S/W breakpt.) */ #define RSTI 0x00000002 /* Bit 1: Address: 08: Reset */ #define SOVFI 0x00000008 /* Bit 3: Address: 18: Stack overflow */ #define TMZHI 0x00000010 /* Bit 4: Address: 20: Timer = 0 (high priority) */ #define IRQ3I 0x00000020 /* Bit 5: Address: 28: IRQ3- asserted */ #define IRQ2I 0x00000040 /* Bit 6: Address: 30: IRQ2- asserted */ #define IRQ1I 0x00000080 /* Bit 7: Address: 38: IRQ1- asserted */ #define IRQ0I 0x00000100 /* Bit 8: Address: 40: IRQ0- asserted */ #define CB7I 0x00000800 /* Bit 11: Address: 58: Circ. buffer 7 overflow */ #define CB15I 0x00001000 /* Bit 12: Address: 60: Circ. buffer 15 overflow */ #define TMZLI 0x00004000 /* Bit 14: Address: 70: Timer = 0 (low priority) */ #define FIXI 0x00008000 /* Bit 15: Address: 78: Fixed-pt. overflow */ #define FLTOI 0x00010000 /* Bit 16: Address: 80: fltg-pt. overflow */ #define FLTUI 0x00020000 /* Bit 17: Address: 88: fltg-pt. underflow */ #define FLTII 0x00040000 /* Bit 18: Address: 90: fltg-pt. invalid */ #define SFT0I 0x01000000 /* Bit 24: Address: C0: software int 0 */ #define SFT1I 0x02000000 /* Bit 25: Address: C8: software int 1 */ #define SFT2I 0x04000000 /* Bit 26: Address: D0: software int 2 */ #define SFT3I 0x08000000 /* Bit 27: Address: D8: software int 3 */ #define SFT4I 0x10000000 /* Bit 28: Address: E0: software int 4 */ #define SFT5I 0x20000000 /* Bit 29: Address: E8: software int 5 */ #define SFT6I 0x40000000 /* Bit 30: Address: F0: software int 6 */ #define SFT7I 0x80000000 /* Bit 31: Address: F8: software int 7 */