{ N-tap finite impulse response filter (FIR) for real data Calling Parameters --- fir --- f0 = input sample x(n) r1 = TAPS-3 b0 = address of delay line buffer b8 = address of coefficient buffer m0, m8 = 1 l0, l8 = TAPS --- fir_init --- r0 = TAPS b0 = address of delay line buffer m0 = 1 l0 = TAPS Returned Values f0 = output sample y(n) fir delay line zeroed fir_init Register File Altered: f0, f4, f8, f12 fir -none- fir_init Data Address Generator Altered: i0 fir -none- fir_init Benchmark 9 + TAPS cycles fir (8 + TAPS-3 + 4 cache misses) 4 + TAPS cycles fir_init (incl. non-delayed rts) Memory Usage --- fir --- 9 words instructions in PM TAPS coefficients in PM TAPS delay line storage in DM --- fir_init --- 3 words instructions in PM TAPS delay line storage in DM "fir.asm" Analog Devices, Inc. DSP Applications P.O.Box 9106 Norwood, MA 02062 Christoph D. Cavigioli ... 25-Apr-1991 } .GLOBAL fir, fir_init; .EXTERN coefs, dline; .SEGMENT /PM pm_code; {#1 store input sample (f0) in delay line } { } { D = delay line storage element } { C = filter coefficient } { P = product } { S = accumulated sum } { } { ____ L O O P P R O L O G U E___________________________________________} {#2 get D[0], get C[0] } {#3 P[0]=D[0]*C[0], (S[0]=P[0]) get D[1], get C[1] } {#4 P[1]=D[1]*C[1], get D[2], get C[2] } { } {#5____ L O O P____B O D Y__________________________________________________} {#6 P[n]=D[n]*C[n], S[n-1]=S[n-2]+P[n-1], get D[n+1], get C[n+1] } { } {#7____ L O O P____E P I L O G U E__________________________________________} {#8 P[N-1]=D[N-1]*C[N-1], S[N-2]=S[N-3]+P[N-2] } {#9 S[N-1]=S[N-2]+P[N-1] } { output (S[N-1]) in f0 } fir: dm(i0,m0)=f0; { #1 } f0=dm(i0,m0), f4=pm(i8,m8); { #2 } f8=f0*f4, f0=dm(i0,m0), f4=pm(i8,m8); { #3 } f12=f0*f4, f0=dm(i0,m0), f4=pm(i8,m8); { #4 } lcntr=r1, do macs until lce; { #5 } macs: f12=f0*f4, f8=f8+f12, f0=dm(i0,m0), f4=pm(i8,m8); { #6 } rts (db); { #7 } f12=f0*f4, f8=f8+f12; { #8 } f0=f8+f12; { #9 } fir_init: lcntr=r0, do zero until lce; zero: dm(i0,m0)=0; rts; .ENDSEG;