Motorola DSP56300 Assembler Version 6.2.0 99-09-16 10:39:03 60hzdemo2.asm Page 1 1 page 132,60 2 ;**************************************************************************** 3 ; 60HZDEMO.ASM 4 ; Example program to demonstrate the difference between 24-bit data 5 ; capabilities and 16-bit data capabilities 6 ; 7 ; Copyright (c) MOTOROLA 1994 8 ; Semiconductor Products Sector 9 ; Digital Signal Processing Division 10 ; 11 ; ver. 1.1 3/16/95 Placed coefficients on modulo boundaries. Moved the 12 ; "state" variable locations. Set sine amplitude to 0.3. 13 ; 6/20/96 PFS Modified for 56303 14 ; 15 ;****************************************************************************** 16 ; This code demonstrates the benefits of a 24-bit architecture over that of 17 ; a 16-bit architecture. The demonstration runs on the DSP56303EVM evaluation 18 ; module. An external audio signal is input through the microphone connector 19 ; on the EVM. A 60 Hz tone is generated by the DSP (via a digital oscillator) 20 ; and then added to the digitized audio signal. The resulting data is then 21 ; sent through a filter with one of three sets of coefficients. The first 22 ; set of coefficients is located at location y:no_filter and performs no 23 ; filtering at all, simply allowing the corrupted signal to pass. This first 24 ; set of coefficients are used by the filter when the demo first begins or 25 ; following the IRQB (IRQB). The second set of coefficients 26 ; (located at y:coef_24) are 24-bit coefficients that make up a 60 Hz notch 27 ; filter which removes the 60 Hz portion of the corrupted signal. This second 28 ; set of coefficients are used following the external interrupt A (IRQA). The 29 ; final set of coefficients (located at y:coeff_16) are the same coefficients 30 ; as those for the 24-bit filter, only rounded to 16 bits. These 16-bit 31 ; coefficients are used by the filter following the external interrupt D 32 ; (IRQD). 33 ;****************************************************************************** 34 1099 1100 1101 4.800000E+004 Fs set 48000.0 ;Specify sampling frequency. 1102 3.141593E+000 PI set 2.0*@asn(1.0) ;Compute PI as 2.0*arcsin(1.0) 1103 1.745329E-002 factor set PI/180.0 ;Multiplier for degrees to radians 1104 000012 eighteen set 18 1105 000020 hex_twenty set $20 1106 1107 ;****************************************************************************** 1108 ; Specification for tone a. 1109 6.000000E+001 freq_a set 60.0 ;Specify frequency in Hertz. 1110 4.500000E-001 phi_a set 360.0*(freq_a/Fs) ;Compute phi 1111 0.000000E+000 phase_a set 0.0 ;Specify the phase angle in 1112 ; degrees (-180 -- +180). 1113 3.000000E-001 amp_a set 0.3 ;Specify amplitude (0-1). 1114 -9.000000E-001 theta2_a set (phase_a-(2.0*phi_a)) ;Compute theta2 1115 -4.500000E-001 theta1_a set (phase_a-phi_a) ;Compute theta1 1116 -4.712195E-003 s2_a set amp_a*@sin(factor*theta2_a) ;Compute s2 1117 -2.356170E-003 s1_a set amp_a*@sin(factor*theta1_a) ;Compute s1 1118 9.999692E-001 coeff_a set @cos(factor*phi_a) ;Compute rcoef in 2:14 format 1119 1120 Motorola DSP56300 Assembler Version 6.2.0 99-09-16 10:39:03 60hzdemo2.asm Page 2 1121 ;****************************************************************************** 1122 ; These three interrupts (IRQA, IRQD, and IRQB) load the program memory location 1123 ; of the appropriate filter routine (24-bit, 16-bit, or NMI). 1124 ; 1125 ; org p:$0 1126 ; jmp START 1127 ; jsr no_filter_isr ; Load code pointer. 1128 P:000010 org p:$10 ; IRQA--Filter in 24 bit mode. 1129 P:000010 0BF080 jsr coef_24_isr ; Load code pointer. 00017C 1130 P:000012 org p:$12 ; IRQB--no filtering 1131 P:000012 0BF080 jsr no_filter_isr ; Load code pointer. 00017A 1132 P:000016 org p:$16 ; IRQD--Filter in 16 bit mode. 1133 P:000016 0BF080 jsr no_filter_isr 00017A 1134 ; jsr coef_16_isr ; Load code pointer. 1135 1136 ; org p:$30 1137 ; jsr ssi_rx_isr ;- ESSI0 Receive Data 1138 ; jsr ssi_rxe_isr ;- ESSI0 Receive Data w/ Exception Status 1139 ; jsr ssi_rxls_isr ;- ESSI0 Receive last slot 1140 ; jsr ssi_tx_isr ;- ESSI0 Transmit Data 1141 ; jsr ssi_txe_isr ;- ESSI0 Transmit Data w/ Exception Status 1142 ; jsr ssi_txls_isr ;- ESSI0 Transmit last slot 1143 1144 1145 000003 nsec equ 3 ;number of second order sections 1146 000001 scount equ 1 ;final shift count 1147 1148 1149 ;****************************************************************************** 1150 ;---Buffer for talking to the CS4215 1151 1152 X:000000 org x:0 1153 1154 RX_BUFF_BASE 1155 000000 equ * 1156 RX_data_1_2 1157 X:000000 ds 1 ;data time slot 1/2 for RX ISR 1158 RX_data_3_4 1159 X:000001 ds 1 ;data time slot 3/4 for RX ISR 1160 RX_data_5_6 1161 X:000002 ds 1 ;data time slot 5/6 for RX ISR 1162 RX_data_7_8 1163 X:000003 ds 1 ;data time slot 7/8 for RX ISR 1164 1165 1166 TX_BUFF_BASE 1167 000004 equ * 1168 TX_data_1_2 1169 X:000004 ds 1 ;data time slot 1/2 for TX ISR 1170 TX_data_3_4 1171 X:000005 ds 1 ;data time slot 3/4 for TX ISR 1172 TX_data_5_6 1173 X:000006 ds 1 ;data time slot 5/6 for TX ISR Motorola DSP56300 Assembler Version 6.2.0 99-09-16 10:39:03 60hzdemo2.asm Page 3 1174 TX_data_7_8 1175 X:000007 ds 1 ;data time slot 7/8 for TX ISR 1176 1177 X:000008 RX_PTR ds 1 ; Pointer for rx buffer 1178 X:000009 TX_PTR ds 1 ; Pointer for tx buffer 1179 1180 1181 1182 X:00000A org x: 1183 DOSC_BUFF_BASE 1184 00000A EQU * 1185 X:00000A coeff ds 1 ; data location for osc. a's coeff. 1186 X:00000B s1 ds 1 ; data location for osc. a's sr1. 1187 X:00000C s2 ds 1 ; data location for osc. a's sr2. 1188 X:00000D LEFT_HUM ds 1 ;storage for Left Signal + Hum 1189 X:00000E RIGHT_HUM ds 1 ;storage for Left Signal + Hum 1190 X:000010 org x:$10 1191 X:000010 state1 dsm nsec 1192 X:00001C org x:$1c 1193 X:00001C state1_r dsm nsec 1194 X:000020 org x:$20 1195 X:000020 state2 dsm nsec 1196 X:00002C org x:$2c 1197 X:00002C state2_r dsm nsec 1198 1199 ;****************************************************************************** 1200 Y:000000 org y: 1201 coef_24 1202 Y:000000 dc $3FFD61 ;b(*,0)/2 =0.49992001 section number 1 1203 Y:000001 dc $800641 ;b(*,1)/2 =-.99980915 section number 1 1204 Y:000002 dc $7FF9C0 ;a(*,1)/2 =0.99980927 section number 1 1205 Y:000003 dc $3FFD61 ;b(*,2)/2 =0.49992001 section number 1 1206 Y:000004 dc $C0053E ;a(*,2)/2 =-.49984002 section number 1 1207 Y:000005 dc $3E3C48 ;b(*,0)/2 =0.48621464 section number 2 1208 Y:000006 dc $83886C ;b(*,1)/2 =-.97239923 section number 2 1209 Y:000007 dc $7FFDB8 ;a(*,1)/2 =0.99993038 section number 2 1210 Y:000008 dc $3E3C48 ;b(*,2)/2 =0.48621464 section number 2 1211 Y:000009 dc $C0013F ;a(*,2)/2 =-.49996197 section number 2 1212 Y:00000A dc $20E7A1 ;b(*,0)/ 4 =0.25706875 section number 3 1213 Y:00000B dc $BE3142 ;b(*,1)/ 4 =-.51412177 section number 3 1214 Y:00000C dc $7FFDCE ;a(*,1)/ 2 =0.99993300 section number 3 1215 Y:00000D dc $20E7A1 ;b(*,2)/ 4 =0.25706875 section number 3 1216 Y:00000E dc $C00136 ;a(*,2)/ 2 =-.49996305 section number 3 1217 Y:00000F dc 0 1218 1219 coef_16 1220 Y:000010 dc $3FFD00 ;b(*,0)/2 =0.49991 section number 1 1221 Y:000011 dc $800600 ;b(*,1)/2 =-.99982 section number 1 1222 Y:000012 dc $7FFA00 ;a(*,1)/2 =0.99982 section number 1 1223 Y:000013 dc $3FFD00 ;b(*,2)/2 =0.49991 section number 1 1224 Y:000014 dc $C00500 ;a(*,2)/2 =-.49985 section number 1 1225 Y:000015 dc $3E3C00 ;b(*,0)/2 =0.48621 section number 2 1226 Y:000016 dc $838800 ;b(*,1)/2 =-.97241 section number 2 1227 Y:000017 dc $7FFE00 ;a(*,1)/2 =0.99994 section number 2 1228 Y:000018 dc $3E3C00 ;b(*,2)/2 =0.48621 section number 2 1229 Y:000019 dc $C00100 ;a(*,2)/2 =-.49997 section number 2 Motorola DSP56300 Assembler Version 6.2.0 99-09-16 10:39:03 60hzdemo2.asm Page 4 1230 Y:00001A dc $20E800 ;b(*,0)/ 4 =0.25708 section number 3 1231 Y:00001B dc $BE3100 ;b(*,1)/ 4 =-.51413 section number 3 1232 Y:00001C dc $7FFE00 ;a(*,1)/ 2 =0.99994 section number 3 1233 Y:00001D dc $20E800 ;b(*,2)/ 4 =0.25708 section number 3 1234 Y:00001E dc $C00100 ;a(*,2)/ 2 =-.49997 section number 3 1235 Y:00001F dc 0 1236 1237 no_filter 1238 Y:000020 dc $400000 ;b(*,0)/2 =0.50000000 section number 1 1239 Y:000021 dc $000000 ;b(*,1)/2 =0.00000000 section number 1 1240 Y:000022 dc $000000 ;a(*,1)/2 =0.00000000 section number 1 1241 Y:000023 dc $000000 ;b(*,2)/2 =0.00000000 section number 1 1242 Y:000024 dc $000000 ;a(*,2)/2 =0.00000000 section number 1 1243 Y:000025 dc $400000 ;b(*,0)/2 =0.50000000 section number 2 1244 Y:000026 dc $000000 ;b(*,1)/2 =0.00000000 section number 2 1245 Y:000027 dc $000000 ;a(*,1)/2 =0.00000000 section number 2 1246 Y:000028 dc $000000 ;b(*,2)/2 =0.00000000 section number 2 1247 Y:000029 dc $000000 ;a(*,2)/2 =0.00000000 section number 2 1248 Y:00002A dc $200000 ;b(*,0)/ 4 =0.25000000 section number 3 1249 Y:00002B dc $000000 ;b(*,1)/ 4 =0.00000000 section number 3 1250 Y:00002C dc $000000 ;a(*,1)/ 2 =0.00000000 section number 3 1251 Y:00002D dc $000000 ;b(*,2)/ 4 =0.00000000 section number 3 1252 Y:00002E dc $000000 ;a(*,2)/ 2 =0.00000000 section number 3 1253 1254 1255 Y:00002F left_a ds 1 1256 Y:000030 left_y0 ds 1 1257 Y:000031 right_a ds 1 1258 Y:000032 right_y0 ds 1 1259 1260 1261 ;****************************************************************************** 1262 ;TONE_OUTPUT EQU HEADPHONE_EN+LINEOUT_EN+(4*LEFT_ATTN)+(4*RIGHT_ATTN) 1263 ;TONE_INPUT EQU MIC_IN_SELECT+(15*MONITOR_ATTN) 1264 ;CTRL_WD_12 equ NO_PREAMP+HI_PASS_FILT+SAMP_RATE_48+STEREO+DATA_16 ;CLB=0 1265 ;CTRL_WD_34 equ IMMED_3STATE+XTAL1_SELECT+BITS_64+CODEC_MASTER 1266 ;CTRL_WD_56 equ $000000 1267 ;CTRL_WD_78 equ $000000 1268 1269 000300 CTRL_WD_12 equ MIN_LEFT_ATTN+MIN_RIGHT_ATTN+LIN2+RIN2 1270 000000 CTRL_WD_34 equ MIN_LEFT_GAIN+MIN_RIGHT_GAIN 1271 1272 1273 P:000100 org p:$100 1274 1275 1276 START 1277 main 1278 1279 ; Initialize SC0, SC1 as GPIO inputs 1280 P:000100 08F4BD movep #$040003,x:M_PCTL ; PLL = 4 x 16.9344Mhz = 67.7Mhz 040003 1281 P:000102 08F4BB movep #$012421,x:M_BCR ; one wait state for external spaces 012421 1282 P:000104 08F4BF movep #$000E07,X:M_IPRC ; IRQA/IRQD/SSI level 3 interrupts. edge sensitive 000E07 Motorola DSP56300 Assembler Version 6.2.0 99-09-16 10:39:03 60hzdemo2.asm Page 5 1283 1284 P:000106 0500BA move #0,omr 1285 P:000107 0500BB movec #0,sp 1286 1287 1288 P:000108 364000 move #$40,r6 ; initialize stack pointer 1289 P:000109 05F426 move #-1,m6 ; linear addressing FFFFFF 1290 P:00010B 240000 move #RX_BUFF_BASE,x0 1291 P:00010C 440800 move x0,x:RX_PTR ; Initialize the rx pointer 1292 P:00010D 240400 move #TX_BUFF_BASE,x0 1293 P:00010E 440900 move x0,x:TX_PTR ; Initialize the tx pointer 1294 1295 1296 ; --- INIT THE CODEC --- 1297 1298 P:00010F 0BF080 jsr ada_init ; Jump to initialize the codec 000180 1299 1300 1301 ; Initialize Filter Parameters 1302 P:000111 331000 move #state1,r3 ;point to filter state1 1303 P:000112 312000 move #state2,r1 ;point to filter state2 1304 P:000113 342000 move #no_filter,r4 ;Initialize for unity filter. 1305 P:000114 050EA4 move #5*nsec-1,m4 ;addressing modulo 5*nsec 1306 P:000115 200013 clr a ;initialize internal state storage **** 1307 [60hzdemo2.asm 238]: WARNING --- Pipeline stall reading register written in previous instruction (Y data move field) 1307 P:000116 5E2F00 move a,y:left_a 1308 P:000117 5E3100 move a,y:right_a 1309 P:000118 0604A0 rep #4 ;* zero state1 (BAK) 1310 P:000119 565B00 move a,x:(r3)+ ;* 1311 P:00011A 0604A0 rep #4 ;* zero state2 (BAK) 1312 P:00011B 565900 move a,x:(r1)+ ;* 1313 P:00011C 331C00 move #state1_r,r3 ;point to filter state1 (BAK) 1314 P:00011D 312C00 move #state2_r,r1 ;point to filter state2 (BAK) 1315 P:00011E 0604A0 rep #4 ;* zero state1_r (BAK) 1316 P:00011F 565B00 move a,x:(r3)+ ;* (BAK) 1317 P:000120 0604A0 rep #4 ;* zero state2_r (BAK) 1318 P:000121 565900 move a,x:(r1)+ ;* (BAK) 1319 P:000122 4EDC00 move y:(r4)+,y0 ;a must be initially zero ,y0=b10/2 1320 P:000123 4E3000 move y0,y:left_y0 1321 P:000124 4E3200 move y0,y:right_y0 1322 P:000125 67F400 move #filter,r7 ; Load filter location. 000170 1323 1324 ; Initialize Digital Oscillator Parameters 1325 P:000127 07F436 movep #$FF310C,x:M_CRB0 ; Enable the SSI interrupts. FF310C 1326 P:000129 44F400 move #coeff_a,x0 7FFEFD 1327 P:00012B 440A00 move x0,x:DOSC_BUFF_BASE ; Load coeff. for osc. a. 1328 P:00012C 44F400 move #s1_a,x0 FFB2CB 1329 P:00012E 440B00 move x0,x:DOSC_BUFF_BASE+1 ; Load s1 for osc. a. 1330 P:00012F 44F400 move #s2_a,x0 FF6597 Motorola DSP56300 Assembler Version 6.2.0 99-09-16 10:39:03 60hzdemo2.asm Page 6 1331 P:000131 440C00 move x0,x:DOSC_BUFF_BASE+2 ; Load s2 for osc. a. 1332 1333 ; Main Loop 1334 loop_1 1335 P:000132 01B7A2 jset #2,x:M_SSISR0,* ; Wait for frame sync to pass. 000132 1336 P:000134 01B782 jclr #2,x:M_SSISR0,* ; Wait for frame sync. 000134 1337 1338 1339 P:000136 46F400 move #CTRL_WD_12,y0 ; headphones, line out, mute spkr, no attn. 000300 1340 P:000138 460600 move y0,x:TX_BUFF_BASE+2 1341 P:000139 260000 move #CTRL_WD_34,y0 ; no input gain, monitor mute 1342 P:00013A 460700 move y0,x:TX_BUFF_BASE+3 1343 P:00013B 350A00 move #DOSC_BUFF_BASE,r5 ; Load pointer to osc's coeff, sr1 and sr2 1344 P:00013C 0BF080 jsr dosc_sin ; Call oscillator routine. 000150 1345 P:00013E 21C400 move a,x0 ; Copy new tone into x0. 1346 P:00013F 568000 move x:RX_BUFF_BASE,a ; Load the left channel input. 1347 P:000140 200040 add x0,a ; Add the tone. **** 1348 [60hzdemo2.asm 279]: WARNING --- Pipeline stall reading register written in previous instruction (X data move field) 1348 P:000141 560D00 move a,x:LEFT_HUM 1349 P:000142 578100 move x:RX_BUFF_BASE+1,b ; Load the right channel input. 1350 P:000143 200048 add x0,b ; Add the tone. **** 1351 [60hzdemo2.asm 282]: WARNING --- Pipeline stall reading register written in previous instruction (X data move field) 1351 P:000144 570E00 move b,x:RIGHT_HUM 1352 1353 P:000145 331000 move #state1,r3 1354 P:000146 312000 move #state2,r1 1355 P:000147 0BF080 jsr bst60ev6_l ;bandstop filter at 60 Hz (Elliptical) 000158 1356 P:000149 560400 move a,x:TX_BUFF_BASE ; Put value in left channel tx. 1357 P:00014A 331C00 move #state1_r,r3 1358 P:00014B 312C00 move #state2_r,r1 1359 P:00014C 0BF080 jsr bst60ev6_r ;bandstop filter at 60 Hz (Elliptical) 000164 1360 P:00014E 570500 move b,x:TX_BUFF_BASE+1 ; Put value in right channel tx. 1361 1362 P:00014F 0C0132 jmp loop_1 ; Loop back. 1363 1364 1365 ;************************************************************************************* 1366 1367 ;--------------------------------------------------------------------------- 1368 1369 ;--------------------------------------------------------------------------- 1370 ; The following subroutine calculates the next sinusoidal output value as a 1371 ; function by the digital oscillator given that r5 points to the memory 1372 ; location that contains the "coeff" value followed by the memory location 1373 ; that contains the "s1" value, followed by the memory location that contains 1374 ; the "s2" value. The formula and block diagram of the oscillator are: 1375 ; 1376 ; s1[n] = coeff*s1[n-1] - s2[n-1] = coeff*s1[n-1] - s1[n-2] 1377 ; 1378 ; _______ _______ Motorola DSP56300 Assembler Version 6.2.0 99-09-16 10:39:03 60hzdemo2.asm Page 7 1379 ; | | s1 | | s2 1380 ; +--->| z^-1 |--+--->| z^-1 |----+ 1381 ; | |_______| | |_______| | 1382 ; | | | 1383 ; | ___V___ ___V___ 1384 ; | | | | | 1385 ; | | coeff | | -1 | 1386 ; | |_______| |_______| 1387 ; | | | 1388 ; | | | 1389 ; | | | 1390 ; | +----->( + )<-----+ 1391 ; | | 1392 ; | | 1393 ; +------------------------+---------> sine output 1394 dosc_sin 1395 1396 P:000150 44DD00 move x:(r5)+,x0 ; Load coeff 1397 P:000151 46DD00 move x:(r5)+,y0 ; Load s1 into a. 1398 P:000152 57D500 move x:(r5)-,b ; Load s2 into b, r5 points to s1. 1399 P:000153 2000D0 mpy x0,y0,a ;Get coef*s1 in a in 2:14 format 1400 P:000154 200016 subl b,a ;y0,b ;Get (coef*s1 -s2)=sin_val in a 1401 ; in fractional format **** 1402 [60hzdemo2.asm 333]: WARNING --- Pipeline stall reading register written in previous instruction (X data move field) 1402 P:000155 565D00 move a,x:(r5)+ ; Save new s1. 1403 P:000156 466500 move y0,x:(r5) ; Save new s2. 1404 P:000157 00000C rts 1405 1406 1407 ;BST60EL6 1408 1409 1410 ; 1411 ; This code segment implements cascaded biquad sections in transpose form 1412 ; The "bit_24" section of the code implements the filter with 24 bit data 1413 ; and 24 bit coefficients. The "bit_16" section of the code implements the 1414 ; filter with coefficients that are truncated to 16 bits. The "bit_16" code 1415 ; also truncates the data to 16 bits before writing any accumulator value 1416 ; to memory. This "bit_16" code is to simulate the performance of a 16 bit 1417 ; processor implementing the same filter. In actuality, the filtering 1418 ; performed by "bit_16" will yield a better performance than that which 1419 ; a 16 bit processor would yield. 1420 ; 1421 ; 1422 1423 ; 1424 ; multiple shift left macro 1425 ; 1426 mshl macro scount,acc 1427 m if scount 1428 m rep #scount 1429 m asl acc 1430 m endif 1431 m endm 1432 1433 Motorola DSP56300 Assembler Version 6.2.0 99-09-16 10:39:03 60hzdemo2.asm Page 8 1434 1435 1436 bst60ev6_l ;Bandstop filter at 60Hz (Elliptical 1437 P:000158 0008F8 ori #$08,mr ;set scaling mode 1438 P:000159 478D00 move x:LEFT_HUM,y1 ;load left signal + Hum 1439 1440 P:00015A 5EAF00 move y:left_a,a 1441 P:00015B 4EB000 move y:left_y0,y0 1442 P:00015C 0BE780 jsr (r7) ; Call cascade biquad routine. 1443 P:00015D 4E3000 move y0,y:left_y0 1444 P:00015E 5E2F00 move a,y:left_a 1445 P:00015F 20EE00 move y1,a 1446 mshl scount,a ;bring gain back to 0 dB 1447 + if scount 1448 + P:000160 0601A0 rep #scount 1449 + P:000161 200032 asl a 1450 + endif 1451 P:000162 00F7B8 andi #$f7,mr ;disable scaling mode? 1452 P:000163 00000C rts 1453 1454 bst60ev6_r ;Bandstop filter at 60Hz (Elliptical 1455 P:000164 0008F8 ori #$08,mr ;set scaling mode 1456 P:000165 478E00 move x:RIGHT_HUM,y1 ;load right signal + Hum 1457 1458 P:000166 5EB100 move y:right_a,a 1459 P:000167 4EB200 move y:right_y0,y0 1460 P:000168 0BE780 jsr (r7) ; Call cascade biquad routine. 1461 P:000169 4E3200 move y0,y:right_y0 1462 P:00016A 5E3100 move a,y:right_a 1463 P:00016B 20EF00 move y1,b 1464 mshl scount,b ;bring gain back to 0 dB 1465 + if scount 1466 + P:00016C 0601A0 rep #scount 1467 + P:00016D 20003A asl b 1468 + endif 1469 P:00016E 00F7B8 andi #$f7,mr ;disable scaling mode? 1470 P:00016F 00000C rts 1471 1472 1473 1474 ; assumes each section's coefficients are divided by 2 1475 ; 1476 000170 filter EQU * 1477 P:000170 060380 do #nsec,_end_filter ;do each section 000178 1478 P:000172 FC81B3 macr y0,y1,a x:(r1),b y:(r4)+,y0 ;a=x(n)*bi0/2+wi1/2,b=wi2,y0=bi1/2 **** 1479 [60hzdemo2.asm 402]: WARNING --- Pipeline stall reading register written in previous instruction (X data move field) 1479 P:000173 21C42A asr b a,x0 ;b=wi2/2,x0=y(n) 1480 P:000174 4EDCBA mac y0,y1,b y:(r4)+,y0 ;b=x(n)*bi1/2+wi2/2,y0=ai1/2 1481 P:000175 4EDCDB macr x0,y0,b y:(r4)+,y0 ;b=b+y(n)*ai1/2,y0=bi2/2 **** 1482 [60hzdemo2.asm 405]: WARNING --- Pipeline stall reading register written in previous instruction (X data move field) 1482 P:000176 FC1BB8 mpy y0,y1,b b,x:(r3)+ y:(r4)+,y0 ;b=x(n)*bi2/2,save wi1,y0=ai2 1483 P:000177 19A3DB macr x0,y0,b x:(r3),a a,y1 ;b=b+y(n)*ai2/2,a=next iter wi1, 1484 ;y1=output of section i **** 1485 [60hzdemo2.asm 408]: WARNING --- Pipeline stall reading register written in previous instruction (X data move field) 1485 P:000178 FC1922 asr a b,x:(r1)+ y:(r4)+,y0 ;a=next iter wi1/2,save wi2, Motorola DSP56300 Assembler Version 6.2.0 99-09-16 10:39:03 60hzdemo2.asm Page 9 1486 ;y0=next iter bi0 1487 _end_filter 1488 P:000179 00000C rts ; Return from filter routine. 1489 1490 1491 ;*************************************************************** 1492 ; my stuff 1493 1494 no_filter_isr 1495 P:00017A 342100 move #no_filter+1,r4 ; Load code pointer. 1496 P:00017B 000004 rti 1497 coef_24_isr 1498 P:00017C 340100 move #coef_24+1,r4 ; Load code pointer. 1499 P:00017D 000004 rti 1500 coef_16_isr 1501 P:00017E 341100 move #coef_16+1,r4 ; Load code pointer. 1502 P:00017F 000004 rti 1503 1504 1505 ;****************************************************************************** 1506 1507 include 'ada_init.asm' 1508 page 132,60 1509 ;************************************************************************** 1510 ; ADA_INIT.ASM Ver 1.2 1511 ; Example program to initialize the CS4218 1512 ; 1513 ; Copyright (c) MOTOROLA 1995, 1996, 1997, 1998 1514 ; Semiconductor Products Sector 1515 ; Wireless Signal Processing Division 1516 ; 1517 ; History: 1518 ; 14 June 1996: RLR/LJD - ver 1.0 1519 ; 21 July 1997: BEA - ver 1.1 1520 ; 23 Sept 1998: TTL - ver 1.2 1521 ;************************************************************************** 1522 X:00002F org x: 1523 1524 ; Codec control constants 1525 X:00002F CTRL_WD_HI ds 1 1526 X:000030 CTRL_WD_LO ds 1 1527 1528 1529 ; GPIO pin constants 1530 1531 ; ESSI0 - audio data GPIO mode 1532 ; DSP CODEC 1533 ; --------------------------- 1534 CODEC_RESET 1535 000000 equ 0 ; bit0 SC00 ---> CODEC_RESET~ 1536 1537 ; ESSI1 - control data GPIO Mode 1538 ; DSP CODEC 1539 ;---------------------------- 1540 000000 CCS equ 0 ; bit0 SC10 ---> CCS~ 1541 000001 CCLK equ 1 ; bit1 SC11 ---> CCLK Motorola DSP56300 Assembler Version 6.2.0 99-09-16 10:39:03 ada_init.asm Page 10 1542 000002 CDIN equ 2 ; bit2 SC12 ---> CDIN 1543 1544 ;************************************************************************** 1545 ; Initialize the CS4218 codec 1546 ; --------------------------- 1547 ; Serial Mode 4 (SM4), DSP Slave/Codec Master, 32-bits per frame 1548 ; 1549 ; After a reset, the control port must be written once to initialize it 1550 ; if the port will be accessed to read or write control bits. The initial 1551 ; write is a "dummy" write since the data is ignored by the codec. A second 1552 ; write is needed to configure the codec as desired. Then, the control port 1553 ; only needs to be written to when a change is desired, or to obtain status 1554 ; information. 1555 ; 1556 ; Although only 23 bits contain useful data in CDIN, a minimum of 31 bits 1557 ; must be written. 1558 ; 1559 ; CDIN 1560 ;------------------------------------------------ 1561 ; bit 31 0 1562 ;------------------------------------------------ 1563 ; bit 30 mask interrupt 1564 ; 0=no mask on MF5:\INT pin 1565 ; 1=mask on MF5:\INT pin 1566 ;------------------------------------------------ 1567 ; bit 29 DO1 1568 ;------------------------------------------------ 1569 ; bits 28-24 left output D/A sttenuation (1.5dB steps) 1570 ; 00000=No attenuation 0dB 1571 ; 11111=Max attenuation -46.5dB 1572 ;------------------------------------------------ 1573 ; bits 23-19 right output D/A attenuation (1.5dB steps) 1574 ; 00000=No attenuation 0dB 1575 ; 11111=Max attenuation -46.5dB 1576 ;------------------------------------------------ 1577 ; bit 18 mute D/A outputs 1578 ; 0=outputs ON 1579 ; 1=outputs MUTED 1580 ;------------------------------------------------ 1581 ; bit 17 input mux, left select 1582 ; 0=RIN1 1583 ; 1=RIN2 (used on EVM) 1584 ;------------------------------------------------ 1585 ; bit 16 input mux, right select 1586 ; 0=LIN1 1587 ; 1=LIN2 (used on EVM) 1588 ;------------------------------------------------ 1589 ; bits 15-12 left input A/D gain (1.5dB steps) 1590 ; 0000=No gain 0dB 1591 ; 1111=Max gain +22.5dB 1592 ;------------------------------------------------ 1593 ; bits 11-8 right input A/D gain (1.5dB steps) 1594 ; 0000=No gain 0dB 1595 ; 1111=Max gain +22.5dB 1596 ;------------------------------------------------ 1597 ; bits 7-0 00000000 Motorola DSP56300 Assembler Version 6.2.0 99-09-16 10:39:03 ada_init.asm Page 11 1598 ;------------------------------------------------ 1599 ;************************************************************************** 1600 1601 1602 P:000180 org p: 1603 ada_init 1604 1605 ; reset ESSI ports 1606 P:000180 07F43F movep #$0000,x:M_PCRC ; reset ESSI0 port 000000 1607 P:000182 07F42F movep #$0000,x:M_PCRD ; reset ESSI1 port 000000 1608 1609 ; Set Control Register A and B 1610 P:000184 07F435 movep #$101807,x:M_CRA0 ; 12.288MHz/16 = 768KHz SCLK 101807 1611 ; prescale modulus = 8 1612 ; frame rate divider = 2 1613 ; 16-bits per word 1614 ; 32-bits per frame 1615 ; 16-bit data aligned to bit 23 1616 1617 P:000186 07F436 movep #$ff330c,x:M_CRB0 ; Enable REIE,TEIE,RLIE,TLIE, FF330C 1618 ; RIE,TIE,RE,TE0 1619 ; network mode, synchronous, 1620 ; out on rising/in on falling 1621 ; shift MSB first 1622 ; external clock source drives SCK 1623 ; (codec is master) 1624 ; RX frame sync pulses active for 1625 ; 1 bit clock immediately before 1626 ; transfer period 1627 ; positive frame sync polarity 1628 ; frame sync length is 1-bit 1629 1630 ; Configure GPIO pins -- (functionality and direction ) 1631 P:000188 07F43F movep #$0000,x:M_PCRC ; Enable GPIO pin 0 SC00=CODEC_RESET 000000 1632 P:00018A 07F42F movep #$0000,x:M_PCRD ; Enable GPIO CSS (pin 0),CCLK (pin 1), CDIN (pin 2) 000000 1633 1634 P:00018C 07F43E movep #$0001,x:M_PRRC ; set PC0=CODEC_RESET~ as output 000001 1635 P:00018E 07F42E movep #$0007,x:M_PRRD ; set PD0=CCS~ as output 000007 1636 ; set PD1=CCLK as output 1637 ; set PD2=CDIN as output 1638 1639 ; Codec Reset 1640 P:000190 013D00 bclr #CODEC_RESET,x:M_PDRC ; assert CODEC_RESET~ 1641 P:000191 012D00 bclr #CCS,x:M_PDRD ; assert CCS~ -- allows control register to be writte n to 1642 1643 ; Delay to allow Codec to reset Motorola DSP56300 Assembler Version 6.2.0 99-09-16 10:39:03 ada_init.asm Page 12 1644 P:000192 06E883 do #1000,_delay_loop 000195 1645 P:000194 06E8A3 rep #1000 ; minimum 50 ms delay 1646 P:000195 000000 nop 1647 _delay_loop 1648 1649 1650 ; Setting up to send Codec control information 1651 P:000196 013D20 bset #CODEC_RESET,x:M_PDRC ; deassert CODEC_RESET~ 1652 1653 1654 ; Sending control words 1655 set_control 1656 P:000197 44F400 move #CTRL_WD_12,x0 ; transfer control value to control variable 000300 1657 P:000199 442F00 move x0,x:CTRL_WD_HI 1658 P:00019A 240000 move #CTRL_WD_34,x0 1659 P:00019B 443000 move x0,x:CTRL_WD_LO 1660 P:00019C 0BF080 jsr codec_control ; send in dummy control information 0001A6 1661 P:00019E 0BF080 jsr codec_control ; send in correct control information 0001A6 1662 1663 1664 ; Set and enable interrupts 1665 P:0001A0 08F4BE movep #$000c,x:M_IPRP ; set interrupt priority level for ESSI0 to 3 00000C 1666 P:0001A2 00FCB8 andi #$fc,mr ; enable interrupts 1667 1668 ; Set ESSI functionality 1669 P:0001A3 07F43F movep #$003e,x:M_PCRC ; enable ESSI0 except SC00=CODEC_RESET 00003E 1670 1671 P:0001A5 00000C rts 1672 1673 1674 ;------------------------------------------------------------- 1675 ; codec_control routine 1676 ; Input: CTRL_WD_LO and CTRL_WD_HI 1677 ; Output: CDIN 1678 ; Description: Used to send control information to CODEC 1679 ; NOTE: does not preserve the 'a' register. 1680 ;------------------------------------------------------------- 1681 codec_control 1682 P:0001A6 200013 clr a 1683 P:0001A7 012D00 bclr #CCS,x:M_PDRD ; assert CCS 1684 P:0001A8 54AF00 move x:CTRL_WD_HI,a1 ; upper 16 bits of control data 1685 P:0001A9 0BF080 jsr send_codec ; shift out upper control word 0001B0 1686 P:0001AB 54B000 move x:CTRL_WD_LO,a1 ; lower 16 bits of control data 1687 P:0001AC 0BF080 jsr send_codec ; shift out lower control word 0001B0 1688 P:0001AE 012D20 bset #CCS,x:M_PDRD ; deassert CCS 1689 P:0001AF 00000C rts 1690 1691 Motorola DSP56300 Assembler Version 6.2.0 99-09-16 10:39:03 ada_init.asm Page 13 1692 ;--------------------------------------------------------------- 1693 ; send_codec routine 1694 ; Input: a1 containing control information 1695 ; Output: sends bits to CDIN 1696 ; Description: Determines bits to send to CDIN 1697 ;--------------------------------------------------------------- 1698 1699 send_codec 1700 P:0001B0 061080 do #16,end_send_codec ; 16 bits per word 0001BC 1701 P:0001B2 012D21 bset #CCLK,x:M_PDRD ; toggle CCLK clock high 1702 P:0001B3 0ACC17 jclr #23,a1,bit_low ; test msb 0001B8 1703 P:0001B5 012D22 bset #CDIN,x:M_PDRD ; send high into CDIN 1704 P:0001B6 0AF080 jmp continue 0001B9 1705 bit_low 1706 P:0001B8 012D02 bclr #CDIN,x:M_PDRD ; send low into CDIN 1707 continue 1708 P:0001B9 0602A0 rep #2 ; delay 1709 P:0001BA 000000 nop 1710 P:0001BB 012D01 bclr #CCLK,x:M_PDRD ; restart cycle 1711 P:0001BC 200033 lsl a ; shift control word to 1 bit 1712 ; to left 1713 end_send_codec 1714 P:0001BD 00000C rts 1715 1716 1717 1718 1719 ;**************************************************************************** 1720 ; SSI0_ISR.ASM Ver.2.0 1721 ; Example program to handle interrupts through 1722 ; the 56307 SSI0 to move audio through the CS4218 1723 ; 1724 ; Copyright (c) MOTOROLA 1995, 1996, 1997, 1998 1725 ; Semiconductor Products Sector 1726 ; Digital Signal Processing Division 1727 ; 1728 ; 1729 ; History: 1730 ; 14 June 1996: RLR/LJD - ver 1.0 1731 ; 23 July 1997: BEA - ver 1.1 1732 ;****************************************************************************** 1733 1734 1735 ;----the actual interrupt service routines (ISRs) follow: 1736 1737 ;************************ SSI TRANSMIT ISR ********************************* 1738 ssi_txe_isr 1739 P:0001BE 013704 bclr #4,x:M_SSISR0 ; Read SSISR to clear exception flag 1740 ; explicitly clears underrun flag 1741 ssi_tx_isr 1742 P:0001BF 605F00 move r0,x:(r7)+ ; Save r0 to the stack. 1743 P:0001C0 055F20 move m0,x:(r7)+ ; Save m0 to the stack. 1744 P:0001C1 0501A0 move #1,m0 ; Modulus 2 buffer. Motorola DSP56300 Assembler Version 6.2.0 99-09-16 10:39:03 ada_init.asm Page 14 1745 P:0001C2 608900 move x:TX_PTR,r0 ; Load the pointer to the tx buffer. 1746 P:0001C3 000000 nop 1747 P:0001C4 000000 nop 1748 P:0001C5 000000 nop 1749 P:0001C6 07D83C movep x:(r0)+,x:M_TX00 ; SSI transfer data register. 1750 P:0001C7 600900 move r0,x:TX_PTR ; Update tx buffer pointer. 1751 P:0001C8 05FF20 move x:-(r7),m0 ; Restore m0. 1752 P:0001C9 60FF00 move x:-(r7),r0 ; Restore r0. 1753 P:0001CA 000004 rti 1754 1755 ;********************* SSI TRANSMIT LAST SLOT ISR ************************** 1756 ssi_txls_isr 1757 P:0001CB 605F00 move r0,x:(r7)+ ; Save r0 to the stack. 1758 P:0001CC 300400 move #TX_BUFF_BASE,r0 ; Reset pointer. 1759 P:0001CD 000000 nop 1760 P:0001CE 600900 move r0,x:TX_PTR ; Reset tx buffer pointer just in 1761 P:0001CF 000000 nop ; case it was corrupted. 1762 P:0001D0 60FF00 move x:-(r7),r0 ; Restore r0. 1763 P:0001D1 000004 rti 1764 1765 ;************************** SSI receive ISR ******************************** 1766 ssi_rxe_isr 1767 P:0001D2 013705 bclr #5,x:M_SSISR0 ; Read SSISR to clear exception flag 1768 ; explicitly clears overrun flag 1769 ssi_rx_isr 1770 P:0001D3 605F00 move r0,x:(r7)+ ; Save r0 to the stack. 1771 P:0001D4 055F20 move m0,x:(r7)+ ; Save m0 to the stack. 1772 P:0001D5 0501A0 move #1,m0 ; Modulus 2 buffer. 1773 P:0001D6 608800 move x:RX_PTR,r0 ; Load the pointer to the rx buffer. 1774 P:0001D7 000000 nop 1775 P:0001D8 000000 nop 1776 P:0001D9 000000 nop 1777 P:0001DA 075838 movep x:M_RX0,x:(r0)+ ; Read out received data to buffer. 1778 P:0001DB 600800 move r0,x:RX_PTR ; Update rx buffer pointer. 1779 P:0001DC 05FF20 move x:-(r7),m0 ; Restore m0. 1780 P:0001DD 60FF00 move x:-(r7),r0 ; Restore r0. 1781 P:0001DE 000004 rti 1782 1783 ;********************** SSI receive last slot ISR ************************** 1784 ssi_rxls_isr 1785 P:0001DF 605F00 move r0,x:(r7)+ ; Save r0 to the stack. 1786 P:0001E0 300000 move #RX_BUFF_BASE,r0 ; Reset rx buffer pointer just in 1787 ; case it was corrupted. 1788 P:0001E1 600800 move r0,x:RX_PTR ; Update rx buffer pointer. 1789 P:0001E2 60FF00 move x:-(r7),r0 ; Restore r0. 1790 P:0001E3 000004 rti 1791 1792 ;****************************************************************************** 1793 echo ;added to provide complince with the same vectors.asm that echo.asm and fltr_tst.asm use 1794 end 0 Errors 7 Warnings Motorola DSP56300 Assembler Version 6.2.0 99-09-16 10:39:03 60hzdemo2.asm Page 15