Motorola DSP56300 Assembler Version 6.2.0 99-12-01 16:45:34 pass_s~1.asm Page 1 1 ;*************************************************************************** 2 ;QS_ST.ASM : WILL PASS AUDIO STRAIGHT THROUGH 3 ;*************************************************************************** 1067 1068 ;****************************************************************************** 1069 1070 ;---Buffer for talking to the CS4215 1071 1072 X:000000 org x:0 1073 RX_BUFF_BASE 1074 000000 equ * 1075 RX_data_1_2 1076 X:000000 ds 1 ;data time slot 1/2 for RX ISR 1077 RX_data_3_4 1078 X:000001 ds 1 ;data time slot 3/4 for RX ISR 1079 RX_data_5_6 1080 X:000002 ds 1 ;data time slot 5/6 for RX ISR 1081 RX_data_7_8 1082 X:000003 ds 1 ;data time slot 7/8 for RX ISR 1083 1084 TX_BUFF_BASE 1085 000004 equ * 1086 TX_data_1_2 1087 X:000004 ds 1 ;data time slot 1/2 for TX ISR 1088 TX_data_3_4 1089 X:000005 ds 1 ;data time slot 3/4 for TX ISR 1090 TX_data_5_6 1091 X:000006 ds 1 ;data time slot 5/6 for TX ISR 1092 TX_data_7_8 1093 X:000007 ds 1 ;data time slot 7/8 for TX ISR 1094 1095 X:000008 RX_PTR ds 1 ; Pointer for rx buffer 1096 X:000009 TX_PTR ds 1 ; Pointer for tx buffer 1097 1098 ;TONE_OUTPUT EQU HEADPHONE_EN+LINEOUT_EN+(4*LEFT_ATTN)+(4*RIGHT_ATTN) 1099 ;TONE_INPUT EQU MIC_IN_SELECT+(15*MONITOR_ATTN) 1100 ;CTRL_WD_12 equ NO_PREAMP+HI_PASS_FILT+SAMP_RATE_48+STEREO+DATA_16 ;CLB=0 1101 ;CTRL_WD_34 equ IMMED_3STATE+XTAL1_SELECT+BITS_64+CODEC_MASTER 1102 ;CTRL_WD_56 equ $000000 1103 ;CTRL_WD_78 equ $000000 1104 1105 000300 CTRL_WD_12 equ MIN_LEFT_ATTN+MIN_RIGHT_ATTN+LIN2+RIN2 1106 000000 CTRL_WD_34 equ MIN_LEFT_GAIN+MIN_RIGHT_GAIN 1107 1108 1109 P:000100 org p:$100 1110 START 1111 main 1112 P:000100 08F4BD movep #$040003,x:M_PCTL ; set PLL for MPY of 4X 040003 1113 P:000102 08F4BB movep #$012421,x:M_BCR ; set up one ext. wait state for all AAR areas 012421 1114 P:000104 0003F8 ori #3,mr ;mask interrupts 1115 P:000105 0500BB movec #0,sp ;clear hardware stack pointer 1116 P:000106 0500BA move #0,omr ;operating mode 0 1117 P:000107 364000 move #$40,r6 ; initialise stack pointer Motorola DSP56300 Assembler Version 6.2.0 99-12-01 16:45:34 pass_s~1.asm Page 2 1118 P:000108 05F426 move #-1,m6 ; linear addressing FFFFFF 1119 P:00010A 0BF080 jsr ada_init ; initialize codec 00014C 1120 1121 1122 ; initialize SCI 1123 1124 ; 10-bit asynchronous mode 1125 ; enable reciever and transmitter 1126 P:00010C 07F41C movep #$000302,x:M_SCR ; SCI control register 000302 1127 1128 ; enable tx and rx pins 1129 P:00010E 07F41F movep #$000003,x:M_PCRE ; Port E Control Register 000003 1130 1131 ; Reciever/Transmitter clocks use external clock from SCLK 1132 P:000110 07F41B movep #$00C000,x:M_SCCR ; SCI Clock Control Register 00C000 1133 1134 P:000112 65F400 move #text,r5 000000 1135 P:000114 0BF080 jsr print 00012B 1136 1137 1138 1139 loop_1 1140 1141 P:000116 01B7A2 jset #2,x:M_SSISR0,* ;wait for frame sync to pass 000116 1142 P:000118 01B782 jclr #2,x:M_SSISR0,* ;wait for frame sync 000118 1143 1144 P:00011A 568000 move x:RX_BUFF_BASE,a ;receive left 1145 P:00011B 578100 move x:RX_BUFF_BASE+1,b ;receive right 1146 P:00011C 0BF080 jsr process_stereo 000127 1147 P:00011E 560400 move a,x:TX_BUFF_BASE ;transmit left 1148 P:00011F 570500 move b,x:TX_BUFF_BASE+1 ;transmit right 1149 1150 P:000120 46F400 move #CTRL_WD_12,y0 ;set up control words 000300 1151 P:000122 460600 move y0,x:TX_BUFF_BASE+2 1152 P:000123 46F400 move #CTRL_WD_12,y0 000300 1153 P:000125 460700 move y0,x:TX_BUFF_BASE+3 1154 1155 P:000126 0C0116 jmp loop_1 1156 1157 process_stereo 1158 P:000127 000000 nop 1159 P:000128 000000 nop 1160 P:000129 000000 nop 1161 P:00012A 00000C rts Motorola DSP56300 Assembler Version 6.2.0 99-12-01 16:45:34 pass_s~1.asm Page 3 1162 1163 1164 ;print subroutine takes address in register r5 1165 print 1166 P:00012B 21C400 move a,x0 1167 P:00012C 4EDD00 prbegin move y:(r5)+,y0 1168 1169 P:00012D 56F400 move #$00ffff,a 00FFFF 1170 P:00012F 200055 cmp y0,a 1171 ; cmp #$00ffff,y0 ;check to see if done (char=$00) 1172 P:000130 0D1047 bgt prend 00001A 1173 P:000132 019381 jclr #1,x:M_SSR,* ;wait for tx to finish 000132 1174 P:000134 019380 jclr #0,x:M_SSR,* ;wait for tx to finish 000134 1175 P:000136 467000 move y0,x:M_STXH ; send high byte FFFF97 1176 1177 P:000138 56F400 move #$001111,a 001111 1178 P:00013A 200056 and y0,a 1179 ; cmp #$0000ff,y0 ;check to see if done ($00) 1180 P:00013B 0D1047 bgt prend 00000F 1181 P:00013D 019381 jclr #1,x:M_SSR,* ;wait for tx to finish 00013D 1182 P:00013F 019380 jclr #0,x:M_SSR,* ;wait for tx to finish 00013F 1183 P:000141 467000 move y0,x:M_STXM ; send mid byte FFFF96 1184 1185 P:000143 019381 jclr #1,x:M_SSR,* ;wait for tx to finish 000143 1186 P:000145 019380 jclr #0,x:M_SSR,* ;wait for tx to finish 000145 1187 P:000147 467000 move y0,x:M_STXL ; send low byte FFFF95 1188 1189 P:000149 050FC3 bra prbegin 1190 P:00014A 208E00 prend move x0,a 1191 P:00014B 00000C rts 1192 1193 1194 include 'ada_init.asm' 1195 page 132,60 1196 ;************************************************************************** 1197 ; ADA_INIT.ASM Ver 1.2 1198 ; Example program to initialize the CS4218 1199 ; 1200 ; Copyright (c) MOTOROLA 1995, 1996, 1997, 1998 1201 ; Semiconductor Products Sector 1202 ; Wireless Signal Processing Division 1203 ; 1204 ; History: Motorola DSP56300 Assembler Version 6.2.0 99-12-01 16:45:34 ada_init.asm Page 4 1205 ; 14 June 1996: RLR/LJD - ver 1.0 1206 ; 21 July 1997: BEA - ver 1.1 1207 ; 23 Sept 1998: TTL - ver 1.2 1208 ;************************************************************************** 1209 X:00000A org x: 1210 1211 ; Codec control constants 1212 X:00000A CTRL_WD_HI ds 1 1213 X:00000B CTRL_WD_LO ds 1 1214 1215 1216 ; GPIO pin constants 1217 1218 ; ESSI0 - audio data GPIO mode 1219 ; DSP CODEC 1220 ; --------------------------- 1221 CODEC_RESET 1222 000000 equ 0 ; bit0 SC00 ---> CODEC_RESET~ 1223 1224 ; ESSI1 - control data GPIO Mode 1225 ; DSP CODEC 1226 ;---------------------------- 1227 000000 CCS equ 0 ; bit0 SC10 ---> CCS~ 1228 000001 CCLK equ 1 ; bit1 SC11 ---> CCLK 1229 000002 CDIN equ 2 ; bit2 SC12 ---> CDIN 1230 1231 ;************************************************************************** 1232 ; Initialize the CS4218 codec 1233 ; --------------------------- 1234 ; Serial Mode 4 (SM4), DSP Slave/Codec Master, 32-bits per frame 1235 ; 1236 ; After a reset, the control port must be written once to initialize it 1237 ; if the port will be accessed to read or write control bits. The initial 1238 ; write is a "dummy" write since the data is ignored by the codec. A second 1239 ; write is needed to configure the codec as desired. Then, the control port 1240 ; only needs to be written to when a change is desired, or to obtain status 1241 ; information. 1242 ; 1243 ; Although only 23 bits contain useful data in CDIN, a minimum of 31 bits 1244 ; must be written. 1245 ; 1246 ; CDIN 1247 ;------------------------------------------------ 1248 ; bit 31 0 1249 ;------------------------------------------------ 1250 ; bit 30 mask interrupt 1251 ; 0=no mask on MF5:\INT pin 1252 ; 1=mask on MF5:\INT pin 1253 ;------------------------------------------------ 1254 ; bit 29 DO1 1255 ;------------------------------------------------ 1256 ; bits 28-24 left output D/A sttenuation (1.5dB steps) 1257 ; 00000=No attenuation 0dB 1258 ; 11111=Max attenuation -46.5dB 1259 ;------------------------------------------------ 1260 ; bits 23-19 right output D/A attenuation (1.5dB steps) Motorola DSP56300 Assembler Version 6.2.0 99-12-01 16:45:34 ada_init.asm Page 5 1261 ; 00000=No attenuation 0dB 1262 ; 11111=Max attenuation -46.5dB 1263 ;------------------------------------------------ 1264 ; bit 18 mute D/A outputs 1265 ; 0=outputs ON 1266 ; 1=outputs MUTED 1267 ;------------------------------------------------ 1268 ; bit 17 input mux, left select 1269 ; 0=RIN1 1270 ; 1=RIN2 (used on EVM) 1271 ;------------------------------------------------ 1272 ; bit 16 input mux, right select 1273 ; 0=LIN1 1274 ; 1=LIN2 (used on EVM) 1275 ;------------------------------------------------ 1276 ; bits 15-12 left input A/D gain (1.5dB steps) 1277 ; 0000=No gain 0dB 1278 ; 1111=Max gain +22.5dB 1279 ;------------------------------------------------ 1280 ; bits 11-8 right input A/D gain (1.5dB steps) 1281 ; 0000=No gain 0dB 1282 ; 1111=Max gain +22.5dB 1283 ;------------------------------------------------ 1284 ; bits 7-0 00000000 1285 ;------------------------------------------------ 1286 ;************************************************************************** 1287 1288 1289 P:00014C org p: 1290 ada_init 1291 1292 ; reset ESSI ports 1293 P:00014C 07F43F movep #$0000,x:M_PCRC ; reset ESSI0 port 000000 1294 P:00014E 07F42F movep #$0000,x:M_PCRD ; reset ESSI1 port 000000 1295 1296 ; Set Control Register A and B 1297 P:000150 07F435 movep #$101807,x:M_CRA0 ; 12.288MHz/16 = 768KHz SCLK 101807 1298 ; prescale modulus = 8 1299 ; frame rate divider = 2 1300 ; 16-bits per word 1301 ; 32-bits per frame 1302 ; 16-bit data aligned to bit 23 1303 1304 P:000152 07F436 movep #$ff330c,x:M_CRB0 ; Enable REIE,TEIE,RLIE,TLIE, FF330C 1305 ; RIE,TIE,RE,TE0 1306 ; network mode, synchronous, 1307 ; out on rising/in on falling 1308 ; shift MSB first 1309 ; external clock source drives SCK 1310 ; (codec is master) 1311 ; RX frame sync pulses active for 1312 ; 1 bit clock immediately before Motorola DSP56300 Assembler Version 6.2.0 99-12-01 16:45:34 ada_init.asm Page 6 1313 ; transfer period 1314 ; positive frame sync polarity 1315 ; frame sync length is 1-bit 1316 1317 ; Configure GPIO pins -- (functionality and direction ) 1318 P:000154 07F43F movep #$0000,x:M_PCRC ; Enable GPIO pin 0 SC00=CODEC_RESET 000000 1319 P:000156 07F42F movep #$0000,x:M_PCRD ; Enable GPIO CSS (pin 0),CCLK (pin 1), CDIN (pin 2) 000000 1320 1321 P:000158 07F43E movep #$0001,x:M_PRRC ; set PC0=CODEC_RESET~ as output 000001 1322 P:00015A 07F42E movep #$0007,x:M_PRRD ; set PD0=CCS~ as output 000007 1323 ; set PD1=CCLK as output 1324 ; set PD2=CDIN as output 1325 1326 ; Codec Reset 1327 P:00015C 013D00 bclr #CODEC_RESET,x:M_PDRC ; assert CODEC_RESET~ 1328 P:00015D 012D00 bclr #CCS,x:M_PDRD ; assert CCS~ -- allows control register to be writte n to 1329 1330 ; Delay to allow Codec to reset 1331 P:00015E 06E883 do #1000,_delay_loop 000161 1332 P:000160 06E8A3 rep #1000 ; minimum 50 ms delay 1333 P:000161 000000 nop 1334 _delay_loop 1335 1336 1337 ; Setting up to send Codec control information 1338 P:000162 013D20 bset #CODEC_RESET,x:M_PDRC ; deassert CODEC_RESET~ 1339 1340 1341 ; Sending control words 1342 set_control 1343 P:000163 44F400 move #CTRL_WD_12,x0 ; transfer control value to control variable 000300 1344 P:000165 440A00 move x0,x:CTRL_WD_HI 1345 P:000166 240000 move #CTRL_WD_34,x0 1346 P:000167 440B00 move x0,x:CTRL_WD_LO 1347 P:000168 0BF080 jsr codec_control ; send in dummy control information 000172 1348 P:00016A 0BF080 jsr codec_control ; send in correct control information 000172 1349 1350 1351 ; Set and enable interrupts 1352 P:00016C 08F4BE movep #$000c,x:M_IPRP ; set interrupt priority level for ESSI0 to 3 00000C 1353 P:00016E 00FCB8 andi #$fc,mr ; enable interrupts 1354 1355 ; Set ESSI functionality 1356 P:00016F 07F43F movep #$003e,x:M_PCRC ; enable ESSI0 except SC00=CODEC_RESET 00003E Motorola DSP56300 Assembler Version 6.2.0 99-12-01 16:45:34 ada_init.asm Page 7 1357 1358 P:000171 00000C rts 1359 1360 1361 ;------------------------------------------------------------- 1362 ; codec_control routine 1363 ; Input: CTRL_WD_LO and CTRL_WD_HI 1364 ; Output: CDIN 1365 ; Description: Used to send control information to CODEC 1366 ; NOTE: does not preserve the 'a' register. 1367 ;------------------------------------------------------------- 1368 codec_control 1369 P:000172 200013 clr a 1370 P:000173 012D00 bclr #CCS,x:M_PDRD ; assert CCS 1371 P:000174 548A00 move x:CTRL_WD_HI,a1 ; upper 16 bits of control data 1372 P:000175 0BF080 jsr send_codec ; shift out upper control word 00017C 1373 P:000177 548B00 move x:CTRL_WD_LO,a1 ; lower 16 bits of control data 1374 P:000178 0BF080 jsr send_codec ; shift out lower control word 00017C 1375 P:00017A 012D20 bset #CCS,x:M_PDRD ; deassert CCS 1376 P:00017B 00000C rts 1377 1378 1379 ;--------------------------------------------------------------- 1380 ; send_codec routine 1381 ; Input: a1 containing control information 1382 ; Output: sends bits to CDIN 1383 ; Description: Determines bits to send to CDIN 1384 ;--------------------------------------------------------------- 1385 1386 send_codec 1387 P:00017C 061080 do #16,end_send_codec ; 16 bits per word 000188 1388 P:00017E 012D21 bset #CCLK,x:M_PDRD ; toggle CCLK clock high 1389 P:00017F 0ACC17 jclr #23,a1,bit_low ; test msb 000184 1390 P:000181 012D22 bset #CDIN,x:M_PDRD ; send high into CDIN 1391 P:000182 0AF080 jmp continue 000185 1392 bit_low 1393 P:000184 012D02 bclr #CDIN,x:M_PDRD ; send low into CDIN 1394 continue 1395 P:000185 0602A0 rep #2 ; delay 1396 P:000186 000000 nop 1397 P:000187 012D01 bclr #CCLK,x:M_PDRD ; restart cycle 1398 P:000188 200033 lsl a ; shift control word to 1 bit 1399 ; to left 1400 end_send_codec 1401 P:000189 00000C rts 1402 1403 1404 1405 1406 ;**************************************************************************** 1407 ; SSI0_ISR.ASM Ver.2.0 Motorola DSP56300 Assembler Version 6.2.0 99-12-01 16:45:34 ada_init.asm Page 8 1408 ; Example program to handle interrupts through 1409 ; the 56307 SSI0 to move audio through the CS4218 1410 ; 1411 ; Copyright (c) MOTOROLA 1995, 1996, 1997, 1998 1412 ; Semiconductor Products Sector 1413 ; Digital Signal Processing Division 1414 ; 1415 ; 1416 ; History: 1417 ; 14 June 1996: RLR/LJD - ver 1.0 1418 ; 23 July 1997: BEA - ver 1.1 1419 ;****************************************************************************** 1420 1421 1422 ;----the actual interrupt service routines (ISRs) follow: 1423 1424 ;************************ SSI TRANSMIT ISR ********************************* 1425 ssi_txe_isr 1426 P:00018A 013704 bclr #4,x:M_SSISR0 ; Read SSISR to clear exception flag 1427 ; explicitly clears underrun flag 1428 ssi_tx_isr 1429 P:00018B 605F00 move r0,x:(r7)+ ; Save r0 to the stack. 1430 P:00018C 055F20 move m0,x:(r7)+ ; Save m0 to the stack. 1431 P:00018D 0501A0 move #1,m0 ; Modulus 2 buffer. 1432 P:00018E 608900 move x:TX_PTR,r0 ; Load the pointer to the tx buffer. 1433 P:00018F 000000 nop 1434 P:000190 000000 nop 1435 P:000191 000000 nop 1436 P:000192 07D83C movep x:(r0)+,x:M_TX00 ; SSI transfer data register. 1437 P:000193 600900 move r0,x:TX_PTR ; Update tx buffer pointer. 1438 P:000194 05FF20 move x:-(r7),m0 ; Restore m0. 1439 P:000195 60FF00 move x:-(r7),r0 ; Restore r0. 1440 P:000196 000004 rti 1441 1442 ;********************* SSI TRANSMIT LAST SLOT ISR ************************** 1443 ssi_txls_isr 1444 P:000197 605F00 move r0,x:(r7)+ ; Save r0 to the stack. 1445 P:000198 300400 move #TX_BUFF_BASE,r0 ; Reset pointer. 1446 P:000199 000000 nop 1447 P:00019A 600900 move r0,x:TX_PTR ; Reset tx buffer pointer just in 1448 P:00019B 000000 nop ; case it was corrupted. 1449 P:00019C 60FF00 move x:-(r7),r0 ; Restore r0. 1450 P:00019D 000004 rti 1451 1452 ;************************** SSI receive ISR ******************************** 1453 ssi_rxe_isr 1454 P:00019E 013705 bclr #5,x:M_SSISR0 ; Read SSISR to clear exception flag 1455 ; explicitly clears overrun flag 1456 ssi_rx_isr 1457 P:00019F 605F00 move r0,x:(r7)+ ; Save r0 to the stack. 1458 P:0001A0 055F20 move m0,x:(r7)+ ; Save m0 to the stack. 1459 P:0001A1 0501A0 move #1,m0 ; Modulus 2 buffer. 1460 P:0001A2 608800 move x:RX_PTR,r0 ; Load the pointer to the rx buffer. 1461 P:0001A3 000000 nop 1462 P:0001A4 000000 nop 1463 P:0001A5 000000 nop Motorola DSP56300 Assembler Version 6.2.0 99-12-01 16:45:34 ada_init.asm Page 9 1464 P:0001A6 075838 movep x:M_RX0,x:(r0)+ ; Read out received data to buffer. 1465 P:0001A7 600800 move r0,x:RX_PTR ; Update rx buffer pointer. 1466 P:0001A8 05FF20 move x:-(r7),m0 ; Restore m0. 1467 P:0001A9 60FF00 move x:-(r7),r0 ; Restore r0. 1468 P:0001AA 000004 rti 1469 1470 ;********************** SSI receive last slot ISR ************************** 1471 ssi_rxls_isr 1472 P:0001AB 605F00 move r0,x:(r7)+ ; Save r0 to the stack. 1473 P:0001AC 300000 move #RX_BUFF_BASE,r0 ; Reset rx buffer pointer just in 1474 ; case it was corrupted. 1475 P:0001AD 600800 move r0,x:RX_PTR ; Update rx buffer pointer. 1476 P:0001AE 60FF00 move x:-(r7),r0 ; Restore r0. 1477 P:0001AF 000004 rti 1478 1479 Y:000000 org y: 1480 text 1481 Y:000000 dc "Testing one two three" 1482 Y:000007 dc $0 1483 Y:000008 dc "12345" 1484 echo 1485 end 0 Errors 0 Warnings