A51 MACRO ASSEMBLER BLINK 10/07/2004 09:28:42 PAGE 1 MACRO ASSEMBLER A51 V6.14a OBJECT MODULE PLACED IN blink.OBJ ASSEMBLER INVOKED BY: F:\Cygnal\IDEfiles\C51\BIN\a51.exe blink.asm XR GEN DB EP NOMOD51 LOC OBJ LINE SOURCE 1 ;----------------------------------------------------------------------------- 2 ; Copyright (C) 2001 CYGNAL INTEGRATED PRODUCTS, INC. 3 ; All rights reserved. 4 ; 5 ; 6 ; 7 ; FILE NAME : BLINK.ASM 8 ; TARGET MCU : C8051F020 9 ; DESCRIPTION : This program illustrates how to disable the watchdog timer, 10 ; configure the Crossbar, configure a port and write to a port 11 ; I/O pin. 12 ; 13 ; NOTES: 14 ; 15 ;----------------------------------------------------------------------------- 16 17 ;$include (c8051f020.inc) ; Include regsiter definition file. +1 18 ;----------------------------------------------------------------------------- +1 19 ; Copyright (C) 2001 CYGNAL INTEGRATED PRODUCTS, INC. +1 20 ; All rights reserved. +1 21 ; +1 22 ; +1 23 ; FILE NAME : C8051F020.INC +1 24 ; TARGET MCUs : C8051F020, 'F021, 'F022, 'F023 +1 25 ; DESCRIPTION : Register/bit definitions for the C8051F02x product family. +1 26 ; +1 27 ; REVISION 1.0 +1 28 ; +1 29 ;----------------------------------------------------------------------------- +1 30 ;REGISTER DEFINITIONS +1 31 ; 0080 +1 32 P0 DATA 080H ; PORT 0 0081 +1 33 SP DATA 081H ; STACK POINTER 0082 +1 34 DPL DATA 082H ; DATA POINTER - LOW BYTE 0083 +1 35 DPH DATA 083H ; DATA POINTER - HIGH BYTE 0084 +1 36 P4 DATA 084H ; PORT 4 0085 +1 37 P5 DATA 085H ; PORT 5 0086 +1 38 P6 DATA 086H ; PORT 6 0087 +1 39 PCON DATA 087H ; POWER CONTROL 0088 +1 40 TCON DATA 088H ; TIMER CONTROL 0089 +1 41 TMOD DATA 089H ; TIMER MODE 008A +1 42 TL0 DATA 08AH ; TIMER 0 - LOW BYTE 008B +1 43 TL1 DATA 08BH ; TIMER 1 - LOW BYTE 008C +1 44 TH0 DATA 08CH ; TIMER 0 - HIGH BYTE 008D +1 45 TH1 DATA 08DH ; TIMER 1 - HIGH BYTE 008E +1 46 CKCON DATA 08EH ; CLOCK CONTROL 008F +1 47 PSCTL DATA 08FH ; PROGRAM STORE R/W CONTROL 0090 +1 48 P1 DATA 090H ; PORT 1 0091 +1 49 TMR3CN DATA 091H ; TIMER 3 CONTROL 0092 +1 50 TMR3RLL DATA 092H ; TIMER 3 RELOAD REGISTER - LOW BYTE 0093 +1 51 TMR3RLH DATA 093H ; TIMER 3 RELOAD REGISTER - HIGH BYTE 0094 +1 52 TMR3L DATA 094H ; TIMER 3 - LOW BYTE 0095 +1 53 TMR3H DATA 095H ; TIMER 3 - HIGH BYTE 0096 +1 54 P7 DATA 096H ; PORT 7 0098 +1 55 SCON0 DATA 098H ; SERIAL PORT 0 CONTROL 0099 +1 56 SBUF0 DATA 099H ; SERIAL PORT 0 BUFFER 009A +1 57 SPI0CFG DATA 09AH ; SERIAL PERIPHERAL INTERFACE 0 CONFIGURATION 009B +1 58 SPI0DAT DATA 09BH ; SERIAL PERIPHERAL INTERFACE 0 DATA A51 MACRO ASSEMBLER BLINK 10/07/2004 09:28:42 PAGE 2 009C +1 59 ADC1 DATA 09CH ; ADC 1 DATA 009D +1 60 SPI0CKR DATA 09DH ; SERIAL PERIPHERAL INTERFACE 0 CLOCK RATE CONTROL 009E +1 61 CPT0CN DATA 09EH ; COMPARATOR 0 CONTROL 009F +1 62 CPT1CN DATA 09FH ; COMPARATOR 1 CONTROL 00A0 +1 63 P2 DATA 0A0H ; PORT 2 00A1 +1 64 EMI0TC DATA 0A1H ; EMIF TIMING CONTROL 00A3 +1 65 EMI0CF DATA 0A3H ; EXTERNAL MEMORY INTERFACE (EMIF) CONFIGURATION 00A4 +1 66 P0MDOUT DATA 0A4H ; PORT 0 OUTPUT MODE CONFIGURATION 00A5 +1 67 P1MDOUT DATA 0A5H ; PORT 1 OUTPUT MODE CONFIGURATION 00A6 +1 68 P2MDOUT DATA 0A6H ; PORT 2 OUTPUT MODE CONFIGURATION 00A7 +1 69 P3MDOUT DATA 0A7H ; PORT 3 OUTPUT MODE CONFIGURATION 00A8 +1 70 IE DATA 0A8H ; INTERRUPT ENABLE 00A9 +1 71 SADDR0 DATA 0A9H ; SERIAL PORT 0 SLAVE ADDRESS 00AA +1 72 ADC1CN DATA 0AAH ; ADC 1 CONTROL 00AB +1 73 ADC1CF DATA 0ABH ; ADC 1 ANALOG MUX CONFIGURATION 00AC +1 74 AMX1SL DATA 0ACH ; ADC 1 ANALOG MUX CHANNEL SELECT 00AD +1 75 P3IF DATA 0ADH ; PORT 3 EXTERNAL INTERRUPT FLAGS 00AE +1 76 SADEN1 DATA 0AEH ; SERIAL PORT 1 SLAVE ADDRESS MASK 00AF +1 77 EMI0CN DATA 0AFH ; EXTERNAL MEMORY INTERFACE CONTROL 00B0 +1 78 P3 DATA 0B0H ; PORT 3 00B1 +1 79 OSCXCN DATA 0B1H ; EXTERNAL OSCILLATOR CONTROL 00B2 +1 80 OSCICN DATA 0B2H ; INTERNAL OSCILLATOR CONTROL 00B5 +1 81 P74OUT DATA 0B5H ; PORTS 4 - 7 OUTPUT MODE 00B6 +1 82 FLSCL DATA 0B6H ; FLASH MEMORY TIMING PRESCALER 00B7 +1 83 FLACL DATA 0B7H ; FLASH ACESS LIMIT 00B8 +1 84 IP DATA 0B8H ; INTERRUPT PRIORITY 00B9 +1 85 SADEN0 DATA 0B9H ; SERIAL PORT 0 SLAVE ADDRESS MASK 00BA +1 86 AMX0CF DATA 0BAH ; ADC 0 MUX CONFIGURATION 00BB +1 87 AMX0SL DATA 0BBH ; ADC 0 MUX CHANNEL SELECTION 00BC +1 88 ADC0CF DATA 0BCH ; ADC 0 CONFIGURATION 00BD +1 89 P1MDIN DATA 0BDH ; PORT 1 INPUT MODE 00BE +1 90 ADC0L DATA 0BEH ; ADC 0 DATA - LOW BYTE 00BF +1 91 ADC0H DATA 0BFH ; ADC 0 DATA - HIGH BYTE 00C0 +1 92 SMB0CN DATA 0C0H ; SMBUS 0 CONTROL 00C1 +1 93 SMB0STA DATA 0C1H ; SMBUS 0 STATUS 00C2 +1 94 SMB0DAT DATA 0C2H ; SMBUS 0 DATA 00C3 +1 95 SMB0ADR DATA 0C3H ; SMBUS 0 SLAVE ADDRESS 00C4 +1 96 ADC0GTL DATA 0C4H ; ADC 0 GREATER-THAN REGISTER - LOW BYTE 00C5 +1 97 ADC0GTH DATA 0C5H ; ADC 0 GREATER-THAN REGISTER - HIGH BYTE 00C6 +1 98 ADC0LTL DATA 0C6H ; ADC 0 LESS-THAN REGISTER - LOW BYTE 00C7 +1 99 ADC0LTH DATA 0C7H ; ADC 0 LESS-THAN REGISTER - HIGH BYTE 00C8 +1 100 T2CON DATA 0C8H ; TIMER 2 CONTROL 00C9 +1 101 T4CON DATA 0C9H ; TIMER 4 CONTROL 00CA +1 102 RCAP2L DATA 0CAH ; TIMER 2 CAPTURE REGISTER - LOW BYTE 00CB +1 103 RCAP2H DATA 0CBH ; TIMER 2 CAPTURE REGISTER - HIGH BYTE 00CC +1 104 TL2 DATA 0CCH ; TIMER 2 - LOW BYTE 00CD +1 105 TH2 DATA 0CDH ; TIMER 2 - HIGH BYTE 00CF +1 106 SMB0CR DATA 0CFH ; SMBUS 0 CLOCK RATE 00D0 +1 107 PSW DATA 0D0H ; PROGRAM STATUS WORD 00D1 +1 108 REF0CN DATA 0D1H ; VOLTAGE REFERENCE 0 CONTROL 00D2 +1 109 DAC0L DATA 0D2H ; DAC 0 REGISTER - LOW BYTE 00D3 +1 110 DAC0H DATA 0D3H ; DAC 0 REGISTER - HIGH BYTE 00D4 +1 111 DAC0CN DATA 0D4H ; DAC 0 CONTROL 00D5 +1 112 DAC1L DATA 0D5H ; DAC 1 REGISTER - LOW BYTE 00D6 +1 113 DAC1H DATA 0D6H ; DAC 1 REGISTER - HIGH BYTE 00D7 +1 114 DAC1CN DATA 0D7H ; DAC 1 CONTROL 00D8 +1 115 PCA0CN DATA 0D8H ; PCA 0 COUNTER CONTROL 00D9 +1 116 PCA0MD DATA 0D9H ; PCA 0 COUNTER MODE 00DA +1 117 PCA0CPM0 DATA 0DAH ; CONTROL REGISTER FOR PCA 0 MODULE 0 00DB +1 118 PCA0CPM1 DATA 0DBH ; CONTROL REGISTER FOR PCA 0 MODULE 1 00DC +1 119 PCA0CPM2 DATA 0DCH ; CONTROL REGISTER FOR PCA 0 MODULE 2 00DD +1 120 PCA0CPM3 DATA 0DDH ; CONTROL REGISTER FOR PCA 0 MODULE 3 00DE +1 121 PCA0CPM4 DATA 0DEH ; CONTROL REGISTER FOR PCA 0 MODULE 4 00E0 +1 122 ACC DATA 0E0H ; ACCUMULATOR 00E1 +1 123 XBR0 DATA 0E1H ; DIGITAL CROSSBAR CONFIGURATION REGISTER 0 00E2 +1 124 XBR1 DATA 0E2H ; DIGITAL CROSSBAR CONFIGURATION REGISTER 1 A51 MACRO ASSEMBLER BLINK 10/07/2004 09:28:42 PAGE 3 00E3 +1 125 XBR2 DATA 0E3H ; DIGITAL CROSSBAR CONFIGURATION REGISTER 2 00E4 +1 126 RCAP4L DATA 0E4H ; TIMER 4 CAPTURE REGISTER - LOW BYTE 00E5 +1 127 RCAP4H DATA 0E5H ; TIMER 4 CAPTURE REGISTER - HIGH BYTE 00E6 +1 128 EIE1 DATA 0E6H ; EXTERNAL INTERRUPT ENABLE 1 00E7 +1 129 EIE2 DATA 0E7H ; EXTERNAL INTERRUPT ENABLE 2 00E8 +1 130 ADC0CN DATA 0E8H ; ADC 0 CONTROL 00E9 +1 131 PCA0L DATA 0E9H ; PCA 0 TIMER - LOW BYTE 00EA +1 132 PCA0CPL0 DATA 0EAH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - LOW BYTE 00EB +1 133 PCA0CPL1 DATA 0EBH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - LOW BYTE 00EC +1 134 PCA0CPL2 DATA 0ECH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - LOW BYTE 00ED +1 135 PCA0CPL3 DATA 0EDH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - LOW BYTE 00EE +1 136 PCA0CPL4 DATA 0EEH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - LOW BYTE 00EF +1 137 RSTSRC DATA 0EFH ; RESET SOURCE 00F0 +1 138 B DATA 0F0H ; B REGISTER 00F1 +1 139 SCON1 DATA 0F1H ; SERIAL PORT 1 CONTROL 00F2 +1 140 SBUF1 DATA 0F2H ; SERAIL PORT 1 DATA 00F3 +1 141 SADDR1 DATA 0F3H ; SERAIL PORT 1 00F4 +1 142 TL4 DATA 0F4H ; TIMER 4 DATA - LOW BYTE 00F5 +1 143 TH4 DATA 0F5H ; TIMER 4 DATA - HIGH BYTE 00F6 +1 144 EIP1 DATA 0F6H ; EXTERNAL INTERRUPT PRIORITY REGISTER 1 00F7 +1 145 EIP2 DATA 0F7H ; EXTERNAL INTERRUPT PRIORITY REGISTER 2 00F8 +1 146 SPI0CN DATA 0F8H ; SERIAL PERIPHERAL INTERFACE 0 CONTROL 00F9 +1 147 PCA0H DATA 0F9H ; PCA 0 TIMER - HIGH BYTE 00FA +1 148 PCA0CPH0 DATA 0FAH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - HIGH BYTE 00FB +1 149 PCA0CPH1 DATA 0FBH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - HIGH BYTE 00FC +1 150 PCA0CPH2 DATA 0FCH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - HIGH BYTE 00FD +1 151 PCA0CPH3 DATA 0FDH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - HIGH BYTE 00FE +1 152 PCA0CPH4 DATA 0FEH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - HIGH BYTE 00FF +1 153 WDTCN DATA 0FFH ; WATCHDOG TIMER CONTROL +1 154 ; +1 155 ;------------------------------------------------------------------------------ +1 156 ;BIT DEFINITIONS +1 157 ; +1 158 ; TCON 88H 0088 +1 159 IT0 BIT TCON.0 ; EXT. INTERRUPT 0 TYPE 0089 +1 160 IE0 BIT TCON.1 ; EXT. INTERRUPT 0 EDGE FLAG 008A +1 161 IT1 BIT TCON.2 ; EXT. INTERRUPT 1 TYPE 008B +1 162 IE1 BIT TCON.3 ; EXT. INTERRUPT 1 EDGE FLAG 008C +1 163 TR0 BIT TCON.4 ; TIMER 0 ON/OFF CONTROL 008D +1 164 TF0 BIT TCON.5 ; TIMER 0 OVERFLOW FLAG 008E +1 165 TR1 BIT TCON.6 ; TIMER 1 ON/OFF CONTROL 008F +1 166 TF1 BIT TCON.7 ; TIMER 1 OVERFLOW FLAG +1 167 ; +1 168 ; SCON0 98H 0098 +1 169 RI BIT SCON0.0 ; RECEIVE INTERRUPT FLAG 0099 +1 170 TI BIT SCON0.1 ; TRANSMIT INTERRUPT FLAG 009A +1 171 RB8 BIT SCON0.2 ; RECEIVE BIT 8 009B +1 172 TB8 BIT SCON0.3 ; TRANSMIT BIT 8 009C +1 173 REN BIT SCON0.4 ; RECEIVE ENABLE 009D +1 174 SM2 BIT SCON0.5 ; MULTIPROCESSOR COMMUNICATION ENABLE 009E +1 175 SM1 BIT SCON0.6 ; SERIAL MODE CONTROL BIT 1 009F +1 176 SM0 BIT SCON0.7 ; SERIAL MODE CONTROL BIT 0 +1 177 ; +1 178 ; IE A8H 00A8 +1 179 EX0 BIT IE.0 ; EXTERNAL INTERRUPT 0 ENABLE 00A9 +1 180 ET0 BIT IE.1 ; TIMER 0 INTERRUPT ENABLE 00AA +1 181 EX1 BIT IE.2 ; EXTERNAL INTERRUPT 1 ENABLE 00AB +1 182 ET1 BIT IE.3 ; TIMER 1 INTERRUPT ENABLE 00AC +1 183 ES BIT IE.4 ; SERIAL PORT INTERRUPT ENABLE 00AD +1 184 ET2 BIT IE.5 ; TIMER 2 INTERRUPT ENABLE 00AF +1 185 EA BIT IE.7 ; GLOBAL INTERRUPT ENABLE +1 186 ; +1 187 ; IP B8H 00B8 +1 188 PX0 BIT IP.0 ; EXTERNAL INTERRUPT 0 PRIORITY 00B9 +1 189 PT0 BIT IP.1 ; TIMER 0 PRIORITY 00BA +1 190 PX1 BIT IP.2 ; EXTERNAL INTERRUPT 1 PRIORITY A51 MACRO ASSEMBLER BLINK 10/07/2004 09:28:42 PAGE 4 00BB +1 191 PT1 BIT IP.3 ; TIMER 1 PRIORITY 00BC +1 192 PS BIT IP.4 ; SERIAL PORT PRIORITY 00BD +1 193 PT2 BIT IP.5 ; TIMER 2 PRIORITY +1 194 ; +1 195 ; SMB0CN C0H 00C0 +1 196 SMBTOE BIT SMB0CN.0 ; SMBUS 0 TIMEOUT ENABLE 00C1 +1 197 SMBFTE BIT SMB0CN.1 ; SMBUS 0 FREE TIMER ENABLE 00C2 +1 198 AA BIT SMB0CN.2 ; SMBUS 0 ASSERT/ACKNOWLEDGE FLAG 00C3 +1 199 SI BIT SMB0CN.3 ; SMBUS 0 INTERRUPT PENDING FLAG 00C4 +1 200 STO BIT SMB0CN.4 ; SMBUS 0 STOP FLAG 00C5 +1 201 STA BIT SMB0CN.5 ; SMBUS 0 START FLAG 00C6 +1 202 ENSMB BIT SMB0CN.6 ; SMBUS 0 ENABLE +1 203 ; +1 204 ; T2CON C8H 00C8 +1 205 CPRL2 BIT T2CON.0 ; CAPTURE OR RELOAD SELECT 00C9 +1 206 CT2 BIT T2CON.1 ; TIMER OR COUNTER SELECT 00CA +1 207 TR2 BIT T2CON.2 ; TIMER 2 ON/OFF CONTROL 00CB +1 208 EXEN2 BIT T2CON.3 ; TIMER 2 EXTERNAL ENABLE FLAG 00CC +1 209 TCLK BIT T2CON.4 ; TRANSMIT CLOCK FLAG 00CD +1 210 RCLK BIT T2CON.5 ; RECEIVE CLOCK FLAG 00CE +1 211 EXF2 BIT T2CON.6 ; EXTERNAL FLAG 00CF +1 212 TF2 BIT T2CON.7 ; TIMER 2 OVERFLOW FLAG +1 213 ; +1 214 ; PSW D0H 00D0 +1 215 P BIT PSW.0 ; ACCUMULATOR PARITY FLAG 00D1 +1 216 F1 BIT PSW.1 ; USER FLAG 1 00D2 +1 217 OV BIT PSW.2 ; OVERFLOW FLAG 00D3 +1 218 RS0 BIT PSW.3 ; REGISTER BANK SELECT 0 00D4 +1 219 RS1 BIT PSW.4 ; REGISTER BANK SELECT 1 00D5 +1 220 F0 BIT PSW.5 ; USER FLAG 0 00D6 +1 221 AC BIT PSW.6 ; AUXILIARY CARRY FLAG 00D7 +1 222 CY BIT PSW.7 ; CARRY FLAG +1 223 ; +1 224 ; PCA0CN D8H 00D8 +1 225 CCF0 BIT PCA0CN.0 ; PCA 0 MODULE 0 INTERRUPT FLAG 00D9 +1 226 CCF1 BIT PCA0CN.1 ; PCA 0 MODULE 1 INTERRUPT FLAG 00DA +1 227 CCF2 BIT PCA0CN.2 ; PCA 0 MODULE 2 INTERRUPT FLAG 00DB +1 228 CCF3 BIT PCA0CN.3 ; PCA 0 MODULE 3 INTERRUPT FLAG 00DC +1 229 CCF4 BIT PCA0CN.4 ; PCA 0 MODULE 4 INTERRUPT FLAG 00DE +1 230 CR BIT PCA0CN.6 ; PCA 0 COUNTER RUN CONTROL BIT 00DF +1 231 CF BIT PCA0CN.7 ; PCA 0 COUNTER OVERFLOW FLAG +1 232 ; +1 233 ; ADC0CN E8H 00E8 +1 234 AD0LJST BIT ADC0CN.0 ; ADC 0 RIGHT JUSTIFY DATA BIT 00E9 +1 235 AD0WINT BIT ADC0CN.1 ; ADC 0 WINDOW COMPARE INTERRUPT FLAG 00EA +1 236 AD0STM0 BIT ADC0CN.2 ; ADC 0 START OF CONVERSION MODE BIT 0 00EB +1 237 AD0STM1 BIT ADC0CN.3 ; ADC 0 START OF CONVERSION MODE BIT 1 00EC +1 238 AD0BUSY BIT ADC0CN.4 ; ADC 0 BUSY FLAG 00ED +1 239 AD0INT BIT ADC0CN.5 ; ADC 0 CONVERISION COMPLETE INTERRUPT FLAG 00EE +1 240 AD0TM BIT ADC0CN.6 ; ADC 0 TRACK MODE 00EF +1 241 AD0EN BIT ADC0CN.7 ; ADC 0 ENABLE +1 242 ; +1 243 ; SPI0CN F8H 00F8 +1 244 SPIEN BIT SPI0CN.0 ; SPI 0 SPI ENABLE 00F9 +1 245 MSTEN BIT SPI0CN.1 ; SPI 0 MASTER ENABLE 00FA +1 246 SLVSEL BIT SPI0CN.2 ; SPI 0 SLAVE SELECT 00FB +1 247 TXBSY BIT SPI0CN.3 ; SPI 0 TX BUSY FLAG 00FC +1 248 RXOVRN BIT SPI0CN.4 ; SPI 0 RX OVERRUN FLAG 00FD +1 249 MODF BIT SPI0CN.5 ; SPI 0 MODE FAULT FLAG 00FE +1 250 WCOL BIT SPI0CN.6 ; SPI 0 WRITE COLLISION FLAG 00FF +1 251 SPIF BIT SPI0CN.7 ; SPI 0 INTERRUPT FLAG 252 253 ;----------------------------------------------------------------------------- 254 ; EQUATES 255 ;----------------------------------------------------------------------------- 256 A51 MACRO ASSEMBLER BLINK 10/07/2004 09:28:42 PAGE 5 0096 257 GREEN_LED equ P1.6 ; Port I/O pin connected to Green LED. 258 259 ;----------------------------------------------------------------------------- 260 ; RESET and INTERRUPT VECTORS 261 ;----------------------------------------------------------------------------- 262 263 ; Reset Vector ---- 264 cseg AT 0 0000 020000 F 265 ljmp Main ; Locate a jump to the start of code at 266 ; the reset vector. 267 268 ;----------------------------------------------------------------------------- 269 ; CODE SEGMENT 270 ;----------------------------------------------------------------------------- 271 272 273 Blink segment CODE 274 ---- 275 rseg Blink ; Switch to this code segment. 276 using 0 ; Specify register bank for the following 277 ; program code. 278 0000 279 Main: ; Disable the WDT. (IRQs not enabled at this point.) 280 ; If interrupts were enabled, we would need to explicitly disable 281 ; them so that the 2nd move to WDTCN occurs no more than four clock 282 ; cycles after the first move to WDTCN. 283 0000 75FFDE 284 mov WDTCN, #0DEh 0003 75FFAD 285 mov WDTCN, #0ADh 286 287 ; Enable the Port I/O Crossbar 0006 75E340 288 mov XBR2, #40h 289 290 ; Set P1.6 (LED) as digital output in push-pull mode. 0009 43BD40 291 orl P1MDIN, #40h 000C 43A540 292 orl P1MDOUT,#40h 293 294 ; Initialize LED to OFF 000F C296 295 clr GREEN_LED 296 297 ; Simple delay loop. 0011 7F03 298 Loop2: mov R7, #03h 0013 7E00 299 Loop1: mov R6, #00h 0015 7D00 300 Loop0: mov R5, #00h 0017 DDFE 301 djnz R5, $ 0019 DEFA 302 djnz R6, Loop0 001B DFF6 303 djnz R7, Loop1 001D B296 304 cpl GREEN_LED ; Toggle LED. 001F 80F0 305 jmp Loop2 306 307 308 ;----------------------------------------------------------------------------- 309 ; End of file. 310 311 END A51 MACRO ASSEMBLER BLINK 10/07/2004 09:28:42 PAGE 6 XREF SYMBOL TABLE LISTING ---- ------ ----- ------- N A M E T Y P E V A L U E ATTRIBUTES / REFERENCES AA . . . . . . . . B ADDR 00C0H.2 A 198# AC . . . . . . . . B ADDR 00D0H.6 A 221# ACC. . . . . . . . D ADDR 00E0H A 122# AD0BUSY. . . . . . B ADDR 00E8H.4 A 238# AD0EN. . . . . . . B ADDR 00E8H.7 A 241# AD0INT . . . . . . B ADDR 00E8H.5 A 239# AD0LJST. . . . . . B ADDR 00E8H.0 A 234# AD0STM0. . . . . . B ADDR 00E8H.2 A 236# AD0STM1. . . . . . B ADDR 00E8H.3 A 237# AD0TM. . . . . . . B ADDR 00E8H.6 A 240# AD0WINT. . . . . . B ADDR 00E8H.1 A 235# ADC0CF . . . . . . D ADDR 00BCH A 88# ADC0CN . . . . . . D ADDR 00E8H A 130# 234 235 236 237 238 239 240 241 ADC0GTH. . . . . . D ADDR 00C5H A 97# ADC0GTL. . . . . . D ADDR 00C4H A 96# ADC0H. . . . . . . D ADDR 00BFH A 91# ADC0L. . . . . . . D ADDR 00BEH A 90# ADC0LTH. . . . . . D ADDR 00C7H A 99# ADC0LTL. . . . . . D ADDR 00C6H A 98# ADC1 . . . . . . . D ADDR 009CH A 59# ADC1CF . . . . . . D ADDR 00ABH A 73# ADC1CN . . . . . . D ADDR 00AAH A 72# AMX0CF . . . . . . D ADDR 00BAH A 86# AMX0SL . . . . . . D ADDR 00BBH A 87# AMX1SL . . . . . . D ADDR 00ACH A 74# B. . . . . . . . . D ADDR 00F0H A 138# BLINK. . . . . . . C SEG 0021H REL=UNIT 273# 275 CCF0 . . . . . . . B ADDR 00D8H.0 A 225# CCF1 . . . . . . . B ADDR 00D8H.1 A 226# CCF2 . . . . . . . B ADDR 00D8H.2 A 227# CCF3 . . . . . . . B ADDR 00D8H.3 A 228# CCF4 . . . . . . . B ADDR 00D8H.4 A 229# CF . . . . . . . . B ADDR 00D8H.7 A 231# CKCON. . . . . . . D ADDR 008EH A 46# CPRL2. . . . . . . B ADDR 00C8H.0 A 205# CPT0CN . . . . . . D ADDR 009EH A 61# CPT1CN . . . . . . D ADDR 009FH A 62# CR . . . . . . . . B ADDR 00D8H.6 A 230# CT2. . . . . . . . B ADDR 00C8H.1 A 206# CY . . . . . . . . B ADDR 00D0H.7 A 222# DAC0CN . . . . . . D ADDR 00D4H A 111# DAC0H. . . . . . . D ADDR 00D3H A 110# DAC0L. . . . . . . D ADDR 00D2H A 109# DAC1CN . . . . . . D ADDR 00D7H A 114# DAC1H. . . . . . . D ADDR 00D6H A 113# DAC1L. . . . . . . D ADDR 00D5H A 112# DPH. . . . . . . . D ADDR 0083H A 35# DPL. . . . . . . . D ADDR 0082H A 34# EA . . . . . . . . B ADDR 00A8H.7 A 185# EIE1 . . . . . . . D ADDR 00E6H A 128# EIE2 . . . . . . . D ADDR 00E7H A 129# EIP1 . . . . . . . D ADDR 00F6H A 144# EIP2 . . . . . . . D ADDR 00F7H A 145# EMI0CF . . . . . . D ADDR 00A3H A 65# EMI0CN . . . . . . D ADDR 00AFH A 77# EMI0TC . . . . . . D ADDR 00A1H A 64# ENSMB. . . . . . . B ADDR 00C0H.6 A 202# ES . . . . . . . . B ADDR 00A8H.4 A 183# ET0. . . . . . . . B ADDR 00A8H.1 A 180# ET1. . . . . . . . B ADDR 00A8H.3 A 182# A51 MACRO ASSEMBLER BLINK 10/07/2004 09:28:42 PAGE 7 ET2. . . . . . . . B ADDR 00A8H.5 A 184# EX0. . . . . . . . B ADDR 00A8H.0 A 179# EX1. . . . . . . . B ADDR 00A8H.2 A 181# EXEN2. . . . . . . B ADDR 00C8H.3 A 208# EXF2 . . . . . . . B ADDR 00C8H.6 A 211# F0 . . . . . . . . B ADDR 00D0H.5 A 220# F1 . . . . . . . . B ADDR 00D0H.1 A 216# FLACL. . . . . . . D ADDR 00B7H A 83# FLSCL. . . . . . . D ADDR 00B6H A 82# GREEN_LED. . . . . B ADDR 0090H.6 A 257# 295 304 IE . . . . . . . . D ADDR 00A8H A 70# 179 180 181 182 183 184 185 IE0. . . . . . . . B ADDR 0088H.1 A 160# IE1. . . . . . . . B ADDR 0088H.3 A 162# IP . . . . . . . . D ADDR 00B8H A 84# 188 189 190 191 192 193 IT0. . . . . . . . B ADDR 0088H.0 A 159# IT1. . . . . . . . B ADDR 0088H.2 A 161# LOOP0. . . . . . . C ADDR 0015H R SEG=BLINK 300# 302 LOOP1. . . . . . . C ADDR 0013H R SEG=BLINK 299# 303 LOOP2. . . . . . . C ADDR 0011H R SEG=BLINK 298# 305 MAIN . . . . . . . C ADDR 0000H R SEG=BLINK 265 279# MODF . . . . . . . B ADDR 00F8H.5 A 249# MSTEN. . . . . . . B ADDR 00F8H.1 A 245# OSCICN . . . . . . D ADDR 00B2H A 80# OSCXCN . . . . . . D ADDR 00B1H A 79# OV . . . . . . . . B ADDR 00D0H.2 A 217# P. . . . . . . . . B ADDR 00D0H.0 A 215# P0 . . . . . . . . D ADDR 0080H A 32# P0MDOUT. . . . . . D ADDR 00A4H A 66# P1 . . . . . . . . D ADDR 0090H A 48# 257 P1MDIN . . . . . . D ADDR 00BDH A 89# 291 P1MDOUT. . . . . . D ADDR 00A5H A 67# 292 P2 . . . . . . . . D ADDR 00A0H A 63# P2MDOUT. . . . . . D ADDR 00A6H A 68# P3 . . . . . . . . D ADDR 00B0H A 78# P3IF . . . . . . . D ADDR 00ADH A 75# P3MDOUT. . . . . . D ADDR 00A7H A 69# P4 . . . . . . . . D ADDR 0084H A 36# P5 . . . . . . . . D ADDR 0085H A 37# P6 . . . . . . . . D ADDR 0086H A 38# P7 . . . . . . . . D ADDR 0096H A 54# P74OUT . . . . . . D ADDR 00B5H A 81# PCA0CN . . . . . . D ADDR 00D8H A 115# 225 226 227 228 229 230 231 PCA0CPH0 . . . . . D ADDR 00FAH A 148# PCA0CPH1 . . . . . D ADDR 00FBH A 149# PCA0CPH2 . . . . . D ADDR 00FCH A 150# PCA0CPH3 . . . . . D ADDR 00FDH A 151# PCA0CPH4 . . . . . D ADDR 00FEH A 152# PCA0CPL0 . . . . . D ADDR 00EAH A 132# PCA0CPL1 . . . . . D ADDR 00EBH A 133# PCA0CPL2 . . . . . D ADDR 00ECH A 134# PCA0CPL3 . . . . . D ADDR 00EDH A 135# PCA0CPL4 . . . . . D ADDR 00EEH A 136# PCA0CPM0 . . . . . D ADDR 00DAH A 117# PCA0CPM1 . . . . . D ADDR 00DBH A 118# PCA0CPM2 . . . . . D ADDR 00DCH A 119# PCA0CPM3 . . . . . D ADDR 00DDH A 120# PCA0CPM4 . . . . . D ADDR 00DEH A 121# PCA0H. . . . . . . D ADDR 00F9H A 147# PCA0L. . . . . . . D ADDR 00E9H A 131# PCA0MD . . . . . . D ADDR 00D9H A 116# PCON . . . . . . . D ADDR 0087H A 39# PS . . . . . . . . B ADDR 00B8H.4 A 192# PSCTL. . . . . . . D ADDR 008FH A 47# PSW. . . . . . . . D ADDR 00D0H A 107# 215 216 217 218 219 220 221 222 PT0. . . . . . . . B ADDR 00B8H.1 A 189# PT1. . . . . . . . B ADDR 00B8H.3 A 191# A51 MACRO ASSEMBLER BLINK 10/07/2004 09:28:42 PAGE 8 PT2. . . . . . . . B ADDR 00B8H.5 A 193# PX0. . . . . . . . B ADDR 00B8H.0 A 188# PX1. . . . . . . . B ADDR 00B8H.2 A 190# RB8. . . . . . . . B ADDR 0098H.2 A 171# RCAP2H . . . . . . D ADDR 00CBH A 103# RCAP2L . . . . . . D ADDR 00CAH A 102# RCAP4H . . . . . . D ADDR 00E5H A 127# RCAP4L . . . . . . D ADDR 00E4H A 126# RCLK . . . . . . . B ADDR 00C8H.5 A 210# REF0CN . . . . . . D ADDR 00D1H A 108# REN. . . . . . . . B ADDR 0098H.4 A 173# RI . . . . . . . . B ADDR 0098H.0 A 169# RS0. . . . . . . . B ADDR 00D0H.3 A 218# RS1. . . . . . . . B ADDR 00D0H.4 A 219# RSTSRC . . . . . . D ADDR 00EFH A 137# RXOVRN . . . . . . B ADDR 00F8H.4 A 248# SADDR0 . . . . . . D ADDR 00A9H A 71# SADDR1 . . . . . . D ADDR 00F3H A 141# SADEN0 . . . . . . D ADDR 00B9H A 85# SADEN1 . . . . . . D ADDR 00AEH A 76# SBUF0. . . . . . . D ADDR 0099H A 56# SBUF1. . . . . . . D ADDR 00F2H A 140# SCON0. . . . . . . D ADDR 0098H A 55# 169 170 171 172 173 174 175 176 SCON1. . . . . . . D ADDR 00F1H A 139# SI . . . . . . . . B ADDR 00C0H.3 A 199# SLVSEL . . . . . . B ADDR 00F8H.2 A 246# SM0. . . . . . . . B ADDR 0098H.7 A 176# SM1. . . . . . . . B ADDR 0098H.6 A 175# SM2. . . . . . . . B ADDR 0098H.5 A 174# SMB0ADR. . . . . . D ADDR 00C3H A 95# SMB0CN . . . . . . D ADDR 00C0H A 92# 196 197 198 199 200 201 202 SMB0CR . . . . . . D ADDR 00CFH A 106# SMB0DAT. . . . . . D ADDR 00C2H A 94# SMB0STA. . . . . . D ADDR 00C1H A 93# SMBFTE . . . . . . B ADDR 00C0H.1 A 197# SMBTOE . . . . . . B ADDR 00C0H.0 A 196# SP . . . . . . . . D ADDR 0081H A 33# SPI0CFG. . . . . . D ADDR 009AH A 57# SPI0CKR. . . . . . D ADDR 009DH A 60# SPI0CN . . . . . . D ADDR 00F8H A 146# 244 245 246 247 248 249 250 251 SPI0DAT. . . . . . D ADDR 009BH A 58# SPIEN. . . . . . . B ADDR 00F8H.0 A 244# SPIF . . . . . . . B ADDR 00F8H.7 A 251# STA. . . . . . . . B ADDR 00C0H.5 A 201# STO. . . . . . . . B ADDR 00C0H.4 A 200# T2CON. . . . . . . D ADDR 00C8H A 100# 205 206 207 208 209 210 211 212 T4CON. . . . . . . D ADDR 00C9H A 101# TB8. . . . . . . . B ADDR 0098H.3 A 172# TCLK . . . . . . . B ADDR 00C8H.4 A 209# TCON . . . . . . . D ADDR 0088H A 40# 159 160 161 162 163 164 165 166 TF0. . . . . . . . B ADDR 0088H.5 A 164# TF1. . . . . . . . B ADDR 0088H.7 A 166# TF2. . . . . . . . B ADDR 00C8H.7 A 212# TH0. . . . . . . . D ADDR 008CH A 44# TH1. . . . . . . . D ADDR 008DH A 45# TH2. . . . . . . . D ADDR 00CDH A 105# TH4. . . . . . . . D ADDR 00F5H A 143# TI . . . . . . . . B ADDR 0098H.1 A 170# TL0. . . . . . . . D ADDR 008AH A 42# TL1. . . . . . . . D ADDR 008BH A 43# TL2. . . . . . . . D ADDR 00CCH A 104# TL4. . . . . . . . D ADDR 00F4H A 142# TMOD . . . . . . . D ADDR 0089H A 41# TMR3CN . . . . . . D ADDR 0091H A 49# TMR3H. . . . . . . D ADDR 0095H A 53# TMR3L. . . . . . . D ADDR 0094H A 52# A51 MACRO ASSEMBLER BLINK 10/07/2004 09:28:42 PAGE 9 TMR3RLH. . . . . . D ADDR 0093H A 51# TMR3RLL. . . . . . D ADDR 0092H A 50# TR0. . . . . . . . B ADDR 0088H.4 A 163# TR1. . . . . . . . B ADDR 0088H.6 A 165# TR2. . . . . . . . B ADDR 00C8H.2 A 207# TXBSY. . . . . . . B ADDR 00F8H.3 A 247# WCOL . . . . . . . B ADDR 00F8H.6 A 250# WDTCN. . . . . . . D ADDR 00FFH A 153# 284 285 XBR0 . . . . . . . D ADDR 00E1H A 123# XBR1 . . . . . . . D ADDR 00E2H A 124# XBR2 . . . . . . . D ADDR 00E3H A 125# 288 REGISTER BANK(S) USED: 0 ASSEMBLY COMPLETE. 0 WARNING(S), 0 ERROR(S)