A51 MACRO ASSEMBLER MEM_TEST 06/26/2003 11:09:26 PAGE 1 MACRO ASSEMBLER A51 V6.14a OBJECT MODULE PLACED IN mem_test.OBJ ASSEMBLER INVOKED BY: C:\CYGNAL\IDEFILES\C51\BIN\A51.EXE mem_test.asm XR GEN DB EP NOMOD51 LOC OBJ LINE SOURCE 1 ;----------------------------------------------------------------------------- 2 ; 3 ; FILE NAME : MEM_TEST.ASM 4 ; TARGET MCU : C8051F020 5 ; DESCRIPTION : This program disables the watchdog timer and writes value in 6 ; acc A to address po inted to by DPTR in external SRAM on 7 ; plug-in board AB1. 8 ; 9 ; NOTES: 10 ; (1) /WE = P4.7 (/WR) 11 ; (2) /CE = P4.4 (J1 closed on AB1 board) 12 ; (3) /OE = P4.6 (/RD) 13 ; (4) D0-D7 = P7.0-P7.7 (DATA bus) 14 ; (5) A0-A7 = P6.0-P6.7 (ADR bus lo byte) 15 ; (6) A8-A15 = P5.0-P5.7 (ADR bus hi byte) 16 ; (7) A16 = P4.5 (BANK select) 17 ; 18 ; 19 ;----------------------------------------------------------------------------- 20 21 ;$include (c8051F020.inc) ; Include register definition file +1 22 ;----------------------------------------------------------------------------- +1 23 ; Copyright (C) 2001 CYGNAL INTEGRATED PRODUCTS, INC. +1 24 ; All rights reserved. +1 25 ; +1 26 ; +1 27 ; FILE NAME : C8051F020.INC +1 28 ; TARGET MCUs : C8051F020, 'F021, 'F022, 'F023 +1 29 ; DESCRIPTION : Register/bit definitions for the C8051F02x product family. +1 30 ; +1 31 ; REVISION 1.0 +1 32 ; +1 33 ;----------------------------------------------------------------------------- +1 34 ;REGISTER DEFINITIONS +1 35 ; 0080 +1 36 P0 DATA 080H ; PORT 0 0081 +1 37 SP DATA 081H ; STACK POINTER 0082 +1 38 DPL DATA 082H ; DATA POINTER - LOW BYTE 0083 +1 39 DPH DATA 083H ; DATA POINTER - HIGH BYTE 0084 +1 40 P4 DATA 084H ; PORT 4 0085 +1 41 P5 DATA 085H ; PORT 5 0086 +1 42 P6 DATA 086H ; PORT 6 0087 +1 43 PCON DATA 087H ; POWER CONTROL 0088 +1 44 TCON DATA 088H ; TIMER CONTROL 0089 +1 45 TMOD DATA 089H ; TIMER MODE 008A +1 46 TL0 DATA 08AH ; TIMER 0 - LOW BYTE 008B +1 47 TL1 DATA 08BH ; TIMER 1 - LOW BYTE 008C +1 48 TH0 DATA 08CH ; TIMER 0 - HIGH BYTE 008D +1 49 TH1 DATA 08DH ; TIMER 1 - HIGH BYTE 008E +1 50 CKCON DATA 08EH ; CLOCK CONTROL 008F +1 51 PSCTL DATA 08FH ; PROGRAM STORE R/W CONTROL 0090 +1 52 P1 DATA 090H ; PORT 1 0091 +1 53 TMR3CN DATA 091H ; TIMER 3 CONTROL 0092 +1 54 TMR3RLL DATA 092H ; TIMER 3 RELOAD REGISTER - LOW BYTE 0093 +1 55 TMR3RLH DATA 093H ; TIMER 3 RELOAD REGISTER - HIGH BYTE 0094 +1 56 TMR3L DATA 094H ; TIMER 3 - LOW BYTE 0095 +1 57 TMR3H DATA 095H ; TIMER 3 - HIGH BYTE A51 MACRO ASSEMBLER MEM_TEST 06/26/2003 11:09:26 PAGE 2 0096 +1 58 P7 DATA 096H ; PORT 7 0098 +1 59 SCON0 DATA 098H ; SERIAL PORT 0 CONTROL 0099 +1 60 SBUF0 DATA 099H ; SERIAL PORT 0 BUFFER 009A +1 61 SPI0CFG DATA 09AH ; SERIAL PERIPHERAL INTERFACE 0 CONFIGURATION 009B +1 62 SPI0DAT DATA 09BH ; SERIAL PERIPHERAL INTERFACE 0 DATA 009C +1 63 ADC1 DATA 09CH ; ADC 1 DATA 009D +1 64 SPI0CKR DATA 09DH ; SERIAL PERIPHERAL INTERFACE 0 CLOCK RATE CONTROL 009E +1 65 CPT0CN DATA 09EH ; COMPARATOR 0 CONTROL 009F +1 66 CPT1CN DATA 09FH ; COMPARATOR 1 CONTROL 00A0 +1 67 P2 DATA 0A0H ; PORT 2 00A1 +1 68 EMI0TC DATA 0A1H ; EMIF TIMING CONTROL 00A3 +1 69 EMI0CF DATA 0A3H ; EXTERNAL MEMORY INTERFACE (EMIF) CONFIGURATION 00A4 +1 70 P0MDOUT DATA 0A4H ; PORT 0 OUTPUT MODE CONFIGURATION 00A5 +1 71 P1MDOUT DATA 0A5H ; PORT 1 OUTPUT MODE CONFIGURATION 00A6 +1 72 P2MDOUT DATA 0A6H ; PORT 2 OUTPUT MODE CONFIGURATION 00A7 +1 73 P3MDOUT DATA 0A7H ; PORT 3 OUTPUT MODE CONFIGURATION 00A8 +1 74 IE DATA 0A8H ; INTERRUPT ENABLE 00A9 +1 75 SADDR0 DATA 0A9H ; SERIAL PORT 0 SLAVE ADDRESS 00AA +1 76 ADC1CN DATA 0AAH ; ADC 1 CONTROL 00AB +1 77 ADC1CF DATA 0ABH ; ADC 1 ANALOG MUX CONFIGURATION 00AC +1 78 AMX1SL DATA 0ACH ; ADC 1 ANALOG MUX CHANNEL SELECT 00AD +1 79 P3IF DATA 0ADH ; PORT 3 EXTERNAL INTERRUPT FLAGS 00AE +1 80 SADEN1 DATA 0AEH ; SERIAL PORT 1 SLAVE ADDRESS MASK 00AF +1 81 EMI0CN DATA 0AFH ; EXTERNAL MEMORY INTERFACE CONTROL 00B0 +1 82 P3 DATA 0B0H ; PORT 3 00B1 +1 83 OSCXCN DATA 0B1H ; EXTERNAL OSCILLATOR CONTROL 00B2 +1 84 OSCICN DATA 0B2H ; INTERNAL OSCILLATOR CONTROL 00B5 +1 85 P74OUT DATA 0B5H ; PORTS 4 - 7 OUTPUT MODE 00B6 +1 86 FLSCL DATA 0B6H ; FLASH MEMORY TIMING PRESCALER 00B7 +1 87 FLACL DATA 0B7H ; FLASH ACESS LIMIT 00B8 +1 88 IP DATA 0B8H ; INTERRUPT PRIORITY 00B9 +1 89 SADEN0 DATA 0B9H ; SERIAL PORT 0 SLAVE ADDRESS MASK 00BA +1 90 AMX0CF DATA 0BAH ; ADC 0 MUX CONFIGURATION 00BB +1 91 AMX0SL DATA 0BBH ; ADC 0 MUX CHANNEL SELECTION 00BC +1 92 ADC0CF DATA 0BCH ; ADC 0 CONFIGURATION 00BD +1 93 P1MDIN DATA 0BDH ; PORT 1 INPUT MODE 00BE +1 94 ADC0L DATA 0BEH ; ADC 0 DATA - LOW BYTE 00BF +1 95 ADC0H DATA 0BFH ; ADC 0 DATA - HIGH BYTE 00C0 +1 96 SMB0CN DATA 0C0H ; SMBUS 0 CONTROL 00C1 +1 97 SMB0STA DATA 0C1H ; SMBUS 0 STATUS 00C2 +1 98 SMB0DAT DATA 0C2H ; SMBUS 0 DATA 00C3 +1 99 SMB0ADR DATA 0C3H ; SMBUS 0 SLAVE ADDRESS 00C4 +1 100 ADC0GTL DATA 0C4H ; ADC 0 GREATER-THAN REGISTER - LOW BYTE 00C5 +1 101 ADC0GTH DATA 0C5H ; ADC 0 GREATER-THAN REGISTER - HIGH BYTE 00C6 +1 102 ADC0LTL DATA 0C6H ; ADC 0 LESS-THAN REGISTER - LOW BYTE 00C7 +1 103 ADC0LTH DATA 0C7H ; ADC 0 LESS-THAN REGISTER - HIGH BYTE 00C8 +1 104 T2CON DATA 0C8H ; TIMER 2 CONTROL 00C9 +1 105 T4CON DATA 0C9H ; TIMER 4 CONTROL 00CA +1 106 RCAP2L DATA 0CAH ; TIMER 2 CAPTURE REGISTER - LOW BYTE 00CB +1 107 RCAP2H DATA 0CBH ; TIMER 2 CAPTURE REGISTER - HIGH BYTE 00CC +1 108 TL2 DATA 0CCH ; TIMER 2 - LOW BYTE 00CD +1 109 TH2 DATA 0CDH ; TIMER 2 - HIGH BYTE 00CF +1 110 SMB0CR DATA 0CFH ; SMBUS 0 CLOCK RATE 00D0 +1 111 PSW DATA 0D0H ; PROGRAM STATUS WORD 00D1 +1 112 REF0CN DATA 0D1H ; VOLTAGE REFERENCE 0 CONTROL 00D2 +1 113 DAC0L DATA 0D2H ; DAC 0 REGISTER - LOW BYTE 00D3 +1 114 DAC0H DATA 0D3H ; DAC 0 REGISTER - HIGH BYTE 00D4 +1 115 DAC0CN DATA 0D4H ; DAC 0 CONTROL 00D5 +1 116 DAC1L DATA 0D5H ; DAC 1 REGISTER - LOW BYTE 00D6 +1 117 DAC1H DATA 0D6H ; DAC 1 REGISTER - HIGH BYTE 00D7 +1 118 DAC1CN DATA 0D7H ; DAC 1 CONTROL 00D8 +1 119 PCA0CN DATA 0D8H ; PCA 0 COUNTER CONTROL 00D9 +1 120 PCA0MD DATA 0D9H ; PCA 0 COUNTER MODE 00DA +1 121 PCA0CPM0 DATA 0DAH ; CONTROL REGISTER FOR PCA 0 MODULE 0 00DB +1 122 PCA0CPM1 DATA 0DBH ; CONTROL REGISTER FOR PCA 0 MODULE 1 00DC +1 123 PCA0CPM2 DATA 0DCH ; CONTROL REGISTER FOR PCA 0 MODULE 2 A51 MACRO ASSEMBLER MEM_TEST 06/26/2003 11:09:26 PAGE 3 00DD +1 124 PCA0CPM3 DATA 0DDH ; CONTROL REGISTER FOR PCA 0 MODULE 3 00DE +1 125 PCA0CPM4 DATA 0DEH ; CONTROL REGISTER FOR PCA 0 MODULE 4 00E0 +1 126 ACC DATA 0E0H ; ACCUMULATOR 00E1 +1 127 XBR0 DATA 0E1H ; DIGITAL CROSSBAR CONFIGURATION REGISTER 0 00E2 +1 128 XBR1 DATA 0E2H ; DIGITAL CROSSBAR CONFIGURATION REGISTER 1 00E3 +1 129 XBR2 DATA 0E3H ; DIGITAL CROSSBAR CONFIGURATION REGISTER 2 00E4 +1 130 RCAP4L DATA 0E4H ; TIMER 4 CAPTURE REGISTER - LOW BYTE 00E5 +1 131 RCAP4H DATA 0E5H ; TIMER 4 CAPTURE REGISTER - HIGH BYTE 00E6 +1 132 EIE1 DATA 0E6H ; EXTERNAL INTERRUPT ENABLE 1 00E7 +1 133 EIE2 DATA 0E7H ; EXTERNAL INTERRUPT ENABLE 2 00E8 +1 134 ADC0CN DATA 0E8H ; ADC 0 CONTROL 00E9 +1 135 PCA0L DATA 0E9H ; PCA 0 TIMER - LOW BYTE 00EA +1 136 PCA0CPL0 DATA 0EAH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - LOW BYTE 00EB +1 137 PCA0CPL1 DATA 0EBH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - LOW BYTE 00EC +1 138 PCA0CPL2 DATA 0ECH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - LOW BYTE 00ED +1 139 PCA0CPL3 DATA 0EDH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - LOW BYTE 00EE +1 140 PCA0CPL4 DATA 0EEH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - LOW BYTE 00EF +1 141 RSTSRC DATA 0EFH ; RESET SOURCE 00F0 +1 142 B DATA 0F0H ; B REGISTER 00F1 +1 143 SCON1 DATA 0F1H ; SERIAL PORT 1 CONTROL 00F2 +1 144 SBUF1 DATA 0F2H ; SERAIL PORT 1 DATA 00F3 +1 145 SADDR1 DATA 0F3H ; SERAIL PORT 1 00F4 +1 146 TL4 DATA 0F4H ; TIMER 4 DATA - LOW BYTE 00F5 +1 147 TH4 DATA 0F5H ; TIMER 4 DATA - HIGH BYTE 00F6 +1 148 EIP1 DATA 0F6H ; EXTERNAL INTERRUPT PRIORITY REGISTER 1 00F7 +1 149 EIP2 DATA 0F7H ; EXTERNAL INTERRUPT PRIORITY REGISTER 2 00F8 +1 150 SPI0CN DATA 0F8H ; SERIAL PERIPHERAL INTERFACE 0 CONTROL 00F9 +1 151 PCA0H DATA 0F9H ; PCA 0 TIMER - HIGH BYTE 00FA +1 152 PCA0CPH0 DATA 0FAH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - HIGH BYTE 00FB +1 153 PCA0CPH1 DATA 0FBH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - HIGH BYTE 00FC +1 154 PCA0CPH2 DATA 0FCH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - HIGH BYTE 00FD +1 155 PCA0CPH3 DATA 0FDH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - HIGH BYTE 00FE +1 156 PCA0CPH4 DATA 0FEH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - HIGH BYTE 00FF +1 157 WDTCN DATA 0FFH ; WATCHDOG TIMER CONTROL +1 158 ; +1 159 ;------------------------------------------------------------------------------ +1 160 ;BIT DEFINITIONS +1 161 ; +1 162 ; TCON 88H 0088 +1 163 IT0 BIT TCON.0 ; EXT. INTERRUPT 0 TYPE 0089 +1 164 IE0 BIT TCON.1 ; EXT. INTERRUPT 0 EDGE FLAG 008A +1 165 IT1 BIT TCON.2 ; EXT. INTERRUPT 1 TYPE 008B +1 166 IE1 BIT TCON.3 ; EXT. INTERRUPT 1 EDGE FLAG 008C +1 167 TR0 BIT TCON.4 ; TIMER 0 ON/OFF CONTROL 008D +1 168 TF0 BIT TCON.5 ; TIMER 0 OVERFLOW FLAG 008E +1 169 TR1 BIT TCON.6 ; TIMER 1 ON/OFF CONTROL 008F +1 170 TF1 BIT TCON.7 ; TIMER 1 OVERFLOW FLAG +1 171 ; +1 172 ; SCON0 98H 0098 +1 173 RI BIT SCON0.0 ; RECEIVE INTERRUPT FLAG 0099 +1 174 TI BIT SCON0.1 ; TRANSMIT INTERRUPT FLAG 009A +1 175 RB8 BIT SCON0.2 ; RECEIVE BIT 8 009B +1 176 TB8 BIT SCON0.3 ; TRANSMIT BIT 8 009C +1 177 REN BIT SCON0.4 ; RECEIVE ENABLE 009D +1 178 SM2 BIT SCON0.5 ; MULTIPROCESSOR COMMUNICATION ENABLE 009E +1 179 SM1 BIT SCON0.6 ; SERIAL MODE CONTROL BIT 1 009F +1 180 SM0 BIT SCON0.7 ; SERIAL MODE CONTROL BIT 0 +1 181 ; +1 182 ; IE A8H 00A8 +1 183 EX0 BIT IE.0 ; EXTERNAL INTERRUPT 0 ENABLE 00A9 +1 184 ET0 BIT IE.1 ; TIMER 0 INTERRUPT ENABLE 00AA +1 185 EX1 BIT IE.2 ; EXTERNAL INTERRUPT 1 ENABLE 00AB +1 186 ET1 BIT IE.3 ; TIMER 1 INTERRUPT ENABLE 00AC +1 187 ES BIT IE.4 ; SERIAL PORT INTERRUPT ENABLE 00AD +1 188 ET2 BIT IE.5 ; TIMER 2 INTERRUPT ENABLE 00AF +1 189 EA BIT IE.7 ; GLOBAL INTERRUPT ENABLE A51 MACRO ASSEMBLER MEM_TEST 06/26/2003 11:09:26 PAGE 4 +1 190 ; +1 191 ; IP B8H 00B8 +1 192 PX0 BIT IP.0 ; EXTERNAL INTERRUPT 0 PRIORITY 00B9 +1 193 PT0 BIT IP.1 ; TIMER 0 PRIORITY 00BA +1 194 PX1 BIT IP.2 ; EXTERNAL INTERRUPT 1 PRIORITY 00BB +1 195 PT1 BIT IP.3 ; TIMER 1 PRIORITY 00BC +1 196 PS BIT IP.4 ; SERIAL PORT PRIORITY 00BD +1 197 PT2 BIT IP.5 ; TIMER 2 PRIORITY +1 198 ; +1 199 ; SMB0CN C0H 00C0 +1 200 SMBTOE BIT SMB0CN.0 ; SMBUS 0 TIMEOUT ENABLE 00C1 +1 201 SMBFTE BIT SMB0CN.1 ; SMBUS 0 FREE TIMER ENABLE 00C2 +1 202 AA BIT SMB0CN.2 ; SMBUS 0 ASSERT/ACKNOWLEDGE FLAG 00C3 +1 203 SI BIT SMB0CN.3 ; SMBUS 0 INTERRUPT PENDING FLAG 00C4 +1 204 STO BIT SMB0CN.4 ; SMBUS 0 STOP FLAG 00C5 +1 205 STA BIT SMB0CN.5 ; SMBUS 0 START FLAG 00C6 +1 206 ENSMB BIT SMB0CN.6 ; SMBUS 0 ENABLE +1 207 ; +1 208 ; T2CON C8H 00C8 +1 209 CPRL2 BIT T2CON.0 ; CAPTURE OR RELOAD SELECT 00C9 +1 210 CT2 BIT T2CON.1 ; TIMER OR COUNTER SELECT 00CA +1 211 TR2 BIT T2CON.2 ; TIMER 2 ON/OFF CONTROL 00CB +1 212 EXEN2 BIT T2CON.3 ; TIMER 2 EXTERNAL ENABLE FLAG 00CC +1 213 TCLK BIT T2CON.4 ; TRANSMIT CLOCK FLAG 00CD +1 214 RCLK BIT T2CON.5 ; RECEIVE CLOCK FLAG 00CE +1 215 EXF2 BIT T2CON.6 ; EXTERNAL FLAG 00CF +1 216 TF2 BIT T2CON.7 ; TIMER 2 OVERFLOW FLAG +1 217 ; +1 218 ; PSW D0H 00D0 +1 219 P BIT PSW.0 ; ACCUMULATOR PARITY FLAG 00D1 +1 220 F1 BIT PSW.1 ; USER FLAG 1 00D2 +1 221 OV BIT PSW.2 ; OVERFLOW FLAG 00D3 +1 222 RS0 BIT PSW.3 ; REGISTER BANK SELECT 0 00D4 +1 223 RS1 BIT PSW.4 ; REGISTER BANK SELECT 1 00D5 +1 224 F0 BIT PSW.5 ; USER FLAG 0 00D6 +1 225 AC BIT PSW.6 ; AUXILIARY CARRY FLAG 00D7 +1 226 CY BIT PSW.7 ; CARRY FLAG +1 227 ; +1 228 ; PCA0CN D8H 00D8 +1 229 CCF0 BIT PCA0CN.0 ; PCA 0 MODULE 0 INTERRUPT FLAG 00D9 +1 230 CCF1 BIT PCA0CN.1 ; PCA 0 MODULE 1 INTERRUPT FLAG 00DA +1 231 CCF2 BIT PCA0CN.2 ; PCA 0 MODULE 2 INTERRUPT FLAG 00DB +1 232 CCF3 BIT PCA0CN.3 ; PCA 0 MODULE 3 INTERRUPT FLAG 00DC +1 233 CCF4 BIT PCA0CN.4 ; PCA 0 MODULE 4 INTERRUPT FLAG 00DE +1 234 CR BIT PCA0CN.6 ; PCA 0 COUNTER RUN CONTROL BIT 00DF +1 235 CF BIT PCA0CN.7 ; PCA 0 COUNTER OVERFLOW FLAG +1 236 ; +1 237 ; ADC0CN E8H 00E8 +1 238 AD0LJST BIT ADC0CN.0 ; ADC 0 RIGHT JUSTIFY DATA BIT 00E9 +1 239 AD0WINT BIT ADC0CN.1 ; ADC 0 WINDOW COMPARE INTERRUPT FLAG 00EA +1 240 AD0STM0 BIT ADC0CN.2 ; ADC 0 START OF CONVERSION MODE BIT 0 00EB +1 241 AD0STM1 BIT ADC0CN.3 ; ADC 0 START OF CONVERSION MODE BIT 1 00EC +1 242 AD0BUSY BIT ADC0CN.4 ; ADC 0 BUSY FLAG 00ED +1 243 AD0INT BIT ADC0CN.5 ; ADC 0 CONVERISION COMPLETE INTERRUPT FLAG 00EE +1 244 AD0TM BIT ADC0CN.6 ; ADC 0 TRACK MODE 00EF +1 245 AD0EN BIT ADC0CN.7 ; ADC 0 ENABLE +1 246 ; +1 247 ; SPI0CN F8H 00F8 +1 248 SPIEN BIT SPI0CN.0 ; SPI 0 SPI ENABLE 00F9 +1 249 MSTEN BIT SPI0CN.1 ; SPI 0 MASTER ENABLE 00FA +1 250 SLVSEL BIT SPI0CN.2 ; SPI 0 SLAVE SELECT 00FB +1 251 TXBSY BIT SPI0CN.3 ; SPI 0 TX BUSY FLAG 00FC +1 252 RXOVRN BIT SPI0CN.4 ; SPI 0 RX OVERRUN FLAG 00FD +1 253 MODF BIT SPI0CN.5 ; SPI 0 MODE FAULT FLAG 00FE +1 254 WCOL BIT SPI0CN.6 ; SPI 0 WRITE COLLISION FLAG 00FF +1 255 SPIF BIT SPI0CN.7 ; SPI 0 INTERRUPT FLAG A51 MACRO ASSEMBLER MEM_TEST 06/26/2003 11:09:26 PAGE 5 256 257 ;----------------------------------------------------------------------------- 258 ; EQUATES 259 ;----------------------------------------------------------------------------- 260 261 262 ;----------------------------------------------------------------------------- 263 ; VARIABLES 264 ;----------------------------------------------------------------------------- 265 266 267 ;----------------------------------------------------------------------------- 268 ; RESET and INTERRUPT VECTORS 269 ;----------------------------------------------------------------------------- 270 271 ; Reset Vector 0000 272 org 00h 0000 020003 273 ljmp Main 274 275 ;----------------------------------------------------------------------------- 276 ; CODE SEGMENT 277 ;----------------------------------------------------------------------------- 278 0003 279 Main: ; Disable the WDT. (IRQs not enabled at this point.) 280 ; If interrupts were enabled, we would need to explicitly 281 ; disable them so that the 2nd move to WDTCN occurs no more 282 ; than four clock cycles after the first move to WDTCN. 283 0003 75FFDE 284 mov WDTCN, #0DEh 0006 75FFAD 285 mov WDTCN, #0ADh 286 ; set up the XBAR 0009 75E342 287 mov XBR2, #42h ;weak pull-ups, XBAR enable d, 288 ;non-multiplexed mode 000C 75A33F 289 mov EMI0CF, #3Fh ;EMIF active on P4-P7, EMIF in non- multi- 290 ;plexed mode, external XRAM only 291 000F 74CF 292 start: mov A, #0CFh ;clr P4.4 for /CE, P4.5 lo for lower 64k of 293 ;external 128k SRAM (bank1) 0011 F584 294 mov P4, A ;enable ext ernal /CE & lower 64k SRAM 0013 E4 295 clr A 0014 7855 296 mov R0, #055h ;value to write into SRAM 0016 E8 297 mov A, R0 ;load write value 0017 900000 298 mov DPTR, #0000h ;start at addr $00000 001A F0 299 loop: movx @DPTR, A ;write to SRAM 001B E0 300 movx A, @DPTR ;read SRAM value 001C B50056 301 cjne A, 00h, error ;compare rd/wr, jump if error 001F A3 302 inc DPTR 0020 E583 303 mov A, DPH 0022 4582 304 orl A, DPL 0024 6003 305 jz b155done 0026 E8 306 mov A, R0 0027 80F1 307 jmp loop 308 0029 74EF 309 b155done: mov A, #0EFh ;clr P4.4 for /CE, P4.5 hi for upper 64k of 310 ;external 128k SRAM (bank2) A51 MACRO ASSEMBLER MEM_TEST 06/26/2003 11:09:26 PAGE 6 002B F584 311 mov P4, A ;enable ext ernal /CE & upper 64K SRAM 002D E4 312 clr A 002E E8 313 mov A, R0 002F 900000 314 mov DPTR, #0000h ;start at addr $10000 0032 F0 315 loop1: movx @DPTR, A 0033 E0 316 movx A, @DPTR ;read SRAM value 0034 B5003E 317 cjne A, 00h, error ;compare rd/wr, jump if error 0037 A3 318 inc DPTR 0038 E583 319 mov A, DPH 003A 4582 320 orl A, DPL 003C 6003 321 jz b255done 003E E8 322 mov A, R0 003F 80F1 323 jmp loop1 324 0041 74CF 325 b255done: mov A, #0CFh ;clr P4.4 for /CE, P4.5 lo for lower 64k of 326 ;external 128k SRAM (bank1) 0043 F584 327 mov P4, A ;enable ext ernal /CE & lower 64k SRAM 0045 E4 328 clr A 0046 78AA 329 mov R0, #0AAh ;value to write into SRAM 0048 E8 330 mov A, R0 ;load write value 0049 900000 331 mov DPTR, #0000h ;start at addr $00000 004C F0 332 loop2: movx @DPTR, A 004D E0 333 movx A, @DPTR ;read SRAM value 004E B50024 334 cjne A, 00h, error ;compare rd/wr, jump if error 0051 A3 335 inc DPTR 0052 E583 336 mov A, DPH 0054 4582 337 orl A, DPL 0056 6003 338 jz b1AAdone 0058 E8 339 mov A, R0 0059 80F1 340 jmp loop2 341 005B 74EF 342 b1AAdone: mov A, #0EFh ;clr P4.4 for /CE, P4.5 hi for upper 64k of 343 ;external 128k SRAM (bank2) 005D F584 344 mov P4, A ;enable ext ernal /CE & upper 64K SRAM 005F E4 345 clr A 0060 E8 346 mov A, R0 0061 900000 347 mov DPTR, #0000h ;start at addr $10000 0064 F0 348 loop3: movx @DPTR, A 0065 E0 349 movx A, @DPTR ;read SRAM value 0066 B5000C 350 cjne A, 00h, error ;compare rd/wr, jump if error 0069 A3 351 inc DPTR 006A E583 352 mov A, DPH 006C 4582 353 orl A, DPL 006E 6003 354 jz b2AAdone 0070 E8 355 mov A, R0 0071 80F1 356 jmp loop3 357 0073 809A 358 b2AAdone: jmp start 0075 80FE 359 error: jmp $ ;error occured 360 361 362 ;----------------------------------------------------------------------------- 363 ; End of file. 364 365 END A51 MACRO ASSEMBLER MEM_TEST 06/26/2003 11:09:26 PAGE 7 XREF SYMBOL TABLE LISTING ---- ------ ----- ------- N A M E T Y P E V A L U E ATTRIBUTES / REFERENCES AA . . . . . . . . B ADDR 00C0H.2 A 202# AC . . . . . . . . B ADDR 00D0H.6 A 225# ACC. . . . . . . . D ADDR 00E0H A 126# AD0BUSY. . . . . . B ADDR 00E8H.4 A 242# AD0EN. . . . . . . B ADDR 00E8H.7 A 245# AD0INT . . . . . . B ADDR 00E8H.5 A 243# AD0LJST. . . . . . B ADDR 00E8H.0 A 238# AD0STM0. . . . . . B ADDR 00E8H.2 A 240# AD0STM1. . . . . . B ADDR 00E8H.3 A 241# AD0TM. . . . . . . B ADDR 00E8H.6 A 244# AD0WINT. . . . . . B ADDR 00E8H.1 A 239# ADC0CF . . . . . . D ADDR 00BCH A 92# ADC0CN . . . . . . D ADDR 00E8H A 134# 238 239 240 241 242 243 244 245 ADC0GTH. . . . . . D ADDR 00C5H A 101# ADC0GTL. . . . . . D ADDR 00C4H A 100# ADC0H. . . . . . . D ADDR 00BFH A 95# ADC0L. . . . . . . D ADDR 00BEH A 94# ADC0LTH. . . . . . D ADDR 00C7H A 103# ADC0LTL. . . . . . D ADDR 00C6H A 102# ADC1 . . . . . . . D ADDR 009CH A 63# ADC1CF . . . . . . D ADDR 00ABH A 77# ADC1CN . . . . . . D ADDR 00AAH A 76# AMX0CF . . . . . . D ADDR 00BAH A 90# AMX0SL . . . . . . D ADDR 00BBH A 91# AMX1SL . . . . . . D ADDR 00ACH A 78# B. . . . . . . . . D ADDR 00F0H A 142# B155DONE . . . . . C ADDR 0029H A 305 309# B1AADONE . . . . . C ADDR 005BH A 338 342# B255DONE . . . . . C ADDR 0041H A 321 325# B2AADONE . . . . . C ADDR 0073H A 354 358# CCF0 . . . . . . . B ADDR 00D8H.0 A 229# CCF1 . . . . . . . B ADDR 00D8H.1 A 230# CCF2 . . . . . . . B ADDR 00D8H.2 A 231# CCF3 . . . . . . . B ADDR 00D8H.3 A 232# CCF4 . . . . . . . B ADDR 00D8H.4 A 233# CF . . . . . . . . B ADDR 00D8H.7 A 235# CKCON. . . . . . . D ADDR 008EH A 50# CPRL2. . . . . . . B ADDR 00C8H.0 A 209# CPT0CN . . . . . . D ADDR 009EH A 65# CPT1CN . . . . . . D ADDR 009FH A 66# CR . . . . . . . . B ADDR 00D8H.6 A 234# CT2. . . . . . . . B ADDR 00C8H.1 A 210# CY . . . . . . . . B ADDR 00D0H.7 A 226# DAC0CN . . . . . . D ADDR 00D4H A 115# DAC0H. . . . . . . D ADDR 00D3H A 114# DAC0L. . . . . . . D ADDR 00D2H A 113# DAC1CN . . . . . . D ADDR 00D7H A 118# DAC1H. . . . . . . D ADDR 00D6H A 117# DAC1L. . . . . . . D ADDR 00D5H A 116# DPH. . . . . . . . D ADDR 0083H A 39# 303 319 336 352 DPL. . . . . . . . D ADDR 0082H A 38# 304 320 337 353 EA . . . . . . . . B ADDR 00A8H.7 A 189# EIE1 . . . . . . . D ADDR 00E6H A 132# EIE2 . . . . . . . D ADDR 00E7H A 133# EIP1 . . . . . . . D ADDR 00F6H A 148# EIP2 . . . . . . . D ADDR 00F7H A 149# EMI0CF . . . . . . D ADDR 00A3H A 69# 289 EMI0CN . . . . . . D ADDR 00AFH A 81# EMI0TC . . . . . . D ADDR 00A1H A 68# ENSMB. . . . . . . B ADDR 00C0H.6 A 206# A51 MACRO ASSEMBLER MEM_TEST 06/26/2003 11:09:26 PAGE 8 ERROR. . . . . . . C ADDR 0075H A 301 317 334 350 359# ES . . . . . . . . B ADDR 00A8H.4 A 187# ET0. . . . . . . . B ADDR 00A8H.1 A 184# ET1. . . . . . . . B ADDR 00A8H.3 A 186# ET2. . . . . . . . B ADDR 00A8H.5 A 188# EX0. . . . . . . . B ADDR 00A8H.0 A 183# EX1. . . . . . . . B ADDR 00A8H.2 A 185# EXEN2. . . . . . . B ADDR 00C8H.3 A 212# EXF2 . . . . . . . B ADDR 00C8H.6 A 215# F0 . . . . . . . . B ADDR 00D0H.5 A 224# F1 . . . . . . . . B ADDR 00D0H.1 A 220# FLACL. . . . . . . D ADDR 00B7H A 87# FLSCL. . . . . . . D ADDR 00B6H A 86# IE . . . . . . . . D ADDR 00A8H A 74# 183 184 185 186 187 188 189 IE0. . . . . . . . B ADDR 0088H.1 A 164# IE1. . . . . . . . B ADDR 0088H.3 A 166# IP . . . . . . . . D ADDR 00B8H A 88# 192 193 194 195 196 197 IT0. . . . . . . . B ADDR 0088H.0 A 163# IT1. . . . . . . . B ADDR 0088H.2 A 165# LOOP . . . . . . . C ADDR 001AH A 299# 307 LOOP1. . . . . . . C ADDR 0032H A 315# 323 LOOP2. . . . . . . C ADDR 004CH A 332# 340 LOOP3. . . . . . . C ADDR 0064H A 348# 356 MAIN . . . . . . . C ADDR 0003H A 273 279# MODF . . . . . . . B ADDR 00F8H.5 A 253# MSTEN. . . . . . . B ADDR 00F8H.1 A 249# OSCICN . . . . . . D ADDR 00B2H A 84# OSCXCN . . . . . . D ADDR 00B1H A 83# OV . . . . . . . . B ADDR 00D0H.2 A 221# P. . . . . . . . . B ADDR 00D0H.0 A 219# P0 . . . . . . . . D ADDR 0080H A 36# P0MDOUT. . . . . . D ADDR 00A4H A 70# P1 . . . . . . . . D ADDR 0090H A 52# P1MDIN . . . . . . D ADDR 00BDH A 93# P1MDOUT. . . . . . D ADDR 00A5H A 71# P2 . . . . . . . . D ADDR 00A0H A 67# P2MDOUT. . . . . . D ADDR 00A6H A 72# P3 . . . . . . . . D ADDR 00B0H A 82# P3IF . . . . . . . D ADDR 00ADH A 79# P3MDOUT. . . . . . D ADDR 00A7H A 73# P4 . . . . . . . . D ADDR 0084H A 40# 294 311 327 344 P5 . . . . . . . . D ADDR 0085H A 41# P6 . . . . . . . . D ADDR 0086H A 42# P7 . . . . . . . . D ADDR 0096H A 58# P74OUT . . . . . . D ADDR 00B5H A 85# PCA0CN . . . . . . D ADDR 00D8H A 119# 229 230 231 232 233 234 235 PCA0CPH0 . . . . . D ADDR 00FAH A 152# PCA0CPH1 . . . . . D ADDR 00FBH A 153# PCA0CPH2 . . . . . D ADDR 00FCH A 154# PCA0CPH3 . . . . . D ADDR 00FDH A 155# PCA0CPH4 . . . . . D ADDR 00FEH A 156# PCA0CPL0 . . . . . D ADDR 00EAH A 136# PCA0CPL1 . . . . . D ADDR 00EBH A 137# PCA0CPL2 . . . . . D ADDR 00ECH A 138# PCA0CPL3 . . . . . D ADDR 00EDH A 139# PCA0CPL4 . . . . . D ADDR 00EEH A 140# PCA0CPM0 . . . . . D ADDR 00DAH A 121# PCA0CPM1 . . . . . D ADDR 00DBH A 122# PCA0CPM2 . . . . . D ADDR 00DCH A 123# PCA0CPM3 . . . . . D ADDR 00DDH A 124# PCA0CPM4 . . . . . D ADDR 00DEH A 125# PCA0H. . . . . . . D ADDR 00F9H A 151# PCA0L. . . . . . . D ADDR 00E9H A 135# PCA0MD . . . . . . D ADDR 00D9H A 120# PCON . . . . . . . D ADDR 0087H A 43# PS . . . . . . . . B ADDR 00B8H.4 A 196# A51 MACRO ASSEMBLER MEM_TEST 06/26/2003 11:09:26 PAGE 9 PSCTL. . . . . . . D ADDR 008FH A 51# PSW. . . . . . . . D ADDR 00D0H A 111# 219 220 221 222 223 224 225 226 PT0. . . . . . . . B ADDR 00B8H.1 A 193# PT1. . . . . . . . B ADDR 00B8H.3 A 195# PT2. . . . . . . . B ADDR 00B8H.5 A 197# PX0. . . . . . . . B ADDR 00B8H.0 A 192# PX1. . . . . . . . B ADDR 00B8H.2 A 194# RB8. . . . . . . . B ADDR 0098H.2 A 175# RCAP2H . . . . . . D ADDR 00CBH A 107# RCAP2L . . . . . . D ADDR 00CAH A 106# RCAP4H . . . . . . D ADDR 00E5H A 131# RCAP4L . . . . . . D ADDR 00E4H A 130# RCLK . . . . . . . B ADDR 00C8H.5 A 214# REF0CN . . . . . . D ADDR 00D1H A 112# REN. . . . . . . . B ADDR 0098H.4 A 177# RI . . . . . . . . B ADDR 0098H.0 A 173# RS0. . . . . . . . B ADDR 00D0H.3 A 222# RS1. . . . . . . . B ADDR 00D0H.4 A 223# RSTSRC . . . . . . D ADDR 00EFH A 141# RXOVRN . . . . . . B ADDR 00F8H.4 A 252# SADDR0 . . . . . . D ADDR 00A9H A 75# SADDR1 . . . . . . D ADDR 00F3H A 145# SADEN0 . . . . . . D ADDR 00B9H A 89# SADEN1 . . . . . . D ADDR 00AEH A 80# SBUF0. . . . . . . D ADDR 0099H A 60# SBUF1. . . . . . . D ADDR 00F2H A 144# SCON0. . . . . . . D ADDR 0098H A 59# 173 174 175 176 177 178 179 180 SCON1. . . . . . . D ADDR 00F1H A 143# SI . . . . . . . . B ADDR 00C0H.3 A 203# SLVSEL . . . . . . B ADDR 00F8H.2 A 250# SM0. . . . . . . . B ADDR 0098H.7 A 180# SM1. . . . . . . . B ADDR 0098H.6 A 179# SM2. . . . . . . . B ADDR 0098H.5 A 178# SMB0ADR. . . . . . D ADDR 00C3H A 99# SMB0CN . . . . . . D ADDR 00C0H A 96# 200 201 202 203 204 205 206 SMB0CR . . . . . . D ADDR 00CFH A 110# SMB0DAT. . . . . . D ADDR 00C2H A 98# SMB0STA. . . . . . D ADDR 00C1H A 97# SMBFTE . . . . . . B ADDR 00C0H.1 A 201# SMBTOE . . . . . . B ADDR 00C0H.0 A 200# SP . . . . . . . . D ADDR 0081H A 37# SPI0CFG. . . . . . D ADDR 009AH A 61# SPI0CKR. . . . . . D ADDR 009DH A 64# SPI0CN . . . . . . D ADDR 00F8H A 150# 248 249 250 251 252 253 254 255 SPI0DAT. . . . . . D ADDR 009BH A 62# SPIEN. . . . . . . B ADDR 00F8H.0 A 248# SPIF . . . . . . . B ADDR 00F8H.7 A 255# STA. . . . . . . . B ADDR 00C0H.5 A 205# START. . . . . . . C ADDR 000FH A 292# 358 STO. . . . . . . . B ADDR 00C0H.4 A 204# T2CON. . . . . . . D ADDR 00C8H A 104# 209 210 211 212 213 214 215 216 T4CON. . . . . . . D ADDR 00C9H A 105# TB8. . . . . . . . B ADDR 0098H.3 A 176# TCLK . . . . . . . B ADDR 00C8H.4 A 213# TCON . . . . . . . D ADDR 0088H A 44# 163 164 165 166 167 168 169 170 TF0. . . . . . . . B ADDR 0088H.5 A 168# TF1. . . . . . . . B ADDR 0088H.7 A 170# TF2. . . . . . . . B ADDR 00C8H.7 A 216# TH0. . . . . . . . D ADDR 008CH A 48# TH1. . . . . . . . D ADDR 008DH A 49# TH2. . . . . . . . D ADDR 00CDH A 109# TH4. . . . . . . . D ADDR 00F5H A 147# TI . . . . . . . . B ADDR 0098H.1 A 174# TL0. . . . . . . . D ADDR 008AH A 46# TL1. . . . . . . . D ADDR 008BH A 47# TL2. . . . . . . . D ADDR 00CCH A 108# A51 MACRO ASSEMBLER MEM_TEST 06/26/2003 11:09:26 PAGE 10 TL4. . . . . . . . D ADDR 00F4H A 146# TMOD . . . . . . . D ADDR 0089H A 45# TMR3CN . . . . . . D ADDR 0091H A 53# TMR3H. . . . . . . D ADDR 0095H A 57# TMR3L. . . . . . . D ADDR 0094H A 56# TMR3RLH. . . . . . D ADDR 0093H A 55# TMR3RLL. . . . . . D ADDR 0092H A 54# TR0. . . . . . . . B ADDR 0088H.4 A 167# TR1. . . . . . . . B ADDR 0088H.6 A 169# TR2. . . . . . . . B ADDR 00C8H.2 A 211# TXBSY. . . . . . . B ADDR 00F8H.3 A 251# WCOL . . . . . . . B ADDR 00F8H.6 A 254# WDTCN. . . . . . . D ADDR 00FFH A 157# 284 285 XBR0 . . . . . . . D ADDR 00E1H A 127# XBR1 . . . . . . . D ADDR 00E2H A 128# XBR2 . . . . . . . D ADDR 00E3H A 129# 287 REGISTER BANK(S) USED: 0 ASSEMBLY COMPLETE. 0 WARNING(S), 0 ERROR(S)