A51 MACRO ASSEMBLER ADC2 10/20/2004 15:11:56 PAGE 1 MACRO ASSEMBLER A51 V6.14a OBJECT MODULE PLACED IN adc2.OBJ ASSEMBLER INVOKED BY: F:\Cygnal\IDEfiles\C51\BIN\a51.exe adc2.asm XR GEN DB EP NOMOD51 LOC OBJ LINE SOURCE 1 ;----------------------------------------------------------------------------- 2 ; 10/18/2004 sjd 3 ; 4 ; 5 ; 6 ; FILE NAME : ADC2.ASM 7 ; TARGET MCU : C8051F000 8 ; DESCRIPTION : This program illustrates how to configure the 9 ; : ADC2 and Crossbar, read t he ADC2 and write to the 10 ; : port 2&3 I/O pins. Defau lt values for ADC2. LED 11 ; : displays used as indicato rs. 12 ; 13 ; 14 ; NOTES: 15 ; 16 ; (1) This note intentionally left blank. 17 ; 18 ; 19 ;----------------------------------------------------------------------------- 20 21 22 ;----------------------------------------------------------------------------- 23 ; EQUATES 24 ;----------------------------------------------------------------------------- 25 26 ;$include (c8051f000.inc) ; Include register definition file. +1 27 ;----------------------------------------------------------------------------- +1 28 ; Copyright (C) 2001 CYGNAL INTEGRATED PRODUCTS, INC. +1 29 ; All rights reserved. +1 30 ; +1 31 ; +1 32 ; FILE NAME : C8051F000.INC +1 33 ; TARGET MCUs : C8051F000, 'F001, 'F002, 'F010, 'F011, 'F012, 'F005, 'F006, +1 34 ; 'F007, 'F015, 'F016 and 'F017 +1 35 ; DESCRIPTION : Register/bit definitions for the C8051F0xx product family. +1 36 ; +1 37 ; REVISION 1.9 +1 38 ; +1 39 ;----------------------------------------------------------------------------- +1 40 ;REGISTER DEFINITIONS +1 41 ; 0080 +1 42 P0 DATA 080H ; PORT 0 0081 +1 43 SP DATA 081H ; STACK POINTER 0082 +1 44 DPL DATA 082H ; DATA POINTER - LOW BYTE 0083 +1 45 DPH DATA 083H ; DATA POINTER - HIGH BYTE 0087 +1 46 PCON DATA 087H ; POWER CONTROL 0088 +1 47 TCON DATA 088H ; TIMER CONTROL 0089 +1 48 TMOD DATA 089H ; TIMER MODE 008A +1 49 TL0 DATA 08AH ; TIMER 0 - LOW BYTE 008B +1 50 TL1 DATA 08BH ; TIMER 1 - LOW BYTE 008C +1 51 TH0 DATA 08CH ; TIMER 0 - HIGH BYTE 008D +1 52 TH1 DATA 08DH ; TIMER 1 - HIGH BYTE 008E +1 53 CKCON DATA 08EH ; CLOCK CONTROL 008F +1 54 PSCTL DATA 08FH ; PROGRAM STORE R/W CONTROL 0090 +1 55 P1 DATA 090H ; PORT 1 A51 MACRO ASSEMBLER ADC2 10/20/2004 15:11:56 PAGE 2 0091 +1 56 TMR3CN DATA 091H ; TIMER 3 CONTROL 0092 +1 57 TMR3RLL DATA 092H ; TIMER 3 RELOAD REGISTER - LOW BYTE 0093 +1 58 TMR3RLH DATA 093H ; TIMER 3 RELOAD REGISTER - HIGH BYTE 0094 +1 59 TMR3L DATA 094H ; TIMER 3 - LOW BYTE 0095 +1 60 TMR3H DATA 095H ; TIMER 3 - HIGH BYTE 0098 +1 61 SCON DATA 098H ; SERIAL PORT CONTROL 0099 +1 62 SBUF DATA 099H ; SERIAL PORT BUFFER 009A +1 63 SPI0CFG DATA 09AH ; SERIAL PERIPHERAL INTERFACE 0 CONFIGURATION 009B +1 64 SPI0DAT DATA 09BH ; SERIAL PERIPHERAL INTERFACE 0 DATA 009D +1 65 SPI0CKR DATA 09DH ; SERIAL PERIPHERAL INTERFACE 0 CLOCK RATE CONTROL 009E +1 66 CPT0CN DATA 09EH ; COMPARATOR 0 CONTROL 009F +1 67 CPT1CN DATA 09FH ; COMPARATOR 1 CONTROL 00A0 +1 68 P2 DATA 0A0H ; PORT 2 00A4 +1 69 PRT0CF DATA 0A4H ; PORT 0 CONFIGURATION 00A5 +1 70 PRT1CF DATA 0A5H ; PORT 1 CONFIGURATION 00A6 +1 71 PRT2CF DATA 0A6H ; PORT 2 CONFIGURATION 00A7 +1 72 PRT3CF DATA 0A7H ; PORT 3 CONFIGURATION 00A8 +1 73 IE DATA 0A8H ; INTERRUPT ENABLE 00AD +1 74 PRT1IF DATA 0ADH ; PORT 1 EXTERNAL INTERRUPT FLAGS 00AF +1 75 EMI0CN DATA 0AFH ; EXTERNAL MEMORY INTERFACE CONTROL 00B0 +1 76 P3 DATA 0B0H ; PORT 3 00B1 +1 77 OSCXCN DATA 0B1H ; EXTERNAL OSCILLATOR CONTROL 00B2 +1 78 OSCICN DATA 0B2H ; INTERNAL OSCILLATOR CONTROL 00B6 +1 79 FLSCL DATA 0B6H ; FLASH MEMORY TIMING PRESCALER 00B7 +1 80 FLACL DATA 0B7H ; FLASH ACESS LIMIT 00B8 +1 81 IP DATA 0B8H ; INTERRUPT PRIORITY 00BA +1 82 AMX0CF DATA 0BAH ; ADC 0 MUX CONFIGURATION 00BB +1 83 AMX0SL DATA 0BBH ; ADC 0 MUX CHANNEL SELECTION 00BC +1 84 ADC0CF DATA 0BCH ; ADC 0 CONFIGURATION 00BE +1 85 ADC0L DATA 0BEH ; ADC 0 DATA - LOW BYTE 00BF +1 86 ADC0H DATA 0BFH ; ADC 0 DATA - HIGH BYTE 00C0 +1 87 SMB0CN DATA 0C0H ; SMBUS 0 CONTROL 00C1 +1 88 SMB0STA DATA 0C1H ; SMBUS 0 STATUS 00C2 +1 89 SMB0DAT DATA 0C2H ; SMBUS 0 DATA 00C3 +1 90 SMB0ADR DATA 0C3H ; SMBUS 0 SLAVE ADDRESS 00C4 +1 91 ADC0GTL DATA 0C4H ; ADC 0 GREATER-THAN REGISTER - LOW BYTE 00C5 +1 92 ADC0GTH DATA 0C5H ; ADC 0 GREATER-THAN REGISTER - HIGH BYTE 00C6 +1 93 ADC0LTL DATA 0C6H ; ADC 0 LESS-THAN REGISTER - LOW BYTE 00C7 +1 94 ADC0LTH DATA 0C7H ; ADC 0 LESS-THAN REGISTER - HIGH BYTE 00C8 +1 95 T2CON DATA 0C8H ; TIMER 2 CONTROL 00CA +1 96 RCAP2L DATA 0CAH ; TIMER 2 CAPTURE REGISTER - LOW BYTE 00CB +1 97 RCAP2H DATA 0CBH ; TIMER 2 CAPTURE REGISTER - HIGH BYTE 00CC +1 98 TL2 DATA 0CCH ; TIMER 2 - LOW BYTE 00CD +1 99 TH2 DATA 0CDH ; TIMER 2 - HIGH BYTE 00CF +1 100 SMB0CR DATA 0CFH ; SMBUS 0 CLOCK RATE 00D0 +1 101 PSW DATA 0D0H ; PROGRAM STATUS WORD 00D1 +1 102 REF0CN DATA 0D1H ; VOLTAGE REFERENCE 0 CONTROL 00D2 +1 103 DAC0L DATA 0D2H ; DAC 0 REGISTER - LOW BYTE 00D3 +1 104 DAC0H DATA 0D3H ; DAC 0 REGISTER - HIGH BYTE 00D4 +1 105 DAC0CN DATA 0D4H ; DAC 0 CONTROL 00D5 +1 106 DAC1L DATA 0D5H ; DAC 1 REGISTER - LOW BYTE 00D6 +1 107 DAC1H DATA 0D6H ; DAC 1 REGISTER - HIGH BYTE 00D7 +1 108 DAC1CN DATA 0D7H ; DAC 1 CONTROL 00D8 +1 109 PCA0CN DATA 0D8H ; PCA 0 COUNTER CONTROL 00D9 +1 110 PCA0MD DATA 0D9H ; PCA 0 COUNTER MODE 00DA +1 111 PCA0CPM0 DATA 0DAH ; CONTROL REGISTER FOR PCA 0 MODULE 0 00DB +1 112 PCA0CPM1 DATA 0DBH ; CONTROL REGISTER FOR PCA 0 MODULE 1 00DC +1 113 PCA0CPM2 DATA 0DCH ; CONTROL REGISTER FOR PCA 0 MODULE 2 00DD +1 114 PCA0CPM3 DATA 0DDH ; CONTROL REGISTER FOR PCA 0 MODULE 3 00DE +1 115 PCA0CPM4 DATA 0DEH ; CONTROL REGISTER FOR PCA 0 MODULE 4 00E0 +1 116 ACC DATA 0E0H ; ACCUMULATOR 00E1 +1 117 XBR0 DATA 0E1H ; DIGITAL CROSSBAR CONFIGURATION REGISTER 0 00E2 +1 118 XBR1 DATA 0E2H ; DIGITAL CROSSBAR CONFIGURATION REGISTER 1 00E3 +1 119 XBR2 DATA 0E3H ; DIGITAL CROSSBAR CONFIGURATION REGISTER 2 00E6 +1 120 EIE1 DATA 0E6H ; EXTERNAL INTERRUPT ENABLE 1 00E7 +1 121 EIE2 DATA 0E7H ; EXTERNAL INTERRUPT ENABLE 2 A51 MACRO ASSEMBLER ADC2 10/20/2004 15:11:56 PAGE 3 00E8 +1 122 ADC0CN DATA 0E8H ; ADC 0 CONTROL 00E9 +1 123 PCA0L DATA 0E9H ; PCA 0 TIMER - LOW BYTE 00EA +1 124 PCA0CPL0 DATA 0EAH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - LOW BYTE 00EB +1 125 PCA0CPL1 DATA 0EBH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - LOW BYTE 00EC +1 126 PCA0CPL2 DATA 0ECH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - LOW BYTE 00ED +1 127 PCA0CPL3 DATA 0EDH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - LOW BYTE 00EE +1 128 PCA0CPL4 DATA 0EEH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - LOW BYTE 00EF +1 129 RSTSRC DATA 0EFH ; RESET SOURCE 00F0 +1 130 B DATA 0F0H ; B REGISTER 00F6 +1 131 EIP1 DATA 0F6H ; EXTERNAL INTERRUPT PRIORITY REGISTER 1 00F7 +1 132 EIP2 DATA 0F7H ; EXTERNAL INTERRUPT PRIORITY REGISTER 2 00F8 +1 133 SPI0CN DATA 0F8H ; SERIAL PERIPHERAL INTERFACE 0 CONTROL 00F9 +1 134 PCA0H DATA 0F9H ; PCA 0 TIMER - HIGH BYTE 00FA +1 135 PCA0CPH0 DATA 0FAH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - HIGH BYTE 00FB +1 136 PCA0CPH1 DATA 0FBH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - HIGH BYTE 00FC +1 137 PCA0CPH2 DATA 0FCH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - HIGH BYTE 00FD +1 138 PCA0CPH3 DATA 0FDH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - HIGH BYTE 00FE +1 139 PCA0CPH4 DATA 0FEH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - HIGH BYTE 00FF +1 140 WDTCN DATA 0FFH ; WATCHDOG TIMER CONTROL +1 141 ; +1 142 ;------------------------------------------------------------------------------ +1 143 ;BIT DEFINITIONS +1 144 ; +1 145 ; TCON 88H 0088 +1 146 IT0 BIT TCON.0 ; EXT. INTERRUPT 0 TYPE 0089 +1 147 IE0 BIT TCON.1 ; EXT. INTERRUPT 0 EDGE FLAG 008A +1 148 IT1 BIT TCON.2 ; EXT. INTERRUPT 1 TYPE 008B +1 149 IE1 BIT TCON.3 ; EXT. INTERRUPT 1 EDGE FLAG 008C +1 150 TR0 BIT TCON.4 ; TIMER 0 ON/OFF CONTROL 008D +1 151 TF0 BIT TCON.5 ; TIMER 0 OVERFLOW FLAG 008E +1 152 TR1 BIT TCON.6 ; TIMER 1 ON/OFF CONTROL 008F +1 153 TF1 BIT TCON.7 ; TIMER 1 OVERFLOW FLAG +1 154 ; +1 155 ; SCON 98H 0098 +1 156 RI BIT SCON.0 ; RECEIVE INTERRUPT FLAG 0099 +1 157 TI BIT SCON.1 ; TRANSMIT INTERRUPT FLAG 009A +1 158 RB8 BIT SCON.2 ; RECEIVE BIT 8 009B +1 159 TB8 BIT SCON.3 ; TRANSMIT BIT 8 009C +1 160 REN BIT SCON.4 ; RECEIVE ENABLE 009D +1 161 SM2 BIT SCON.5 ; MULTIPROCESSOR COMMUNICATION ENABLE 009E +1 162 SM1 BIT SCON.6 ; SERIAL MODE CONTROL BIT 1 009F +1 163 SM0 BIT SCON.7 ; SERIAL MODE CONTROL BIT 0 +1 164 ; +1 165 ; IE A8H 00A8 +1 166 EX0 BIT IE.0 ; EXTERNAL INTERRUPT 0 ENABLE 00A9 +1 167 ET0 BIT IE.1 ; TIMER 0 INTERRUPT ENABLE 00AA +1 168 EX1 BIT IE.2 ; EXTERNAL INTERRUPT 1 ENABLE 00AB +1 169 ET1 BIT IE.3 ; TIMER 1 INTERRUPT ENABLE 00AC +1 170 ES BIT IE.4 ; SERIAL PORT INTERRUPT ENABLE 00AD +1 171 ET2 BIT IE.5 ; TIMER 2 INTERRUPT ENABLE 00AF +1 172 EA BIT IE.7 ; GLOBAL INTERRUPT ENABLE +1 173 ; +1 174 ; IP B8H 00B8 +1 175 PX0 BIT IP.0 ; EXTERNAL INTERRUPT 0 PRIORITY 00B9 +1 176 PT0 BIT IP.1 ; TIMER 0 PRIORITY 00BA +1 177 PX1 BIT IP.2 ; EXTERNAL INTERRUPT 1 PRIORITY 00BB +1 178 PT1 BIT IP.3 ; TIMER 1 PRIORITY 00BC +1 179 PS BIT IP.4 ; SERIAL PORT PRIORITY 00BD +1 180 PT2 BIT IP.5 ; TIMER 2 PRIORITY +1 181 ; +1 182 ; SMB0CN C0H 00C0 +1 183 SMBTOE BIT SMB0CN.0 ; SMBUS 0 TIMEOUT ENABLE 00C1 +1 184 SMBFTE BIT SMB0CN.1 ; SMBUS 0 FREE TIMER ENABLE 00C2 +1 185 AA BIT SMB0CN.2 ; SMBUS 0 ASSERT/ACKNOWLEDGE FLAG 00C3 +1 186 SI BIT SMB0CN.3 ; SMBUS 0 INTERRUPT PENDING FLAG 00C4 +1 187 STO BIT SMB0CN.4 ; SMBUS 0 STOP FLAG A51 MACRO ASSEMBLER ADC2 10/20/2004 15:11:56 PAGE 4 00C5 +1 188 STA BIT SMB0CN.5 ; SMBUS 0 START FLAG 00C6 +1 189 ENSMB BIT SMB0CN.6 ; SMBUS 0 ENABLE +1 190 ; +1 191 ; T2CON C8H 00C8 +1 192 CPRL2 BIT T2CON.0 ; CAPTURE OR RELOAD SELECT 00C9 +1 193 CT2 BIT T2CON.1 ; TIMER OR COUNTER SELECT 00CA +1 194 TR2 BIT T2CON.2 ; TIMER 2 ON/OFF CONTROL 00CB +1 195 EXEN2 BIT T2CON.3 ; TIMER 2 EXTERNAL ENABLE FLAG 00CC +1 196 TCLK BIT T2CON.4 ; TRANSMIT CLOCK FLAG 00CD +1 197 RCLK BIT T2CON.5 ; RECEIVE CLOCK FLAG 00CE +1 198 EXF2 BIT T2CON.6 ; EXTERNAL FLAG 00CF +1 199 TF2 BIT T2CON.7 ; TIMER 2 OVERFLOW FLAG +1 200 ; +1 201 ; PSW D0H 00D0 +1 202 P BIT PSW.0 ; ACCUMULATOR PARITY FLAG 00D1 +1 203 F1 BIT PSW.1 ; USER FLAG 1 00D2 +1 204 OV BIT PSW.2 ; OVERFLOW FLAG 00D3 +1 205 RS0 BIT PSW.3 ; REGISTER BANK SELECT 0 00D4 +1 206 RS1 BIT PSW.4 ; REGISTER BANK SELECT 1 00D5 +1 207 F0 BIT PSW.5 ; USER FLAG 0 00D6 +1 208 AC BIT PSW.6 ; AUXILIARY CARRY FLAG 00D7 +1 209 CY BIT PSW.7 ; CARRY FLAG +1 210 ; +1 211 ; PCA0CN D8H 00D8 +1 212 CCF0 BIT PCA0CN.0 ; PCA 0 MODULE 0 INTERRUPT FLAG 00D9 +1 213 CCF1 BIT PCA0CN.1 ; PCA 0 MODULE 1 INTERRUPT FLAG 00DA +1 214 CCF2 BIT PCA0CN.2 ; PCA 0 MODULE 2 INTERRUPT FLAG 00DB +1 215 CCF3 BIT PCA0CN.3 ; PCA 0 MODULE 3 INTERRUPT FLAG 00DC +1 216 CCF4 BIT PCA0CN.4 ; PCA 0 MODULE 4 INTERRUPT FLAG 00DE +1 217 CR BIT PCA0CN.6 ; PCA 0 COUNTER RUN CONTROL BIT 00DF +1 218 CF BIT PCA0CN.7 ; PCA 0 COUNTER OVERFLOW FLAG +1 219 ; +1 220 ; ADC0CN E8H 00E8 +1 221 ADLJST BIT ADC0CN.0 ; ADC 0 RIGHT JUSTIFY DATA BIT 00E9 +1 222 ADWINT BIT ADC0CN.1 ; ADC 0 WINDOW COMPARE INTERRUPT FLAG 00EA +1 223 ADSTM0 BIT ADC0CN.2 ; ADC 0 START OF CONVERSION MODE BIT 0 00EB +1 224 ADSTM1 BIT ADC0CN.3 ; ADC 0 START OF CONVERSION MODE BIT 1 00EC +1 225 ADBUSY BIT ADC0CN.4 ; ADC 0 BUSY FLAG 00ED +1 226 ADCINT BIT ADC0CN.5 ; ADC 0 CONVERISION COMPLETE INTERRUPT FLAG 00EE +1 227 ADCTM BIT ADC0CN.6 ; ADC 0 TRACK MODE 00EF +1 228 ADCEN BIT ADC0CN.7 ; ADC 0 ENABLE +1 229 ; +1 230 ; SPI0CN F8H 00F8 +1 231 SPIEN BIT SPI0CN.0 ; SPI 0 SPI ENABLE 00F9 +1 232 MSTEN BIT SPI0CN.1 ; SPI 0 MASTER ENABLE 00FA +1 233 SLVSEL BIT SPI0CN.2 ; SPI 0 SLAVE SELECT 00FB +1 234 TXBSY BIT SPI0CN.3 ; SPI 0 TX BUSY FLAG 00FC +1 235 RXOVRN BIT SPI0CN.4 ; SPI 0 RX OVERRUN FLAG 00FD +1 236 MODF BIT SPI0CN.5 ; SPI 0 MODE FAULT FLAG 00FE +1 237 WCOL BIT SPI0CN.6 ; SPI 0 WRITE COLLISION FLAG 00FF +1 238 SPIF BIT SPI0CN.7 ; SPI 0 INTERRUPT FLAG 239 240 241 ;----------------------------------------------------------------------------- 242 ; VARIABLES 243 ;----------------------------------------------------------------------------- 244 245 ;----------------------------------------------------------------------------- 246 ; RESET and INTERRUPT VECTORS 247 ;----------------------------------------------------------------------------- 248 249 250 ; Reset Vector ---- 251 cseg AT 0 0000 020000 F 252 ljmp Main ; Locate a jump to the start of code at 253 ; the reset vector. A51 MACRO ASSEMBLER ADC2 10/20/2004 15:11:56 PAGE 5 254 255 ;----------------------------------------------------------------------------- 256 ; CODE SEGMENT 257 ;----------------------------------------------------------------------------- 258 259 Code_Seg segment CODE 260 ---- 261 rseg Code_Seg ; Switch to this code segment. 262 using 0 ; Specify register bank for the following 263 ; program code. 264 265 ; Enable Vref - required before using adc 0000 75D103 266 Main: mov REF0CN, #00000011b ; bias on, int vref. 267 0003 7800 268 mov R0, #0 ;clear R0 0005 7900 269 mov R1, #0 ;clear R1 270 ; 271 ; Enable the Port I/O Crossbar 0007 75E340 272 mov XBR2, #40h 273 ;P2,P3 set for output to LED displays. 000A 88A0 274 mov P2, R0 000C 89B0 275 mov P3, R1 276 ;loop. 000E 75BB02 277 mov AMX0SL, #00000010b ; select ad c1 0011 75E890 278 Loop: mov ADC0CN, #10010000b 0014 A8BF 279 mov R0, ADC0H 0016 A9BE 280 mov R1, ADC0L 0018 88A0 281 mov P2, R0 ;write ADC0H value to port2 001A 89B0 282 mov P3, R1 ;write ADC0L value to port3 001C 80F3 283 jmp Loop 284 285 286 ;----------------------------------------------------------------------------- 287 ; End of file. 288 289 END A51 MACRO ASSEMBLER ADC2 10/20/2004 15:11:56 PAGE 6 XREF SYMBOL TABLE LISTING ---- ------ ----- ------- N A M E T Y P E V A L U E ATTRIBUTES / REFERENCES AA . . . . . . . . B ADDR 00C0H.2 A 185# AC . . . . . . . . B ADDR 00D0H.6 A 208# ACC. . . . . . . . D ADDR 00E0H A 116# ADBUSY . . . . . . B ADDR 00E8H.4 A 225# ADC0CF . . . . . . D ADDR 00BCH A 84# ADC0CN . . . . . . D ADDR 00E8H A 122# 221 222 223 224 225 226 227 228 278 ADC0GTH. . . . . . D ADDR 00C5H A 92# ADC0GTL. . . . . . D ADDR 00C4H A 91# ADC0H. . . . . . . D ADDR 00BFH A 86# 279 ADC0L. . . . . . . D ADDR 00BEH A 85# 280 ADC0LTH. . . . . . D ADDR 00C7H A 94# ADC0LTL. . . . . . D ADDR 00C6H A 93# ADCEN. . . . . . . B ADDR 00E8H.7 A 228# ADCINT . . . . . . B ADDR 00E8H.5 A 226# ADCTM. . . . . . . B ADDR 00E8H.6 A 227# ADLJST . . . . . . B ADDR 00E8H.0 A 221# ADSTM0 . . . . . . B ADDR 00E8H.2 A 223# ADSTM1 . . . . . . B ADDR 00E8H.3 A 224# ADWINT . . . . . . B ADDR 00E8H.1 A 222# AMX0CF . . . . . . D ADDR 00BAH A 82# AMX0SL . . . . . . D ADDR 00BBH A 83# 277 B. . . . . . . . . D ADDR 00F0H A 130# CCF0 . . . . . . . B ADDR 00D8H.0 A 212# CCF1 . . . . . . . B ADDR 00D8H.1 A 213# CCF2 . . . . . . . B ADDR 00D8H.2 A 214# CCF3 . . . . . . . B ADDR 00D8H.3 A 215# CCF4 . . . . . . . B ADDR 00D8H.4 A 216# CF . . . . . . . . B ADDR 00D8H.7 A 218# CKCON. . . . . . . D ADDR 008EH A 53# CODE_SEG . . . . . C SEG 001EH REL=UNIT 259# 261 CPRL2. . . . . . . B ADDR 00C8H.0 A 192# CPT0CN . . . . . . D ADDR 009EH A 66# CPT1CN . . . . . . D ADDR 009FH A 67# CR . . . . . . . . B ADDR 00D8H.6 A 217# CT2. . . . . . . . B ADDR 00C8H.1 A 193# CY . . . . . . . . B ADDR 00D0H.7 A 209# DAC0CN . . . . . . D ADDR 00D4H A 105# DAC0H. . . . . . . D ADDR 00D3H A 104# DAC0L. . . . . . . D ADDR 00D2H A 103# DAC1CN . . . . . . D ADDR 00D7H A 108# DAC1H. . . . . . . D ADDR 00D6H A 107# DAC1L. . . . . . . D ADDR 00D5H A 106# DPH. . . . . . . . D ADDR 0083H A 45# DPL. . . . . . . . D ADDR 0082H A 44# EA . . . . . . . . B ADDR 00A8H.7 A 172# EIE1 . . . . . . . D ADDR 00E6H A 120# EIE2 . . . . . . . D ADDR 00E7H A 121# EIP1 . . . . . . . D ADDR 00F6H A 131# EIP2 . . . . . . . D ADDR 00F7H A 132# EMI0CN . . . . . . D ADDR 00AFH A 75# ENSMB. . . . . . . B ADDR 00C0H.6 A 189# ES . . . . . . . . B ADDR 00A8H.4 A 170# ET0. . . . . . . . B ADDR 00A8H.1 A 167# ET1. . . . . . . . B ADDR 00A8H.3 A 169# ET2. . . . . . . . B ADDR 00A8H.5 A 171# EX0. . . . . . . . B ADDR 00A8H.0 A 166# EX1. . . . . . . . B ADDR 00A8H.2 A 168# EXEN2. . . . . . . B ADDR 00C8H.3 A 195# EXF2 . . . . . . . B ADDR 00C8H.6 A 198# F0 . . . . . . . . B ADDR 00D0H.5 A 207# A51 MACRO ASSEMBLER ADC2 10/20/2004 15:11:56 PAGE 7 F1 . . . . . . . . B ADDR 00D0H.1 A 203# FLACL. . . . . . . D ADDR 00B7H A 80# FLSCL. . . . . . . D ADDR 00B6H A 79# IE . . . . . . . . D ADDR 00A8H A 73# 166 167 168 169 170 171 172 IE0. . . . . . . . B ADDR 0088H.1 A 147# IE1. . . . . . . . B ADDR 0088H.3 A 149# IP . . . . . . . . D ADDR 00B8H A 81# 175 176 177 178 179 180 IT0. . . . . . . . B ADDR 0088H.0 A 146# IT1. . . . . . . . B ADDR 0088H.2 A 148# LOOP . . . . . . . C ADDR 0011H R SEG=CODE_SEG 278# 283 MAIN . . . . . . . C ADDR 0000H R SEG=CODE_SEG 252 266# MODF . . . . . . . B ADDR 00F8H.5 A 236# MSTEN. . . . . . . B ADDR 00F8H.1 A 232# OSCICN . . . . . . D ADDR 00B2H A 78# OSCXCN . . . . . . D ADDR 00B1H A 77# OV . . . . . . . . B ADDR 00D0H.2 A 204# P. . . . . . . . . B ADDR 00D0H.0 A 202# P0 . . . . . . . . D ADDR 0080H A 42# P1 . . . . . . . . D ADDR 0090H A 55# P2 . . . . . . . . D ADDR 00A0H A 68# 274 281 P3 . . . . . . . . D ADDR 00B0H A 76# 275 282 PCA0CN . . . . . . D ADDR 00D8H A 109# 212 213 214 215 216 217 218 PCA0CPH0 . . . . . D ADDR 00FAH A 135# PCA0CPH1 . . . . . D ADDR 00FBH A 136# PCA0CPH2 . . . . . D ADDR 00FCH A 137# PCA0CPH3 . . . . . D ADDR 00FDH A 138# PCA0CPH4 . . . . . D ADDR 00FEH A 139# PCA0CPL0 . . . . . D ADDR 00EAH A 124# PCA0CPL1 . . . . . D ADDR 00EBH A 125# PCA0CPL2 . . . . . D ADDR 00ECH A 126# PCA0CPL3 . . . . . D ADDR 00EDH A 127# PCA0CPL4 . . . . . D ADDR 00EEH A 128# PCA0CPM0 . . . . . D ADDR 00DAH A 111# PCA0CPM1 . . . . . D ADDR 00DBH A 112# PCA0CPM2 . . . . . D ADDR 00DCH A 113# PCA0CPM3 . . . . . D ADDR 00DDH A 114# PCA0CPM4 . . . . . D ADDR 00DEH A 115# PCA0H. . . . . . . D ADDR 00F9H A 134# PCA0L. . . . . . . D ADDR 00E9H A 123# PCA0MD . . . . . . D ADDR 00D9H A 110# PCON . . . . . . . D ADDR 0087H A 46# PRT0CF . . . . . . D ADDR 00A4H A 69# PRT1CF . . . . . . D ADDR 00A5H A 70# PRT1IF . . . . . . D ADDR 00ADH A 74# PRT2CF . . . . . . D ADDR 00A6H A 71# PRT3CF . . . . . . D ADDR 00A7H A 72# PS . . . . . . . . B ADDR 00B8H.4 A 179# PSCTL. . . . . . . D ADDR 008FH A 54# PSW. . . . . . . . D ADDR 00D0H A 101# 202 203 204 205 206 207 208 209 PT0. . . . . . . . B ADDR 00B8H.1 A 176# PT1. . . . . . . . B ADDR 00B8H.3 A 178# PT2. . . . . . . . B ADDR 00B8H.5 A 180# PX0. . . . . . . . B ADDR 00B8H.0 A 175# PX1. . . . . . . . B ADDR 00B8H.2 A 177# RB8. . . . . . . . B ADDR 0098H.2 A 158# RCAP2H . . . . . . D ADDR 00CBH A 97# RCAP2L . . . . . . D ADDR 00CAH A 96# RCLK . . . . . . . B ADDR 00C8H.5 A 197# REF0CN . . . . . . D ADDR 00D1H A 102# 266 REN. . . . . . . . B ADDR 0098H.4 A 160# RI . . . . . . . . B ADDR 0098H.0 A 156# RS0. . . . . . . . B ADDR 00D0H.3 A 205# RS1. . . . . . . . B ADDR 00D0H.4 A 206# RSTSRC . . . . . . D ADDR 00EFH A 129# RXOVRN . . . . . . B ADDR 00F8H.4 A 235# SBUF . . . . . . . D ADDR 0099H A 62# A51 MACRO ASSEMBLER ADC2 10/20/2004 15:11:56 PAGE 8 SCON . . . . . . . D ADDR 0098H A 61# 156 157 158 159 160 161 162 163 SI . . . . . . . . B ADDR 00C0H.3 A 186# SLVSEL . . . . . . B ADDR 00F8H.2 A 233# SM0. . . . . . . . B ADDR 0098H.7 A 163# SM1. . . . . . . . B ADDR 0098H.6 A 162# SM2. . . . . . . . B ADDR 0098H.5 A 161# SMB0ADR. . . . . . D ADDR 00C3H A 90# SMB0CN . . . . . . D ADDR 00C0H A 87# 183 184 185 186 187 188 189 SMB0CR . . . . . . D ADDR 00CFH A 100# SMB0DAT. . . . . . D ADDR 00C2H A 89# SMB0STA. . . . . . D ADDR 00C1H A 88# SMBFTE . . . . . . B ADDR 00C0H.1 A 184# SMBTOE . . . . . . B ADDR 00C0H.0 A 183# SP . . . . . . . . D ADDR 0081H A 43# SPI0CFG. . . . . . D ADDR 009AH A 63# SPI0CKR. . . . . . D ADDR 009DH A 65# SPI0CN . . . . . . D ADDR 00F8H A 133# 231 232 233 234 235 236 237 238 SPI0DAT. . . . . . D ADDR 009BH A 64# SPIEN. . . . . . . B ADDR 00F8H.0 A 231# SPIF . . . . . . . B ADDR 00F8H.7 A 238# STA. . . . . . . . B ADDR 00C0H.5 A 188# STO. . . . . . . . B ADDR 00C0H.4 A 187# T2CON. . . . . . . D ADDR 00C8H A 95# 192 193 194 195 196 197 198 199 TB8. . . . . . . . B ADDR 0098H.3 A 159# TCLK . . . . . . . B ADDR 00C8H.4 A 196# TCON . . . . . . . D ADDR 0088H A 47# 146 147 148 149 150 151 152 153 TF0. . . . . . . . B ADDR 0088H.5 A 151# TF1. . . . . . . . B ADDR 0088H.7 A 153# TF2. . . . . . . . B ADDR 00C8H.7 A 199# TH0. . . . . . . . D ADDR 008CH A 51# TH1. . . . . . . . D ADDR 008DH A 52# TH2. . . . . . . . D ADDR 00CDH A 99# TI . . . . . . . . B ADDR 0098H.1 A 157# TL0. . . . . . . . D ADDR 008AH A 49# TL1. . . . . . . . D ADDR 008BH A 50# TL2. . . . . . . . D ADDR 00CCH A 98# TMOD . . . . . . . D ADDR 0089H A 48# TMR3CN . . . . . . D ADDR 0091H A 56# TMR3H. . . . . . . D ADDR 0095H A 60# TMR3L. . . . . . . D ADDR 0094H A 59# TMR3RLH. . . . . . D ADDR 0093H A 58# TMR3RLL. . . . . . D ADDR 0092H A 57# TR0. . . . . . . . B ADDR 0088H.4 A 150# TR1. . . . . . . . B ADDR 0088H.6 A 152# TR2. . . . . . . . B ADDR 00C8H.2 A 194# TXBSY. . . . . . . B ADDR 00F8H.3 A 234# WCOL . . . . . . . B ADDR 00F8H.6 A 237# WDTCN. . . . . . . D ADDR 00FFH A 140# XBR0 . . . . . . . D ADDR 00E1H A 117# XBR1 . . . . . . . D ADDR 00E2H A 118# XBR2 . . . . . . . D ADDR 00E3H A 119# 272 REGISTER BANK(S) USED: 0 ASSEMBLY COMPLETE. 0 WARNING(S), 0 ERROR(S)