;----------------------------------------------------------------------------- ; ; FILE NAME : RAM_TEST.ASM ; TARGET MCU : C8051F020 ; DESCRIPTION : This program disables the watchdog timer and writes value in ; acc A to address pointed to by DPTR in external SRAM on ; plug-in board AB1. ; ; NOTES: ; (1) /WE = P4.7 (/WR) ; (2) /CE = P4.4 (J1 closed on AB1 board) ; (3) /OE = P4.6 (/RD) ; (4) D0-D7 = P7.0-P7.7 (DATA bus) ; (5) A0-A7 = P6.0-P6.7 (ADR bus lo byte) ; (6) A8-A15 = P5.0-P5.7 (ADR bus hi byte) ; (7) A16 = P4.5 (BANK select) ; ; ;----------------------------------------------------------------------------- $include (c8051F020.inc) ; Include register definition file ;----------------------------------------------------------------------------- ; EQUATES ;----------------------------------------------------------------------------- ;----------------------------------------------------------------------------- ; VARIABLES ;----------------------------------------------------------------------------- ;----------------------------------------------------------------------------- ; RESET and INTERRUPT VECTORS ;----------------------------------------------------------------------------- ; Reset Vector org 00h ljmp Main ;----------------------------------------------------------------------------- ; CODE SEGMENT ;----------------------------------------------------------------------------- Main: ; Disable the WDT. (IRQs not enabled at this point.) ; If interrupts were enabled, we would need to explicitly ; disable them so that the 2nd move to WDTCN occurs no more ; than four clock cycles after the first move to WDTCN. mov WDTCN, #0DEh mov WDTCN, #0ADh ; set up the XBAR mov XBR2, #42h ;weak pull-ups, XBAR enabled, ;non-multiplexed mode mov EMI0CF, #3Fh ;EMIF active on P4-P7, EMIF in non-multi- ;plexed mode, external XRAM only mov A, #0EFh ;clr P4.4 for /CE, P4.5 hi for upper 64k of ;external 128k SRAM mov P4, A ;enable external /CE & upper 64K SRAM mov A, #0AAh ;load $AA in acc A mov DPTR, #0AAAAh ;load DPTR with 16 bit addr $1AAAA movx @DPTR, A ;load contents of $1AAAA with acc A mov A, #00 ;load $00 in acc A to clear A movx A, @DPTR ;read $1AAAA mov A, #0CFh ;clr P4.4 for /CE, P4.5 lo for lower 64k of ;external 128k SRAM mov P4, A ;enable external /CE & lower 64k SRAM mov A, #055h ;load $55 in acc A mov DPTR, #5555h ;load DPTR with 16 bit addr $05555 movx @DPTR, A ;load contents of $05555 with acc A mov A, #00 ;load $00 in acc A to clear A movx A, @DPTR ;read $05555 Loop: clr A mov P4, #0EFh ;enable external /CE & upper 64K SRAM mov DPTR, #0AAAAh ; movx A, @DPTR ;read $1AAAA clr A mov P4, #0CFh ;enable external /CE & lower 64k SRAM mov DPTR, #05555h ; movx A, @DPTR ;read $05555 jmp Loop ;----------------------------------------------------------------------------- ; End of file. END