A51 MACRO ASSEMBLER ADC2 04/26/2006 10:02:25 PAGE 1 MACRO ASSEMBLER A51 V7.04a OBJECT MODULE PLACED IN adc2.OBJ ASSEMBLER INVOKED BY: F:\SiLabs\MCU\IDEfiles\C51\BIN\a51.exe adc2.asm XR GEN DB EP NOMOD51 LOC OBJ LINE SOURCE 1 ;----------------------------------------------------------------------------- 2 ; 4/26/2006 sjd 3 ; 4 ; 5 ; 6 ; FILE NAME : ADC2.ASM 7 ; TARGET MCU : C8051F120 8 ; DESCRIPTION : This program illustrates how to configure the 9 ; : ADC2 and Crossbar, read t he ADC2 and write to the 10 ; : port 2 & 3 I/O pins. 11 ; : LED displays used as indi cators. 12 ; 13 ; 14 ; NOTES: 15 ; 16 ; (1) This note intentionally left blank. 17 ; 18 ; 19 ;----------------------------------------------------------------------------- 20 21 22 ;----------------------------------------------------------------------------- 23 ; EQUATES 24 ;----------------------------------------------------------------------------- 25 26 ;$include (c8051f120.inc) ; Include register definition file. +1 27 ;--------------------------------------------------------------------------- +1 28 ; +1 29 ; +1 30 ; +1 31 ; +1 32 ; FILE NAME: C8051F120.INC +1 33 ; TARGET MCUs: C8051F120, F121, F122, F123, F124, F125, F126, F127 +1 34 ; DESCRIPTION: Register/bit definitions for the C8051F120 product family. +1 35 ; +1 36 ; REVISION 1.6 +1 37 ; +1 38 ;--------------------------------------------------------------------------- +1 39 +1 40 ;REGISTER DEFINITIONS +1 41 ; 0080 +1 42 P0 DATA 080H ; PORT 0 LATCH 0081 +1 43 SP DATA 081H ; STACK POINTER 0082 +1 44 DPL DATA 082H ; DATA POINTER LOW BYTE 0083 +1 45 DPH DATA 083H ; DATA POINTER HIGH BYTE 0084 +1 46 SFRPAGE DATA 084H ; SFR PAGE SELECT 0085 +1 47 SFRNEXT DATA 085H ; SFR STACK NEXT PAGE 0086 +1 48 SFRLAST DATA 086H ; SFR STACK LAST PAGE 0087 +1 49 PCON DATA 087H ; POWER CONTROL 0088 +1 50 FLSTAT DATA 088H ; FLASH STATUS 0088 +1 51 CPT0CN DATA 088H ; COMPARATOR 0 CONTROL 0088 +1 52 CPT1CN DATA 088H ; COMPARATOR 1 CONTROL 0088 +1 53 TCON DATA 088H ; TIMER/COUNTER CONTROL 0089 +1 54 TMOD DATA 089H ; TIMER/COUNTER MODE 0089 +1 55 CPT0MD DATA 089H ; COMPARATOR 0 CONFIGURATION 0089 +1 56 CPT1MD DATA 089H ; COMPARATOR 1 CONFIGURATION A51 MACRO ASSEMBLER ADC2 04/26/2006 10:02:25 PAGE 2 0089 +1 57 PLL0CN DATA 089H ; PLL CONTROL 008A +1 58 OSCICN DATA 08AH ; INTERNAL OSCILLATOR CONTROL 008A +1 59 TL0 DATA 08AH ; TIMER/COUNTER 0 LOW BYTE 008B +1 60 OSCICL DATA 08BH ; INTERNAL OSCILLATOR CALIBRATION 008B +1 61 TL1 DATA 08BH ; TIMER/COUNTER 1 LOW BYTE 008C +1 62 OSCXCN DATA 08CH ; EXTERNAL OSCILLATOR CONTROL 008C +1 63 TH0 DATA 08CH ; TIMER/COUNTER 0 HIGH BYTE 008D +1 64 TH1 DATA 08DH ; TIMER/COUNTER 1 HIGH BYTE 008D +1 65 PLL0DIV DATA 08DH ; PLL DIVIDER 008E +1 66 CKCON DATA 08EH ; CLOCK CONTROL 008E +1 67 PLL0MUL DATA 08EH ; PLL MULTIPLIER 008F +1 68 PSCTL DATA 08FH ; FLASH WRITE/ERASE CONTROL 008F +1 69 PLL0FLT DATA 08FH ; PLL FILTER 0090 +1 70 P1 DATA 090H ; PORT 1 LATCH 0091 +1 71 SSTA0 DATA 091H ; UART 0 STATUS 0091 +1 72 MAC0BL DATA 091H ; MAC0 B REGISTER LOW BYTE 0092 +1 73 MAC0BH DATA 092H ; MAC0 B REGISTER HIGH BYTE 0093 +1 74 MAC0ACC0 DATA 093H ; MAC0 ACCUMULATOR BYTE 0 0094 +1 75 MAC0ACC1 DATA 094H ; MAC0 ACCUMULATOR BYTE 1 0095 +1 76 MAC0ACC2 DATA 095H ; MAC0 ACCUMULATOR BYTE 2 0096 +1 77 SFRPGCN DATA 096H ; SFR PAGE CONTROL 0096 +1 78 MAC0ACC3 DATA 096H ; MAC0 ACCUMULATOR BYTE 3 0097 +1 79 MAC0OVR DATA 097H ; MAC0 ACCUMULATOR OVERFLOW BYTE 0097 +1 80 CLKSEL DATA 097H ; SYSTEM CLOCK SELECT 0098 +1 81 SCON0 DATA 098H ; UART 0 CONTROL 0098 +1 82 SCON1 DATA 098H ; UART 1 CONTROL 0099 +1 83 SBUF0 DATA 099H ; UART 0 DATA BUFFER 0099 +1 84 SBUF1 DATA 099H ; UART 1 DATA BUFFER 009A +1 85 SPI0CFG DATA 09AH ; SPI CONFIGURATION 009A +1 86 CCH0MA DATA 09AH ; CACHE MISS ACCUMULATOR 009B +1 87 SPI0DAT DATA 09BH ; SPI DATA 009C +1 88 P4MDOUT DATA 09CH ; PORT 4 OUTPUT MODE CONFIGURATION 009D +1 89 P5MDOUT DATA 09DH ; PORT 5 OUTPUT MODE CONFIGURATION 009D +1 90 SPI0CKR DATA 09DH ; SPI CLOCK RATE CONTROL 009E +1 91 P6MDOUT DATA 09EH ; PORT 6 OUTPUT MODE CONFIGURATION 009F +1 92 P7MDOUT DATA 09FH ; PORT 7 OUTPUT MODE CONFIGURATION 00A0 +1 93 P2 DATA 0A0H ; PORT 2 LATCH 00A1 +1 94 EMI0TC DATA 0A1H ; EMIF TIMING CONTROL 00A1 +1 95 CCH0CN DATA 0A1H ; CACHE CONTROL 00A2 +1 96 EMI0CN DATA 0A2H ; EMIF CONTROL 00A2 +1 97 CCH0TN DATA 0A2H ; CACHE TUNING 00A3 +1 98 EMI0CF DATA 0A3H ; EMIF CONFIGURATION 00A3 +1 99 CCH0LC DATA 0A3H ; CACHE LOCK 00A4 +1 100 P0MDOUT DATA 0A4H ; PORT 0 OUTPUT MODE CONFIGURATION 00A5 +1 101 P1MDOUT DATA 0A5H ; PORT 1 OUTPUT MODE CONFIGURATION 00A6 +1 102 P2MDOUT DATA 0A6H ; PORT 2 OUTPUT MODE CONFIGURATION 00A7 +1 103 P3MDOUT DATA 0A7H ; PORT 3 OUTPUT MODE CONFIGURATION 00A8 +1 104 IE DATA 0A8H ; INTERRUPT ENABLE 00A9 +1 105 SADDR0 DATA 0A9H ; UART 0 SLAVE ADDRESS 00AD +1 106 P1MDIN DATA 0ADH ; PORT 1 INPUT MODE 00B0 +1 107 P3 DATA 0B0H ; PORT 3 LATCH 00B1 +1 108 PSBANK DATA 0B1H ; FLASH BANK SELECT 00B7 +1 109 FLACL DATA 0B7H ; FLASH ACCESS LIMIT 00B7 +1 110 FLSCL DATA 0B7H ; FLASH SCALE 00B8 +1 111 IP DATA 0B8H ; INTERRUPT PRIORITY 00B9 +1 112 SADEN0 DATA 0B9H ; UART 0 SLAVE ADDRESS MASK 00BA +1 113 AMX0CF DATA 0BAH ; ADC0 MULTIPLEXER CONFIGURATION 00BA +1 114 AMX2CF DATA 0BAH ; ADC2 MULTIPLEXER CONFIGURATION 00BB +1 115 AMX0SL DATA 0BBH ; ADC0 MULTIPLEXER CHANNEL SELECT 00BB +1 116 AMX2SL DATA 0BBH ; ADC2 MULTIPLEXER CHANNEL SELECT 00BC +1 117 ADC0CF DATA 0BCH ; ADC0 CONFIGURATION 00BC +1 118 ADC2CF DATA 0BCH ; ADC2 CONFIGURATION 00BE +1 119 ADC0L DATA 0BEH ; ADC0 DATA WORD LOW BYTE 00BE +1 120 ADC2 DATA 0BEH ; ADC2DATA WORD 00BF +1 121 ADC0H DATA 0BFH ; ADC0 DATA WORD HIGH BYTE 00C0 +1 122 MAC0STA DATA 0C0H ; MAC0 STATUS A51 MACRO ASSEMBLER ADC2 04/26/2006 10:02:25 PAGE 3 00C0 +1 123 SMB0CN DATA 0C0H ; SMBUS CONTROL 00C1 +1 124 MAC0AL DATA 0C1H ; MAC0 A REGISTER LOW BYTE 00C1 +1 125 SMB0STA DATA 0C1H ; SMBUS STATUS 00C2 +1 126 MAC0AH DATA 0C2H ; MAC0 A REGISTER HIGH BYTE 00C2 +1 127 SMB0DAT DATA 0C2H ; SMBUS DATA 00C3 +1 128 MAC0CF DATA 0C3H ; MAC0 CONFIGURATION REGISTER 00C3 +1 129 SMB0ADR DATA 0C3H ; SMBUS SLAVE ADDRESS 00C4 +1 130 ADC0GTL DATA 0C4H ; ADC0 GREATER-THAN LOW BYTE 00C4 +1 131 ADC2GT DATA 0C4H ; ADC2 GREATER-THAN 00C5 +1 132 ADC0GTH DATA 0C5H ; ADC0 GREATER-THAN HIGH BYTE 00C6 +1 133 ADC0LTL DATA 0C6H ; ADC0 LESS-THAN LOW BYTE 00C6 +1 134 ADC2LT DATA 0C6H ; ADC2 LESS-THAN 00C7 +1 135 ADC0LTH DATA 0C7H ; ADC0 LESS-THAN HIGH BYTE 00C8 +1 136 P4 DATA 0C8H ; PORT 4 LATCH 00C8 +1 137 TMR2CN DATA 0C8H ; TIMER/COUNTER 2 CONTROL 00C8 +1 138 TMR3CN DATA 0C8H ; TIMER 3 CONTROL 00C8 +1 139 TMR4CN DATA 0C8H ; TIMER/COUNTER 4 CONTROL 00C9 +1 140 TMR2CF DATA 0C9H ; TIMER/COUNTER 2 CONFIGURATION 00C9 +1 141 TMR3CF DATA 0C9H ; TIMER 3 CONFIGURATION 00C9 +1 142 TMR4CF DATA 0C9H ; TIMER/COUNTER 4 CONFIGURATION 00CA +1 143 RCAP2L DATA 0CAH ; TIMER/COUNTER 2 CAPTURE/RELOAD LOW BYTE 00CA +1 144 RCAP3L DATA 0CAH ; TIMER 3 CAPTURE/RELOAD LOW BYTE 00CA +1 145 RCAP4L DATA 0CAH ; TIMER/COUNTER 4 CAPTURE/RELOAD LOW BYTE 00CB +1 146 RCAP2H DATA 0CBH ; TIMER/COUNTER 2 CAPTURE/RELOAD HIGH BYTE 00CB +1 147 RCAP3H DATA 0CBH ; TIMER 3 CAPTURE/RELOAD HIGH BYTE 00CB +1 148 RCAP4H DATA 0CBH ; TIMER/COUNTER 4 CAPTURE/RELOAD HIGH BYTE 00CC +1 149 TMR2L DATA 0CCH ; TIMER/COUNTER 2 LOW BYTE 00CC +1 150 TMR3L DATA 0CCH ; TIMER 3 LOW BYTE 00CC +1 151 TMR4L DATA 0CCH ; TIMER/COUNTER 4 LOW BYTE 00CD +1 152 TMR2H DATA 0CDH ; TIMER/COUNTER 2 HIGH BYTE 00CD +1 153 TMR3H DATA 0CDH ; TIMER 3 HIGH BYTE 00CD +1 154 TMR4H DATA 0CDH ; TIMER/COUNTER 4 HIGH BYTE 00CE +1 155 MAC0RNDL DATA 0CEH ; MAC0 ROUNDING REGISTER LOW BYTE 00CF +1 156 MAC0RNDH DATA 0CFH ; MAC0 ROUNDING REGISTER HIGH BYTE 00CF +1 157 SMB0CR DATA 0CFH ; SMBUS CLOCK RATE 00D0 +1 158 PSW DATA 0D0H ; PROGRAM STATUS WORD 00D1 +1 159 REF0CN DATA 0D1H ; VOLTAGE REFERENCE CONTROL 00D2 +1 160 DAC0L DATA 0D2H ; DAC0 LOW BYTE 00D2 +1 161 DAC1L DATA 0D2H ; DAC1 LOW BYTE 00D3 +1 162 DAC0H DATA 0D3H ; DAC0 HIGH BYTE 00D3 +1 163 DAC1H DATA 0D3H ; DAC1 HIGH BYTE 00D4 +1 164 DAC0CN DATA 0D4H ; DAC0 CONTROL 00D4 +1 165 DAC1CN DATA 0D4H ; DAC1 CONTROL 00D8 +1 166 P5 DATA 0D8H ; PORT 5 LATCH 00D8 +1 167 PCA0CN DATA 0D8H ; PCA CONTROL 00D9 +1 168 PCA0MD DATA 0D9H ; PCA MODE 00DA +1 169 PCA0CPM0 DATA 0DAH ; PCA MODULE 0 MODE 00DB +1 170 PCA0CPM1 DATA 0DBH ; PCA MODULE 1 MODE REGISTER 00DC +1 171 PCA0CPM2 DATA 0DCH ; PCA MODULE 2 MODE 00DD +1 172 PCA0CPM3 DATA 0DDH ; PCA MODULE 3 MODE 00DE +1 173 PCA0CPM4 DATA 0DEH ; PCA MODULE 4 MODE 00DF +1 174 PCA0CPM5 DATA 0DFH ; PCA MODULE 5 MODE 00E0 +1 175 ACC DATA 0E0H ; ACCUMULATOR 00E1 +1 176 XBR0 DATA 0E1H ; PORT I/O CROSSBAR CONTROL 0 00E1 +1 177 PCA0CPL5 DATA 0E1H ; PCA MODULE 5 CAPTURE/COMPARE LOW BYTE 00E2 +1 178 PCA0CPH5 DATA 0E2H ; PCA MODULE 5 CAPTURE/COMPARE HIGH BYTE 00E2 +1 179 XBR1 DATA 0E2H ; PORT I/O CROSSBAR CONTROL 1 00E3 +1 180 XBR2 DATA 0E3H ; PORT I/O CROSSBAR CONTROL 2 00E6 +1 181 EIE1 DATA 0E6H ; EXTENDED INTERRUPT ENABLE 1 00E7 +1 182 EIE2 DATA 0E7H ; EXTENDED INTERRUPT ENABLE 2 00E8 +1 183 ADC0CN DATA 0E8H ; ADC0 CONTROL 00E8 +1 184 ADC2CN DATA 0E8H ; ADC2 CONTROL 00E8 +1 185 P6 DATA 0E8H ; PORT 6 LATCH 00E9 +1 186 PCA0CPL2 DATA 0E9H ; PCA MODULE 2 CAPTURE/COMPARE LOW BYTE 00EA +1 187 PCA0CPH2 DATA 0EAH ; PCA MODULE 2 CAPTURE/COMPARE HIGH BYTE 00EB +1 188 PCA0CPL3 DATA 0EBH ; PCA MODULE 3 CAPTURE/COMPARE LOW BYTE A51 MACRO ASSEMBLER ADC2 04/26/2006 10:02:25 PAGE 4 00EC +1 189 PCA0CPH3 DATA 0ECH ; PCA MODULE 3 CAPTURE/COMPARE HIGH BYTE 00ED +1 190 PCA0CPL4 DATA 0EDH ; PCA MODULE 4 CAPTURE/COMPARE LOW BYTE 00EE +1 191 PCA0CPH4 DATA 0EEH ; PCA MODULE 4 CAPTURE/COMPARE HIGH BYTE 00EF +1 192 RSTSRC DATA 0EFH ; RESET SOURCE 00F0 +1 193 B DATA 0F0H ; B REGISTER 00F6 +1 194 EIP1 DATA 0F6H ; EXTERNAL INTERRUPT PRIORITY 1 00F7 +1 195 EIP2 DATA 0F7H ; EXTERNAL INTERRUPT PRIORITY 2 00F8 +1 196 P7 DATA 0F8H ; PORT 7 LATCH 00F8 +1 197 SPI0CN DATA 0F8H ; SPI CONTROL 00F9 +1 198 PCA0L DATA 0F9H ; PCA COUNTER LOW BYTE 00FA +1 199 PCA0H DATA 0FAH ; PCA COUNTER HIGH BYTE 00FB +1 200 PCA0CPL0 DATA 0FBH ; PCA MODULE 0 CAPTURE/COMPARE LOW BYTE 00FC +1 201 PCA0CPH0 DATA 0FCH ; PCA MODULE 0 CAPTURE/COMPARE HIGH BYTE 00FD +1 202 PCA0CPL1 DATA 0FDH ; PCA MODULE 1 CAPTURE/COMPARE LOW BYTE 00FE +1 203 PCA0CPH1 DATA 0FEH ; PCA MODULE 1 CAPTURE/COMPARE HIGH BYTE 00FF +1 204 WDTCN DATA 0FFH ; WATCHDOG TIMER CONTROL +1 205 +1 206 ; +1 207 ;------------------------------------------------------------------------------ +1 208 ;BIT DEFINITIONS +1 209 ; +1 210 ; TCON 088H 008F +1 211 TF1 BIT 08FH ; TIMER 1 OVERFLOW FLAG 008E +1 212 TR1 BIT 08EH ; TIMER 1 ON/OFF CONTROL 008D +1 213 TF0 BIT 08DH ; TIMER 0 OVERFLOW FLAG 008C +1 214 TR0 BIT 08CH ; TIMER 0 ON/OFF CONTROL 008B +1 215 IE1 BIT 08BH ; EXT. INTERRUPT 1 EDGE FLAG 008A +1 216 IT1 BIT 08AH ; EXT. INTERRUPT 1 TYPE 0089 +1 217 IE0 BIT 089H ; EXT. INTERRUPT 0 EDGE FLAG 0088 +1 218 IT0 BIT 088H ; EXT. INTERRUPT 0 TYPE +1 219 +1 220 ; CPT0CN 088H 008F +1 221 CP0EN BIT 08FH ; COMPARATOR 0 ENABLE 008E +1 222 CP0OUT BIT 08EH ; COMPARATOR 0 OUTPUT 008D +1 223 CP0RIF BIT 08DH ; COMPARATOR 0 RISING EDGE INTERRUPT 008C +1 224 CP0FIF BIT 08CH ; COMPARATOR 0 FALLING EDGE INTERRUPT 008B +1 225 CP0HYP1 BIT 08BH ; COMPARATOR 0 POSITIVE HYSTERISIS 1 008A +1 226 CP0HYP0 BIT 08AH ; COMPARATOR 0 POSITIVE HYSTERISIS 0 0089 +1 227 CP0HYN1 BIT 089H ; COMPARATOR 0 NEGATIVE HYSTERISIS 1 0088 +1 228 CP0HYN0 BIT 088H ; COMPARATOR 0 NEGATIVE HYSTERISIS 0 +1 229 +1 230 ; CPT1CN 088H 008F +1 231 CP1EN BIT 08FH ; COMPARATOR 1 ENABLE 008E +1 232 CP1OUT BIT 08EH ; COMPARATOR 1 OUTPUT 008D +1 233 CP1RIF BIT 08DH ; COMPARATOR 1 RISING EDGE INTERRUPT 008C +1 234 CP1FIF BIT 08CH ; COMPARATOR 1 FALLING EDGE INTERRUPT 008B +1 235 CP1HYP1 BIT 08BH ; COMPARATOR 1 POSITIVE HYSTERISIS 1 008A +1 236 CP1HYP0 BIT 08AH ; COMPARATOR 1 POSITIVE HYSTERISIS 0 0089 +1 237 CP1HYN1 BIT 089H ; COMPARATOR 1 NEGATIVE HYSTERISIS 1 0088 +1 238 CP1HYN0 BIT 088H ; COMPARATOR 1 NEGATIVE HYSTERISIS 0 +1 239 +1 240 ; FLSTAT 088H 0088 +1 241 FLHBUSY BIT 088H ; FLASH BUSY +1 242 +1 243 ; SCON0 098H 009F +1 244 SM00 BIT 09FH ; UART 0 MODE 0 009E +1 245 SM10 BIT 09EH ; UART 0 MODE 1 009D +1 246 SM20 BIT 09DH ; UART 0 MULTIPROCESSOR EN 009C +1 247 REN0 BIT 09CH ; UART 0 RX ENABLE 009B +1 248 TB80 BIT 09BH ; UART 0 TX BIT 8 009A +1 249 RB80 BIT 09AH ; UART 0 RX BIT 8 0099 +1 250 TI0 BIT 099H ; UART 0 TX INTERRUPT FLAG 0098 +1 251 RI0 BIT 098H ; UART 0 RX INTERRUPT FLAG +1 252 +1 253 ; SCON1 098H 009F +1 254 S1MODE BIT 09FH ; UART 1 MODE A51 MACRO ASSEMBLER ADC2 04/26/2006 10:02:25 PAGE 5 009D +1 255 MCE1 BIT 09DH ; UART 1 MCE 009C +1 256 REN1 BIT 09CH ; UART 1 RX ENABLE 009B +1 257 TB81 BIT 09BH ; UART 1 TX BIT 8 009A +1 258 RB81 BIT 09AH ; UART 1 RX BIT 8 0099 +1 259 TI1 BIT 099H ; UART 1 TX INTERRUPT FLAG 0098 +1 260 RI1 BIT 098H ; UART 1 RX INTERRUPT FLAG +1 261 +1 262 ; IE 0A8H 00AF +1 263 EA BIT 0AFH ; GLOBAL INTERRUPT ENABLE 00AD +1 264 ET2 BIT 0ADH ; TIMER 2 INTERRUPT ENABLE 00AC +1 265 ES0 BIT 0ACH ; UART0 INTERRUPT ENABLE 00AB +1 266 ET1 BIT 0ABH ; TIMER 1 INTERRUPT ENABLE 00AA +1 267 EX1 BIT 0AAH ; EXTERNAL INTERRUPT 1 ENABLE 00A9 +1 268 ET0 BIT 0A9H ; TIMER 0 INTERRUPT ENABLE 00A8 +1 269 EX0 BIT 0A8H ; EXTERNAL INTERRUPT 0 ENABLE +1 270 +1 271 ; IP 0B8H 00BD +1 272 PT2 BIT 0BDH ; TIMER 2 PRIORITY 00BC +1 273 PS BIT 0BCH ; SERIAL PORT PRIORITY 00BB +1 274 PT1 BIT 0BBH ; TIMER 1 PRIORITY 00BA +1 275 PX1 BIT 0BAH ; EXTERNAL INTERRUPT 1 PRIORITY 00B9 +1 276 PT0 BIT 0B9H ; TIMER 0 PRIORITY 00B8 +1 277 PX0 BIT 0B8H ; EXTERNAL INTERRUPT 0 PRIORITY +1 278 +1 279 ; SMB0CN 0C0H 00C7 +1 280 BUSY BIT 0C7H ; SMBUS 0 BUSY 00C6 +1 281 ENSMB BIT 0C6H ; SMBUS 0 ENABLE 00C5 +1 282 STA BIT 0C5H ; SMBUS 0 START FLAG 00C4 +1 283 STO BIT 0C4H ; SMBUS 0 STOP FLAG 00C3 +1 284 SI BIT 0C3H ; SMBUS 0 INTERRUPT PENDING FLAG 00C2 +1 285 AA BIT 0C2H ; SMBUS 0 ASSERT/ACKNOWLEDGE FLAG 00C1 +1 286 SMBFTE BIT 0C1H ; SMBUS 0 FREE TIMER ENABLE 00C0 +1 287 SMBTOE BIT 0C0H ; SMBUS 0 TIMEOUT ENABLE +1 288 +1 289 ; MAC0STA 0C0H 00C3 +1 290 MAC0HO BIT 0C3H ; MAC0 HARD OVERFLOW 00C2 +1 291 MAC0Z BIT 0C2H ; MAC0 ZERO 00C1 +1 292 MAC0SO BIT 0C1H ; MAC0 SOFT OVERFLOW 00C0 +1 293 MAC0N BIT 0C0H ; MAC0 NEGATIVE +1 294 +1 295 ; TMR2CN 0C8H 00CF +1 296 TF2 BIT 0CFH ; TIMER 2 OVERFLOW FLAG 00CE +1 297 EXF2 BIT 0CEH ; TIMER 2 EXTERNAL FLAG 00CB +1 298 EXEN2 BIT 0CBH ; TIMER 2 EXTERNAL ENABLE FLAG 00CA +1 299 TR2 BIT 0CAH ; TIMER 2 ON/OFF CONTROL 00C9 +1 300 CT2 BIT 0C9H ; TIMER 2 COUNTER SELECT 00C8 +1 301 CPRL2 BIT 0C8H ; TIMER 2 CAPTURE SELECT +1 302 +1 303 ; TMR3CN 0C8H 00CF +1 304 TF3 BIT 0CFH ; TIMER 3 OVERFLOW FLAG 00CE +1 305 EXF3 BIT 0CEH ; TIMER 3 EXTERNAL FLAG 00CB +1 306 EXEN3 BIT 0CBH ; TIMER 3 EXTERNAL ENABLE FLAG 00CA +1 307 TR3 BIT 0CAH ; TIMER 3 ON/OFF CONTROL 00C9 +1 308 CT3 BIT 0C9H ; TIMER 3 COUNTER SELECT 00C8 +1 309 CPRL3 BIT 0C8H ; TIMER 3 CAPTURE SELECT +1 310 +1 311 ; TMR4CN 0C8H 00CF +1 312 TF4 BIT 0CFH ; TIMER 4 OVERFLOW FLAG 00CE +1 313 EXF4 BIT 0CEH ; TIMER 4 EXTERNAL FLAG 00CB +1 314 EXEN4 BIT 0CBH ; TIMER 4 EXTERNAL ENABLE FLAG 00CA +1 315 TR4 BIT 0CAH ; TIMER 4 ON/OFF CONTROL 00C9 +1 316 CT4 BIT 0C9H ; TIMER 4 COUNTER SELECT 00C8 +1 317 CPRL4 BIT 0C8H ; TIMER 4 CAPTURE SELECT +1 318 +1 319 ; PSW 0D0H 00D7 +1 320 CY BIT 0D7H ; CARRY FLAG A51 MACRO ASSEMBLER ADC2 04/26/2006 10:02:25 PAGE 6 00D6 +1 321 AC BIT 0D6H ; AUXILIARY CARRY FLAG 00D5 +1 322 F0 BIT 0D5H ; USER FLAG 0 00D4 +1 323 RS1 BIT 0D4H ; REGISTER BANK SELECT 1 00D3 +1 324 RS0 BIT 0D3H ; REGISTER BANK SELECT 0 00D2 +1 325 OV BIT 0D2H ; OVERFLOW FLAG 00D1 +1 326 F1 BIT 0D1H ; USER FLAG 1 00D0 +1 327 P BIT 0D0H ; ACCUMULATOR PARITY FLAG +1 328 +1 329 ; PCA0CN 0D8H 00DF +1 330 CF BIT 0DFH ; PCA 0 COUNTER OVERFLOW FLAG 00DE +1 331 CR BIT 0DEH ; PCA 0 COUNTER RUN CONTROL BIT 00DD +1 332 CCF5 BIT 0DDH ; PCA 0 MODULE 5 INTERRUPT FLAG 00DC +1 333 CCF4 BIT 0DCH ; PCA 0 MODULE 4 INTERRUPT FLAG 00DB +1 334 CCF3 BIT 0DBH ; PCA 0 MODULE 3 INTERRUPT FLAG 00DA +1 335 CCF2 BIT 0DAH ; PCA 0 MODULE 2 INTERRUPT FLAG 00D9 +1 336 CCF1 BIT 0D9H ; PCA 0 MODULE 1 INTERRUPT FLAG 00D8 +1 337 CCF0 BIT 0D8H ; PCA 0 MODULE 0 INTERRUPT FLAG +1 338 +1 339 ; ADC0CN 0E8H 00EF +1 340 AD0EN BIT 0EFH ; ADC 0 ENABLE 00EE +1 341 AD0TM BIT 0EEH ; ADC 0 TRACK MODE 00ED +1 342 AD0INT BIT 0EDH ; ADC 0 EOC INTERRUPT FLAG 00EC +1 343 AD0BUSY BIT 0ECH ; ADC 0 BUSY FLAG 00EB +1 344 AD0CM1 BIT 0EBH ; ADC 0 CONVERT START MODE BIT 1 00EA +1 345 AD0CM0 BIT 0EAH ; ADC 0 CONVERT START MODE BIT 0 00E9 +1 346 AD0WINT BIT 0E9H ; ADC 0 WINDOW INTERRUPT FLAG 00E8 +1 347 AD0LJST BIT 0E8H ; ADC 0 LEFT JUSTIFY DATA BIT +1 348 +1 349 ; ADC2CN 0E8H 00EF +1 350 AD2EN BIT 0EFH ; ADC 2 ENABLE 00EE +1 351 AD2TM BIT 0EEH ; ADC 2 TRACK MODE 00ED +1 352 AD2INT BIT 0EDH ; ADC 2 EOC INTERRUPT FLAG 00EC +1 353 AD2BUSY BIT 0ECH ; ADC 2 BUSY FLAG 00EB +1 354 AD2CM2 BIT 0EBH ; ADC 2 CONVERT START MODE BIT 2 00EA +1 355 AD2CM1 BIT 0EAH ; ADC 2 CONVERT START MODE BIT 1 00E9 +1 356 AD2CM0 BIT 0E9H ; ADC 2 CONVERT START MODE BIT 0 00E8 +1 357 AD2WINT BIT 0E8H ; ADC 2 WINDOW INTERRUPT FLAG +1 358 +1 359 ; SPI0CN 0F8H 00FF +1 360 SPIF BIT 0FFH ; SPI 0 INTERRUPT FLAG 00FE +1 361 WCOL BIT 0FEH ; SPI 0 WRITE COLLISION FLAG 00FD +1 362 MODF BIT 0FDH ; SPI 0 MODE FAULT FLAG 00FC +1 363 RXOVRN BIT 0FCH ; SPI 0 RX OVERRUN FLAG 00FB +1 364 NSSMD1 BIT 0FBH ; SPI 0 SLAVE SELECT MODE 1 00FA +1 365 NSSMD0 BIT 0FAH ; SPI 0 SLAVE SELECT MODE 0 00F9 +1 366 TXBMT BIT 0F9H ; SPI 0 TX BUFFER EMPTY FLAG 00F8 +1 367 SPIEN BIT 0F8H ; SPI 0 SPI ENABLE +1 368 +1 369 ; +1 370 ;------------------------------------------------------------------------------ +1 371 ; SFR PAGE DEFINITIONS +1 372 ; 000F +1 373 CONFIG_PAGE EQU 0FH ; SYSTEM AND PORT CONFIGURATION PAGE 0000 +1 374 LEGACY_PAGE EQU 00H ; LEGACY SFR PAGE 0000 +1 375 TIMER01_PAGE EQU 00H ; TIMER 0 AND TIMER 1 0001 +1 376 CPT0_PAGE EQU 01H ; COMPARATOR 0 0002 +1 377 CPT1_PAGE EQU 02H ; COMPARATOR 1 0000 +1 378 UART0_PAGE EQU 00H ; UART 0 0001 +1 379 UART1_PAGE EQU 01H ; UART 1 0000 +1 380 SPI0_PAGE EQU 00H ; SPI 0 0000 +1 381 EMI0_PAGE EQU 00H ; EXTERNAL MEMORY INTERFACE 0000 +1 382 ADC0_PAGE EQU 00H ; ADC 0 0002 +1 383 ADC2_PAGE EQU 02H ; ADC 2 0000 +1 384 SMB0_PAGE EQU 00H ; SMBUS 0 0000 +1 385 TMR2_PAGE EQU 00H ; TIMER 2 0001 +1 386 TMR3_PAGE EQU 01H ; TIMER 3 A51 MACRO ASSEMBLER ADC2 04/26/2006 10:02:25 PAGE 7 0002 +1 387 TMR4_PAGE EQU 02H ; TIMER 4 0000 +1 388 DAC0_PAGE EQU 00H ; DAC 0 0001 +1 389 DAC1_PAGE EQU 01H ; DAC 1 0000 +1 390 PCA0_PAGE EQU 00H ; PCA 0 000F +1 391 PLL0_PAGE EQU 0FH ; PLL 0 0003 +1 392 MAC0_PAGE EQU 03H ; MAC 0 393 394 395 ;----------------------------------------------------------------------------- 396 ; VARIABLES 397 ;----------------------------------------------------------------------------- 398 399 ;----------------------------------------------------------------------------- 400 ; RESET and INTERRUPT VECTORS 401 ;----------------------------------------------------------------------------- 402 403 404 ; Reset Vector ---- 405 cseg AT 0 0000 020000 F 406 ljmp Main ; Locate a jump to the start of code at 407 ; the reset vector. 408 409 ;----------------------------------------------------------------------------- 410 ; CODE SEGMENT 411 ;----------------------------------------------------------------------------- 412 413 Code_Seg segment CODE 414 ---- 415 rseg Code_Seg ; Switch to this code segment. 416 using 0 ; Specify register bank for the following 417 ; program code. 418 419 ; Set SFRPAGE to LEGACY_PAGE before writing to REF0 CN 0000 758400 420 Main: mov SFRPAGE, #LEGACY_PAGE 421 422 ; Enable Vref - required before using adc 0003 75D103 423 mov REF0CN, #00000011b ; bias on, int vref. 424 0006 7800 425 mov R0, #0 ;clear R0 0008 7900 426 mov R1, #0 ;clear R1 427 428 ; Use SFRs on Configuration Page 000A 75840F 429 mov SFRPAGE, #CONFIG_PAGE 430 431 ; Enable the Port I/O Crossbar 000D 75E340 432 mov XBR2, #40h 433 434 ; P2, P3 set for output to LED displays. 0010 88A0 435 mov P2, R0 0012 89B0 436 mov P3, R1 437 438 ; Use SFRs on ADC0_PAGE 0014 758400 439 mov SFRPAGE, #ADC0_PAGE 440 441 ;loop. 0017 75BB02 442 mov AMX0SL, #00000010b ; select ad c2 001A 75E890 443 Loop: mov ADC0CN, #10010000b 001D A8BF 444 mov R0, ADC0H 001F A9BE 445 mov R1, ADC0L 0021 88A0 446 mov P2, R0 ; write ADC0H value to port2 0023 89B0 447 mov P3, R1 ; write ADC0L value to port3 0025 80F3 448 jmp Loop A51 MACRO ASSEMBLER ADC2 04/26/2006 10:02:25 PAGE 8 449 450 451 ;----------------------------------------------------------------------------- 452 ; End of file. 453 454 END A51 MACRO ASSEMBLER ADC2 04/26/2006 10:02:25 PAGE 9 XREF SYMBOL TABLE LISTING ---- ------ ----- ------- N A M E T Y P E V A L U E ATTRIBUTES / REFERENCES AA . . . . . . . . B ADDR 00C0H.2 A 285# AC . . . . . . . . B ADDR 00D0H.6 A 321# ACC. . . . . . . . D ADDR 00E0H A 175# AD0BUSY. . . . . . B ADDR 00E8H.4 A 343# AD0CM0 . . . . . . B ADDR 00E8H.2 A 345# AD0CM1 . . . . . . B ADDR 00E8H.3 A 344# AD0EN. . . . . . . B ADDR 00E8H.7 A 340# AD0INT . . . . . . B ADDR 00E8H.5 A 342# AD0LJST. . . . . . B ADDR 00E8H.0 A 347# AD0TM. . . . . . . B ADDR 00E8H.6 A 341# AD0WINT. . . . . . B ADDR 00E8H.1 A 346# AD2BUSY. . . . . . B ADDR 00E8H.4 A 353# AD2CM0 . . . . . . B ADDR 00E8H.1 A 356# AD2CM1 . . . . . . B ADDR 00E8H.2 A 355# AD2CM2 . . . . . . B ADDR 00E8H.3 A 354# AD2EN. . . . . . . B ADDR 00E8H.7 A 350# AD2INT . . . . . . B ADDR 00E8H.5 A 352# AD2TM. . . . . . . B ADDR 00E8H.6 A 351# AD2WINT. . . . . . B ADDR 00E8H.0 A 357# ADC0CF . . . . . . D ADDR 00BCH A 117# ADC0CN . . . . . . D ADDR 00E8H A 183# 443 ADC0GTH. . . . . . D ADDR 00C5H A 132# ADC0GTL. . . . . . D ADDR 00C4H A 130# ADC0H. . . . . . . D ADDR 00BFH A 121# 444 ADC0L. . . . . . . D ADDR 00BEH A 119# 445 ADC0LTH. . . . . . D ADDR 00C7H A 135# ADC0LTL. . . . . . D ADDR 00C6H A 133# ADC0_PAGE. . . . . N NUMB 0000H A 382# 439 ADC2 . . . . . . . D ADDR 00BEH A 120# ADC2CF . . . . . . D ADDR 00BCH A 118# ADC2CN . . . . . . D ADDR 00E8H A 184# ADC2GT . . . . . . D ADDR 00C4H A 131# ADC2LT . . . . . . D ADDR 00C6H A 134# ADC2_PAGE. . . . . N NUMB 0002H A 383# AMX0CF . . . . . . D ADDR 00BAH A 113# AMX0SL . . . . . . D ADDR 00BBH A 115# 442 AMX2CF . . . . . . D ADDR 00BAH A 114# AMX2SL . . . . . . D ADDR 00BBH A 116# B. . . . . . . . . D ADDR 00F0H A 193# BUSY . . . . . . . B ADDR 00C0H.7 A 280# CCF0 . . . . . . . B ADDR 00D8H.0 A 337# CCF1 . . . . . . . B ADDR 00D8H.1 A 336# CCF2 . . . . . . . B ADDR 00D8H.2 A 335# CCF3 . . . . . . . B ADDR 00D8H.3 A 334# CCF4 . . . . . . . B ADDR 00D8H.4 A 333# CCF5 . . . . . . . B ADDR 00D8H.5 A 332# CCH0CN . . . . . . D ADDR 00A1H A 95# CCH0LC . . . . . . D ADDR 00A3H A 99# CCH0MA . . . . . . D ADDR 009AH A 86# CCH0TN . . . . . . D ADDR 00A2H A 97# CF . . . . . . . . B ADDR 00D8H.7 A 330# CKCON. . . . . . . D ADDR 008EH A 66# CLKSEL . . . . . . D ADDR 0097H A 80# CODE_SEG . . . . . C SEG 0027H REL=UNIT 413# 415 CONFIG_PAGE. . . . N NUMB 000FH A 373# 429 CP0EN. . . . . . . B ADDR 0088H.7 A 221# CP0FIF . . . . . . B ADDR 0088H.4 A 224# CP0HYN0. . . . . . B ADDR 0088H.0 A 228# CP0HYN1. . . . . . B ADDR 0088H.1 A 227# CP0HYP0. . . . . . B ADDR 0088H.2 A 226# A51 MACRO ASSEMBLER ADC2 04/26/2006 10:02:25 PAGE 10 CP0HYP1. . . . . . B ADDR 0088H.3 A 225# CP0OUT . . . . . . B ADDR 0088H.6 A 222# CP0RIF . . . . . . B ADDR 0088H.5 A 223# CP1EN. . . . . . . B ADDR 0088H.7 A 231# CP1FIF . . . . . . B ADDR 0088H.4 A 234# CP1HYN0. . . . . . B ADDR 0088H.0 A 238# CP1HYN1. . . . . . B ADDR 0088H.1 A 237# CP1HYP0. . . . . . B ADDR 0088H.2 A 236# CP1HYP1. . . . . . B ADDR 0088H.3 A 235# CP1OUT . . . . . . B ADDR 0088H.6 A 232# CP1RIF . . . . . . B ADDR 0088H.5 A 233# CPRL2. . . . . . . B ADDR 00C8H.0 A 301# CPRL3. . . . . . . B ADDR 00C8H.0 A 309# CPRL4. . . . . . . B ADDR 00C8H.0 A 317# CPT0CN . . . . . . D ADDR 0088H A 51# CPT0MD . . . . . . D ADDR 0089H A 55# CPT0_PAGE. . . . . N NUMB 0001H A 376# CPT1CN . . . . . . D ADDR 0088H A 52# CPT1MD . . . . . . D ADDR 0089H A 56# CPT1_PAGE. . . . . N NUMB 0002H A 377# CR . . . . . . . . B ADDR 00D8H.6 A 331# CT2. . . . . . . . B ADDR 00C8H.1 A 300# CT3. . . . . . . . B ADDR 00C8H.1 A 308# CT4. . . . . . . . B ADDR 00C8H.1 A 316# CY . . . . . . . . B ADDR 00D0H.7 A 320# DAC0CN . . . . . . D ADDR 00D4H A 164# DAC0H. . . . . . . D ADDR 00D3H A 162# DAC0L. . . . . . . D ADDR 00D2H A 160# DAC0_PAGE. . . . . N NUMB 0000H A 388# DAC1CN . . . . . . D ADDR 00D4H A 165# DAC1H. . . . . . . D ADDR 00D3H A 163# DAC1L. . . . . . . D ADDR 00D2H A 161# DAC1_PAGE. . . . . N NUMB 0001H A 389# DPH. . . . . . . . D ADDR 0083H A 45# DPL. . . . . . . . D ADDR 0082H A 44# EA . . . . . . . . B ADDR 00A8H.7 A 263# EIE1 . . . . . . . D ADDR 00E6H A 181# EIE2 . . . . . . . D ADDR 00E7H A 182# EIP1 . . . . . . . D ADDR 00F6H A 194# EIP2 . . . . . . . D ADDR 00F7H A 195# EMI0CF . . . . . . D ADDR 00A3H A 98# EMI0CN . . . . . . D ADDR 00A2H A 96# EMI0TC . . . . . . D ADDR 00A1H A 94# EMI0_PAGE. . . . . N NUMB 0000H A 381# ENSMB. . . . . . . B ADDR 00C0H.6 A 281# ES0. . . . . . . . B ADDR 00A8H.4 A 265# ET0. . . . . . . . B ADDR 00A8H.1 A 268# ET1. . . . . . . . B ADDR 00A8H.3 A 266# ET2. . . . . . . . B ADDR 00A8H.5 A 264# EX0. . . . . . . . B ADDR 00A8H.0 A 269# EX1. . . . . . . . B ADDR 00A8H.2 A 267# EXEN2. . . . . . . B ADDR 00C8H.3 A 298# EXEN3. . . . . . . B ADDR 00C8H.3 A 306# EXEN4. . . . . . . B ADDR 00C8H.3 A 314# EXF2 . . . . . . . B ADDR 00C8H.6 A 297# EXF3 . . . . . . . B ADDR 00C8H.6 A 305# EXF4 . . . . . . . B ADDR 00C8H.6 A 313# F0 . . . . . . . . B ADDR 00D0H.5 A 322# F1 . . . . . . . . B ADDR 00D0H.1 A 326# FLACL. . . . . . . D ADDR 00B7H A 109# FLHBUSY. . . . . . B ADDR 0088H.0 A 241# FLSCL. . . . . . . D ADDR 00B7H A 110# FLSTAT . . . . . . D ADDR 0088H A 50# IE . . . . . . . . D ADDR 00A8H A 104# IE0. . . . . . . . B ADDR 0088H.1 A 217# IE1. . . . . . . . B ADDR 0088H.3 A 215# A51 MACRO ASSEMBLER ADC2 04/26/2006 10:02:25 PAGE 11 IP . . . . . . . . D ADDR 00B8H A 111# IT0. . . . . . . . B ADDR 0088H.0 A 218# IT1. . . . . . . . B ADDR 0088H.2 A 216# LEGACY_PAGE. . . . N NUMB 0000H A 374# 420 LOOP . . . . . . . C ADDR 001AH R SEG=CODE_SEG 443# 448 MAC0ACC0 . . . . . D ADDR 0093H A 74# MAC0ACC1 . . . . . D ADDR 0094H A 75# MAC0ACC2 . . . . . D ADDR 0095H A 76# MAC0ACC3 . . . . . D ADDR 0096H A 78# MAC0AH . . . . . . D ADDR 00C2H A 126# MAC0AL . . . . . . D ADDR 00C1H A 124# MAC0BH . . . . . . D ADDR 0092H A 73# MAC0BL . . . . . . D ADDR 0091H A 72# MAC0CF . . . . . . D ADDR 00C3H A 128# MAC0HO . . . . . . B ADDR 00C0H.3 A 290# MAC0N. . . . . . . B ADDR 00C0H.0 A 293# MAC0OVR. . . . . . D ADDR 0097H A 79# MAC0RNDH . . . . . D ADDR 00CFH A 156# MAC0RNDL . . . . . D ADDR 00CEH A 155# MAC0SO . . . . . . B ADDR 00C0H.1 A 292# MAC0STA. . . . . . D ADDR 00C0H A 122# MAC0Z. . . . . . . B ADDR 00C0H.2 A 291# MAC0_PAGE. . . . . N NUMB 0003H A 392# MAIN . . . . . . . C ADDR 0000H R SEG=CODE_SEG 406 420# MCE1 . . . . . . . B ADDR 0098H.5 A 255# MODF . . . . . . . B ADDR 00F8H.5 A 362# NSSMD0 . . . . . . B ADDR 00F8H.2 A 365# NSSMD1 . . . . . . B ADDR 00F8H.3 A 364# OSCICL . . . . . . D ADDR 008BH A 60# OSCICN . . . . . . D ADDR 008AH A 58# OSCXCN . . . . . . D ADDR 008CH A 62# OV . . . . . . . . B ADDR 00D0H.2 A 325# P. . . . . . . . . B ADDR 00D0H.0 A 327# P0 . . . . . . . . D ADDR 0080H A 42# P0MDOUT. . . . . . D ADDR 00A4H A 100# P1 . . . . . . . . D ADDR 0090H A 70# P1MDIN . . . . . . D ADDR 00ADH A 106# P1MDOUT. . . . . . D ADDR 00A5H A 101# P2 . . . . . . . . D ADDR 00A0H A 93# 435 446 P2MDOUT. . . . . . D ADDR 00A6H A 102# P3 . . . . . . . . D ADDR 00B0H A 107# 436 447 P3MDOUT. . . . . . D ADDR 00A7H A 103# P4 . . . . . . . . D ADDR 00C8H A 136# P4MDOUT. . . . . . D ADDR 009CH A 88# P5 . . . . . . . . D ADDR 00D8H A 166# P5MDOUT. . . . . . D ADDR 009DH A 89# P6 . . . . . . . . D ADDR 00E8H A 185# P6MDOUT. . . . . . D ADDR 009EH A 91# P7 . . . . . . . . D ADDR 00F8H A 196# P7MDOUT. . . . . . D ADDR 009FH A 92# PCA0CN . . . . . . D ADDR 00D8H A 167# PCA0CPH0 . . . . . D ADDR 00FCH A 201# PCA0CPH1 . . . . . D ADDR 00FEH A 203# PCA0CPH2 . . . . . D ADDR 00EAH A 187# PCA0CPH3 . . . . . D ADDR 00ECH A 189# PCA0CPH4 . . . . . D ADDR 00EEH A 191# PCA0CPH5 . . . . . D ADDR 00E2H A 178# PCA0CPL0 . . . . . D ADDR 00FBH A 200# PCA0CPL1 . . . . . D ADDR 00FDH A 202# PCA0CPL2 . . . . . D ADDR 00E9H A 186# PCA0CPL3 . . . . . D ADDR 00EBH A 188# PCA0CPL4 . . . . . D ADDR 00EDH A 190# PCA0CPL5 . . . . . D ADDR 00E1H A 177# PCA0CPM0 . . . . . D ADDR 00DAH A 169# PCA0CPM1 . . . . . D ADDR 00DBH A 170# PCA0CPM2 . . . . . D ADDR 00DCH A 171# A51 MACRO ASSEMBLER ADC2 04/26/2006 10:02:25 PAGE 12 PCA0CPM3 . . . . . D ADDR 00DDH A 172# PCA0CPM4 . . . . . D ADDR 00DEH A 173# PCA0CPM5 . . . . . D ADDR 00DFH A 174# PCA0H. . . . . . . D ADDR 00FAH A 199# PCA0L. . . . . . . D ADDR 00F9H A 198# PCA0MD . . . . . . D ADDR 00D9H A 168# PCA0_PAGE. . . . . N NUMB 0000H A 390# PCON . . . . . . . D ADDR 0087H A 49# PLL0CN . . . . . . D ADDR 0089H A 57# PLL0DIV. . . . . . D ADDR 008DH A 65# PLL0FLT. . . . . . D ADDR 008FH A 69# PLL0MUL. . . . . . D ADDR 008EH A 67# PLL0_PAGE. . . . . N NUMB 000FH A 391# PS . . . . . . . . B ADDR 00B8H.4 A 273# PSBANK . . . . . . D ADDR 00B1H A 108# PSCTL. . . . . . . D ADDR 008FH A 68# PSW. . . . . . . . D ADDR 00D0H A 158# PT0. . . . . . . . B ADDR 00B8H.1 A 276# PT1. . . . . . . . B ADDR 00B8H.3 A 274# PT2. . . . . . . . B ADDR 00B8H.5 A 272# PX0. . . . . . . . B ADDR 00B8H.0 A 277# PX1. . . . . . . . B ADDR 00B8H.2 A 275# RB80 . . . . . . . B ADDR 0098H.2 A 249# RB81 . . . . . . . B ADDR 0098H.2 A 258# RCAP2H . . . . . . D ADDR 00CBH A 146# RCAP2L . . . . . . D ADDR 00CAH A 143# RCAP3H . . . . . . D ADDR 00CBH A 147# RCAP3L . . . . . . D ADDR 00CAH A 144# RCAP4H . . . . . . D ADDR 00CBH A 148# RCAP4L . . . . . . D ADDR 00CAH A 145# REF0CN . . . . . . D ADDR 00D1H A 159# 423 REN0 . . . . . . . B ADDR 0098H.4 A 247# REN1 . . . . . . . B ADDR 0098H.4 A 256# RI0. . . . . . . . B ADDR 0098H.0 A 251# RI1. . . . . . . . B ADDR 0098H.0 A 260# RS0. . . . . . . . B ADDR 00D0H.3 A 324# RS1. . . . . . . . B ADDR 00D0H.4 A 323# RSTSRC . . . . . . D ADDR 00EFH A 192# RXOVRN . . . . . . B ADDR 00F8H.4 A 363# S1MODE . . . . . . B ADDR 0098H.7 A 254# SADDR0 . . . . . . D ADDR 00A9H A 105# SADEN0 . . . . . . D ADDR 00B9H A 112# SBUF0. . . . . . . D ADDR 0099H A 83# SBUF1. . . . . . . D ADDR 0099H A 84# SCON0. . . . . . . D ADDR 0098H A 81# SCON1. . . . . . . D ADDR 0098H A 82# SFRLAST. . . . . . D ADDR 0086H A 48# SFRNEXT. . . . . . D ADDR 0085H A 47# SFRPAGE. . . . . . D ADDR 0084H A 46# 420 429 439 SFRPGCN. . . . . . D ADDR 0096H A 77# SI . . . . . . . . B ADDR 00C0H.3 A 284# SM00 . . . . . . . B ADDR 0098H.7 A 244# SM10 . . . . . . . B ADDR 0098H.6 A 245# SM20 . . . . . . . B ADDR 0098H.5 A 246# SMB0ADR. . . . . . D ADDR 00C3H A 129# SMB0CN . . . . . . D ADDR 00C0H A 123# SMB0CR . . . . . . D ADDR 00CFH A 157# SMB0DAT. . . . . . D ADDR 00C2H A 127# SMB0STA. . . . . . D ADDR 00C1H A 125# SMB0_PAGE. . . . . N NUMB 0000H A 384# SMBFTE . . . . . . B ADDR 00C0H.1 A 286# SMBTOE . . . . . . B ADDR 00C0H.0 A 287# SP . . . . . . . . D ADDR 0081H A 43# SPI0CFG. . . . . . D ADDR 009AH A 85# SPI0CKR. . . . . . D ADDR 009DH A 90# SPI0CN . . . . . . D ADDR 00F8H A 197# A51 MACRO ASSEMBLER ADC2 04/26/2006 10:02:25 PAGE 13 SPI0DAT. . . . . . D ADDR 009BH A 87# SPI0_PAGE. . . . . N NUMB 0000H A 380# SPIEN. . . . . . . B ADDR 00F8H.0 A 367# SPIF . . . . . . . B ADDR 00F8H.7 A 360# SSTA0. . . . . . . D ADDR 0091H A 71# STA. . . . . . . . B ADDR 00C0H.5 A 282# STO. . . . . . . . B ADDR 00C0H.4 A 283# TB80 . . . . . . . B ADDR 0098H.3 A 248# TB81 . . . . . . . B ADDR 0098H.3 A 257# TCON . . . . . . . D ADDR 0088H A 53# TF0. . . . . . . . B ADDR 0088H.5 A 213# TF1. . . . . . . . B ADDR 0088H.7 A 211# TF2. . . . . . . . B ADDR 00C8H.7 A 296# TF3. . . . . . . . B ADDR 00C8H.7 A 304# TF4. . . . . . . . B ADDR 00C8H.7 A 312# TH0. . . . . . . . D ADDR 008CH A 63# TH1. . . . . . . . D ADDR 008DH A 64# TI0. . . . . . . . B ADDR 0098H.1 A 250# TI1. . . . . . . . B ADDR 0098H.1 A 259# TIMER01_PAGE . . . N NUMB 0000H A 375# TL0. . . . . . . . D ADDR 008AH A 59# TL1. . . . . . . . D ADDR 008BH A 61# TMOD . . . . . . . D ADDR 0089H A 54# TMR2CF . . . . . . D ADDR 00C9H A 140# TMR2CN . . . . . . D ADDR 00C8H A 137# TMR2H. . . . . . . D ADDR 00CDH A 152# TMR2L. . . . . . . D ADDR 00CCH A 149# TMR2_PAGE. . . . . N NUMB 0000H A 385# TMR3CF . . . . . . D ADDR 00C9H A 141# TMR3CN . . . . . . D ADDR 00C8H A 138# TMR3H. . . . . . . D ADDR 00CDH A 153# TMR3L. . . . . . . D ADDR 00CCH A 150# TMR3_PAGE. . . . . N NUMB 0001H A 386# TMR4CF . . . . . . D ADDR 00C9H A 142# TMR4CN . . . . . . D ADDR 00C8H A 139# TMR4H. . . . . . . D ADDR 00CDH A 154# TMR4L. . . . . . . D ADDR 00CCH A 151# TMR4_PAGE. . . . . N NUMB 0002H A 387# TR0. . . . . . . . B ADDR 0088H.4 A 214# TR1. . . . . . . . B ADDR 0088H.6 A 212# TR2. . . . . . . . B ADDR 00C8H.2 A 299# TR3. . . . . . . . B ADDR 00C8H.2 A 307# TR4. . . . . . . . B ADDR 00C8H.2 A 315# TXBMT. . . . . . . B ADDR 00F8H.1 A 366# UART0_PAGE . . . . N NUMB 0000H A 378# UART1_PAGE . . . . N NUMB 0001H A 379# WCOL . . . . . . . B ADDR 00F8H.6 A 361# WDTCN. . . . . . . D ADDR 00FFH A 204# XBR0 . . . . . . . D ADDR 00E1H A 176# XBR1 . . . . . . . D ADDR 00E2H A 179# XBR2 . . . . . . . D ADDR 00E3H A 180# 432 REGISTER BANK(S) USED: 0 ASSEMBLY COMPLETE. 0 WARNING(S), 0 ERROR(S)