A51 MACRO ASSEMBLER BLINK 04/24/2006 14:29:40 PAGE 1 MACRO ASSEMBLER A51 V7.04a OBJECT MODULE PLACED IN blink.OBJ ASSEMBLER INVOKED BY: F:\SiLabs\MCU\IDEfiles\C51\BIN\a51.exe blink.asm XR GEN DB EP NOMOD51 LOC OBJ LINE SOURCE 1 $nomod51 2 ;----------------------------------------------------------------------------- 3 ; Copyright (C) 2005 Silicon Laboratories, Inc. 4 ; All rights reserved. 5 ; 6 ; 7 ; 8 ; FILE NAME : BLINK.ASM 9 ; TARGET MCU : C8051F120/1/2/3/4/5/6/7 10 ; DESCRIPTION : This program illustrates how to disable the watchdog timer, 11 ; configure a port and write to a port I/O pin. 12 ; 13 ; NOTES: 14 ; 15 ;----------------------------------------------------------------------------- 16 17 ;$include (c8051f120.inc) ; Include register definition file. +1 18 ;--------------------------------------------------------------------------- +1 19 ; +1 20 ; +1 21 ; +1 22 ; +1 23 ; FILE NAME: C8051F120.INC +1 24 ; TARGET MCUs: C8051F120, F121, F122, F123, F124, F125, F126, F127 +1 25 ; DESCRIPTION: Register/bit definitions for the C8051F120 product family. +1 26 ; +1 27 ; REVISION 1.6 +1 28 ; +1 29 ;--------------------------------------------------------------------------- +1 30 +1 31 ;REGISTER DEFINITIONS +1 32 ; 0080 +1 33 P0 DATA 080H ; PORT 0 LATCH 0081 +1 34 SP DATA 081H ; STACK POINTER 0082 +1 35 DPL DATA 082H ; DATA POINTER LOW BYTE 0083 +1 36 DPH DATA 083H ; DATA POINTER HIGH BYTE 0084 +1 37 SFRPAGE DATA 084H ; SFR PAGE SELECT 0085 +1 38 SFRNEXT DATA 085H ; SFR STACK NEXT PAGE 0086 +1 39 SFRLAST DATA 086H ; SFR STACK LAST PAGE 0087 +1 40 PCON DATA 087H ; POWER CONTROL 0088 +1 41 FLSTAT DATA 088H ; FLASH STATUS 0088 +1 42 CPT0CN DATA 088H ; COMPARATOR 0 CONTROL 0088 +1 43 CPT1CN DATA 088H ; COMPARATOR 1 CONTROL 0088 +1 44 TCON DATA 088H ; TIMER/COUNTER CONTROL 0089 +1 45 TMOD DATA 089H ; TIMER/COUNTER MODE 0089 +1 46 CPT0MD DATA 089H ; COMPARATOR 0 CONFIGURATION 0089 +1 47 CPT1MD DATA 089H ; COMPARATOR 1 CONFIGURATION 0089 +1 48 PLL0CN DATA 089H ; PLL CONTROL 008A +1 49 OSCICN DATA 08AH ; INTERNAL OSCILLATOR CONTROL 008A +1 50 TL0 DATA 08AH ; TIMER/COUNTER 0 LOW BYTE 008B +1 51 OSCICL DATA 08BH ; INTERNAL OSCILLATOR CALIBRATION 008B +1 52 TL1 DATA 08BH ; TIMER/COUNTER 1 LOW BYTE 008C +1 53 OSCXCN DATA 08CH ; EXTERNAL OSCILLATOR CONTROL 008C +1 54 TH0 DATA 08CH ; TIMER/COUNTER 0 HIGH BYTE 008D +1 55 TH1 DATA 08DH ; TIMER/COUNTER 1 HIGH BYTE 008D +1 56 PLL0DIV DATA 08DH ; PLL DIVIDER 008E +1 57 CKCON DATA 08EH ; CLOCK CONTROL 008E +1 58 PLL0MUL DATA 08EH ; PLL MULTIPLIER A51 MACRO ASSEMBLER BLINK 04/24/2006 14:29:40 PAGE 2 008F +1 59 PSCTL DATA 08FH ; FLASH WRITE/ERASE CONTROL 008F +1 60 PLL0FLT DATA 08FH ; PLL FILTER 0090 +1 61 P1 DATA 090H ; PORT 1 LATCH 0091 +1 62 SSTA0 DATA 091H ; UART 0 STATUS 0091 +1 63 MAC0BL DATA 091H ; MAC0 B REGISTER LOW BYTE 0092 +1 64 MAC0BH DATA 092H ; MAC0 B REGISTER HIGH BYTE 0093 +1 65 MAC0ACC0 DATA 093H ; MAC0 ACCUMULATOR BYTE 0 0094 +1 66 MAC0ACC1 DATA 094H ; MAC0 ACCUMULATOR BYTE 1 0095 +1 67 MAC0ACC2 DATA 095H ; MAC0 ACCUMULATOR BYTE 2 0096 +1 68 SFRPGCN DATA 096H ; SFR PAGE CONTROL 0096 +1 69 MAC0ACC3 DATA 096H ; MAC0 ACCUMULATOR BYTE 3 0097 +1 70 MAC0OVR DATA 097H ; MAC0 ACCUMULATOR OVERFLOW BYTE 0097 +1 71 CLKSEL DATA 097H ; SYSTEM CLOCK SELECT 0098 +1 72 SCON0 DATA 098H ; UART 0 CONTROL 0098 +1 73 SCON1 DATA 098H ; UART 1 CONTROL 0099 +1 74 SBUF0 DATA 099H ; UART 0 DATA BUFFER 0099 +1 75 SBUF1 DATA 099H ; UART 1 DATA BUFFER 009A +1 76 SPI0CFG DATA 09AH ; SPI CONFIGURATION 009A +1 77 CCH0MA DATA 09AH ; CACHE MISS ACCUMULATOR 009B +1 78 SPI0DAT DATA 09BH ; SPI DATA 009C +1 79 P4MDOUT DATA 09CH ; PORT 4 OUTPUT MODE CONFIGURATION 009D +1 80 P5MDOUT DATA 09DH ; PORT 5 OUTPUT MODE CONFIGURATION 009D +1 81 SPI0CKR DATA 09DH ; SPI CLOCK RATE CONTROL 009E +1 82 P6MDOUT DATA 09EH ; PORT 6 OUTPUT MODE CONFIGURATION 009F +1 83 P7MDOUT DATA 09FH ; PORT 7 OUTPUT MODE CONFIGURATION 00A0 +1 84 P2 DATA 0A0H ; PORT 2 LATCH 00A1 +1 85 EMI0TC DATA 0A1H ; EMIF TIMING CONTROL 00A1 +1 86 CCH0CN DATA 0A1H ; CACHE CONTROL 00A2 +1 87 EMI0CN DATA 0A2H ; EMIF CONTROL 00A2 +1 88 CCH0TN DATA 0A2H ; CACHE TUNING 00A3 +1 89 EMI0CF DATA 0A3H ; EMIF CONFIGURATION 00A3 +1 90 CCH0LC DATA 0A3H ; CACHE LOCK 00A4 +1 91 P0MDOUT DATA 0A4H ; PORT 0 OUTPUT MODE CONFIGURATION 00A5 +1 92 P1MDOUT DATA 0A5H ; PORT 1 OUTPUT MODE CONFIGURATION 00A6 +1 93 P2MDOUT DATA 0A6H ; PORT 2 OUTPUT MODE CONFIGURATION 00A7 +1 94 P3MDOUT DATA 0A7H ; PORT 3 OUTPUT MODE CONFIGURATION 00A8 +1 95 IE DATA 0A8H ; INTERRUPT ENABLE 00A9 +1 96 SADDR0 DATA 0A9H ; UART 0 SLAVE ADDRESS 00AD +1 97 P1MDIN DATA 0ADH ; PORT 1 INPUT MODE 00B0 +1 98 P3 DATA 0B0H ; PORT 3 LATCH 00B1 +1 99 PSBANK DATA 0B1H ; FLASH BANK SELECT 00B7 +1 100 FLACL DATA 0B7H ; FLASH ACCESS LIMIT 00B7 +1 101 FLSCL DATA 0B7H ; FLASH SCALE 00B8 +1 102 IP DATA 0B8H ; INTERRUPT PRIORITY 00B9 +1 103 SADEN0 DATA 0B9H ; UART 0 SLAVE ADDRESS MASK 00BA +1 104 AMX0CF DATA 0BAH ; ADC0 MULTIPLEXER CONFIGURATION 00BA +1 105 AMX2CF DATA 0BAH ; ADC2 MULTIPLEXER CONFIGURATION 00BB +1 106 AMX0SL DATA 0BBH ; ADC0 MULTIPLEXER CHANNEL SELECT 00BB +1 107 AMX2SL DATA 0BBH ; ADC2 MULTIPLEXER CHANNEL SELECT 00BC +1 108 ADC0CF DATA 0BCH ; ADC0 CONFIGURATION 00BC +1 109 ADC2CF DATA 0BCH ; ADC2 CONFIGURATION 00BE +1 110 ADC0L DATA 0BEH ; ADC0 DATA WORD LOW BYTE 00BE +1 111 ADC2 DATA 0BEH ; ADC2DATA WORD 00BF +1 112 ADC0H DATA 0BFH ; ADC0 DATA WORD HIGH BYTE 00C0 +1 113 MAC0STA DATA 0C0H ; MAC0 STATUS 00C0 +1 114 SMB0CN DATA 0C0H ; SMBUS CONTROL 00C1 +1 115 MAC0AL DATA 0C1H ; MAC0 A REGISTER LOW BYTE 00C1 +1 116 SMB0STA DATA 0C1H ; SMBUS STATUS 00C2 +1 117 MAC0AH DATA 0C2H ; MAC0 A REGISTER HIGH BYTE 00C2 +1 118 SMB0DAT DATA 0C2H ; SMBUS DATA 00C3 +1 119 MAC0CF DATA 0C3H ; MAC0 CONFIGURATION REGISTER 00C3 +1 120 SMB0ADR DATA 0C3H ; SMBUS SLAVE ADDRESS 00C4 +1 121 ADC0GTL DATA 0C4H ; ADC0 GREATER-THAN LOW BYTE 00C4 +1 122 ADC2GT DATA 0C4H ; ADC2 GREATER-THAN 00C5 +1 123 ADC0GTH DATA 0C5H ; ADC0 GREATER-THAN HIGH BYTE 00C6 +1 124 ADC0LTL DATA 0C6H ; ADC0 LESS-THAN LOW BYTE A51 MACRO ASSEMBLER BLINK 04/24/2006 14:29:40 PAGE 3 00C6 +1 125 ADC2LT DATA 0C6H ; ADC2 LESS-THAN 00C7 +1 126 ADC0LTH DATA 0C7H ; ADC0 LESS-THAN HIGH BYTE 00C8 +1 127 P4 DATA 0C8H ; PORT 4 LATCH 00C8 +1 128 TMR2CN DATA 0C8H ; TIMER/COUNTER 2 CONTROL 00C8 +1 129 TMR3CN DATA 0C8H ; TIMER 3 CONTROL 00C8 +1 130 TMR4CN DATA 0C8H ; TIMER/COUNTER 4 CONTROL 00C9 +1 131 TMR2CF DATA 0C9H ; TIMER/COUNTER 2 CONFIGURATION 00C9 +1 132 TMR3CF DATA 0C9H ; TIMER 3 CONFIGURATION 00C9 +1 133 TMR4CF DATA 0C9H ; TIMER/COUNTER 4 CONFIGURATION 00CA +1 134 RCAP2L DATA 0CAH ; TIMER/COUNTER 2 CAPTURE/RELOAD LOW BYTE 00CA +1 135 RCAP3L DATA 0CAH ; TIMER 3 CAPTURE/RELOAD LOW BYTE 00CA +1 136 RCAP4L DATA 0CAH ; TIMER/COUNTER 4 CAPTURE/RELOAD LOW BYTE 00CB +1 137 RCAP2H DATA 0CBH ; TIMER/COUNTER 2 CAPTURE/RELOAD HIGH BYTE 00CB +1 138 RCAP3H DATA 0CBH ; TIMER 3 CAPTURE/RELOAD HIGH BYTE 00CB +1 139 RCAP4H DATA 0CBH ; TIMER/COUNTER 4 CAPTURE/RELOAD HIGH BYTE 00CC +1 140 TMR2L DATA 0CCH ; TIMER/COUNTER 2 LOW BYTE 00CC +1 141 TMR3L DATA 0CCH ; TIMER 3 LOW BYTE 00CC +1 142 TMR4L DATA 0CCH ; TIMER/COUNTER 4 LOW BYTE 00CD +1 143 TMR2H DATA 0CDH ; TIMER/COUNTER 2 HIGH BYTE 00CD +1 144 TMR3H DATA 0CDH ; TIMER 3 HIGH BYTE 00CD +1 145 TMR4H DATA 0CDH ; TIMER/COUNTER 4 HIGH BYTE 00CE +1 146 MAC0RNDL DATA 0CEH ; MAC0 ROUNDING REGISTER LOW BYTE 00CF +1 147 MAC0RNDH DATA 0CFH ; MAC0 ROUNDING REGISTER HIGH BYTE 00CF +1 148 SMB0CR DATA 0CFH ; SMBUS CLOCK RATE 00D0 +1 149 PSW DATA 0D0H ; PROGRAM STATUS WORD 00D1 +1 150 REF0CN DATA 0D1H ; VOLTAGE REFERENCE CONTROL 00D2 +1 151 DAC0L DATA 0D2H ; DAC0 LOW BYTE 00D2 +1 152 DAC1L DATA 0D2H ; DAC1 LOW BYTE 00D3 +1 153 DAC0H DATA 0D3H ; DAC0 HIGH BYTE 00D3 +1 154 DAC1H DATA 0D3H ; DAC1 HIGH BYTE 00D4 +1 155 DAC0CN DATA 0D4H ; DAC0 CONTROL 00D4 +1 156 DAC1CN DATA 0D4H ; DAC1 CONTROL 00D8 +1 157 P5 DATA 0D8H ; PORT 5 LATCH 00D8 +1 158 PCA0CN DATA 0D8H ; PCA CONTROL 00D9 +1 159 PCA0MD DATA 0D9H ; PCA MODE 00DA +1 160 PCA0CPM0 DATA 0DAH ; PCA MODULE 0 MODE 00DB +1 161 PCA0CPM1 DATA 0DBH ; PCA MODULE 1 MODE REGISTER 00DC +1 162 PCA0CPM2 DATA 0DCH ; PCA MODULE 2 MODE 00DD +1 163 PCA0CPM3 DATA 0DDH ; PCA MODULE 3 MODE 00DE +1 164 PCA0CPM4 DATA 0DEH ; PCA MODULE 4 MODE 00DF +1 165 PCA0CPM5 DATA 0DFH ; PCA MODULE 5 MODE 00E0 +1 166 ACC DATA 0E0H ; ACCUMULATOR 00E1 +1 167 XBR0 DATA 0E1H ; PORT I/O CROSSBAR CONTROL 0 00E1 +1 168 PCA0CPL5 DATA 0E1H ; PCA MODULE 5 CAPTURE/COMPARE LOW BYTE 00E2 +1 169 PCA0CPH5 DATA 0E2H ; PCA MODULE 5 CAPTURE/COMPARE HIGH BYTE 00E2 +1 170 XBR1 DATA 0E2H ; PORT I/O CROSSBAR CONTROL 1 00E3 +1 171 XBR2 DATA 0E3H ; PORT I/O CROSSBAR CONTROL 2 00E6 +1 172 EIE1 DATA 0E6H ; EXTENDED INTERRUPT ENABLE 1 00E7 +1 173 EIE2 DATA 0E7H ; EXTENDED INTERRUPT ENABLE 2 00E8 +1 174 ADC0CN DATA 0E8H ; ADC0 CONTROL 00E8 +1 175 ADC2CN DATA 0E8H ; ADC2 CONTROL 00E8 +1 176 P6 DATA 0E8H ; PORT 6 LATCH 00E9 +1 177 PCA0CPL2 DATA 0E9H ; PCA MODULE 2 CAPTURE/COMPARE LOW BYTE 00EA +1 178 PCA0CPH2 DATA 0EAH ; PCA MODULE 2 CAPTURE/COMPARE HIGH BYTE 00EB +1 179 PCA0CPL3 DATA 0EBH ; PCA MODULE 3 CAPTURE/COMPARE LOW BYTE 00EC +1 180 PCA0CPH3 DATA 0ECH ; PCA MODULE 3 CAPTURE/COMPARE HIGH BYTE 00ED +1 181 PCA0CPL4 DATA 0EDH ; PCA MODULE 4 CAPTURE/COMPARE LOW BYTE 00EE +1 182 PCA0CPH4 DATA 0EEH ; PCA MODULE 4 CAPTURE/COMPARE HIGH BYTE 00EF +1 183 RSTSRC DATA 0EFH ; RESET SOURCE 00F0 +1 184 B DATA 0F0H ; B REGISTER 00F6 +1 185 EIP1 DATA 0F6H ; EXTERNAL INTERRUPT PRIORITY 1 00F7 +1 186 EIP2 DATA 0F7H ; EXTERNAL INTERRUPT PRIORITY 2 00F8 +1 187 P7 DATA 0F8H ; PORT 7 LATCH 00F8 +1 188 SPI0CN DATA 0F8H ; SPI CONTROL 00F9 +1 189 PCA0L DATA 0F9H ; PCA COUNTER LOW BYTE 00FA +1 190 PCA0H DATA 0FAH ; PCA COUNTER HIGH BYTE A51 MACRO ASSEMBLER BLINK 04/24/2006 14:29:40 PAGE 4 00FB +1 191 PCA0CPL0 DATA 0FBH ; PCA MODULE 0 CAPTURE/COMPARE LOW BYTE 00FC +1 192 PCA0CPH0 DATA 0FCH ; PCA MODULE 0 CAPTURE/COMPARE HIGH BYTE 00FD +1 193 PCA0CPL1 DATA 0FDH ; PCA MODULE 1 CAPTURE/COMPARE LOW BYTE 00FE +1 194 PCA0CPH1 DATA 0FEH ; PCA MODULE 1 CAPTURE/COMPARE HIGH BYTE 00FF +1 195 WDTCN DATA 0FFH ; WATCHDOG TIMER CONTROL +1 196 +1 197 ; +1 198 ;------------------------------------------------------------------------------ +1 199 ;BIT DEFINITIONS +1 200 ; +1 201 ; TCON 088H 008F +1 202 TF1 BIT 08FH ; TIMER 1 OVERFLOW FLAG 008E +1 203 TR1 BIT 08EH ; TIMER 1 ON/OFF CONTROL 008D +1 204 TF0 BIT 08DH ; TIMER 0 OVERFLOW FLAG 008C +1 205 TR0 BIT 08CH ; TIMER 0 ON/OFF CONTROL 008B +1 206 IE1 BIT 08BH ; EXT. INTERRUPT 1 EDGE FLAG 008A +1 207 IT1 BIT 08AH ; EXT. INTERRUPT 1 TYPE 0089 +1 208 IE0 BIT 089H ; EXT. INTERRUPT 0 EDGE FLAG 0088 +1 209 IT0 BIT 088H ; EXT. INTERRUPT 0 TYPE +1 210 +1 211 ; CPT0CN 088H 008F +1 212 CP0EN BIT 08FH ; COMPARATOR 0 ENABLE 008E +1 213 CP0OUT BIT 08EH ; COMPARATOR 0 OUTPUT 008D +1 214 CP0RIF BIT 08DH ; COMPARATOR 0 RISING EDGE INTERRUPT 008C +1 215 CP0FIF BIT 08CH ; COMPARATOR 0 FALLING EDGE INTERRUPT 008B +1 216 CP0HYP1 BIT 08BH ; COMPARATOR 0 POSITIVE HYSTERISIS 1 008A +1 217 CP0HYP0 BIT 08AH ; COMPARATOR 0 POSITIVE HYSTERISIS 0 0089 +1 218 CP0HYN1 BIT 089H ; COMPARATOR 0 NEGATIVE HYSTERISIS 1 0088 +1 219 CP0HYN0 BIT 088H ; COMPARATOR 0 NEGATIVE HYSTERISIS 0 +1 220 +1 221 ; CPT1CN 088H 008F +1 222 CP1EN BIT 08FH ; COMPARATOR 1 ENABLE 008E +1 223 CP1OUT BIT 08EH ; COMPARATOR 1 OUTPUT 008D +1 224 CP1RIF BIT 08DH ; COMPARATOR 1 RISING EDGE INTERRUPT 008C +1 225 CP1FIF BIT 08CH ; COMPARATOR 1 FALLING EDGE INTERRUPT 008B +1 226 CP1HYP1 BIT 08BH ; COMPARATOR 1 POSITIVE HYSTERISIS 1 008A +1 227 CP1HYP0 BIT 08AH ; COMPARATOR 1 POSITIVE HYSTERISIS 0 0089 +1 228 CP1HYN1 BIT 089H ; COMPARATOR 1 NEGATIVE HYSTERISIS 1 0088 +1 229 CP1HYN0 BIT 088H ; COMPARATOR 1 NEGATIVE HYSTERISIS 0 +1 230 +1 231 ; FLSTAT 088H 0088 +1 232 FLHBUSY BIT 088H ; FLASH BUSY +1 233 +1 234 ; SCON0 098H 009F +1 235 SM00 BIT 09FH ; UART 0 MODE 0 009E +1 236 SM10 BIT 09EH ; UART 0 MODE 1 009D +1 237 SM20 BIT 09DH ; UART 0 MULTIPROCESSOR EN 009C +1 238 REN0 BIT 09CH ; UART 0 RX ENABLE 009B +1 239 TB80 BIT 09BH ; UART 0 TX BIT 8 009A +1 240 RB80 BIT 09AH ; UART 0 RX BIT 8 0099 +1 241 TI0 BIT 099H ; UART 0 TX INTERRUPT FLAG 0098 +1 242 RI0 BIT 098H ; UART 0 RX INTERRUPT FLAG +1 243 +1 244 ; SCON1 098H 009F +1 245 S1MODE BIT 09FH ; UART 1 MODE 009D +1 246 MCE1 BIT 09DH ; UART 1 MCE 009C +1 247 REN1 BIT 09CH ; UART 1 RX ENABLE 009B +1 248 TB81 BIT 09BH ; UART 1 TX BIT 8 009A +1 249 RB81 BIT 09AH ; UART 1 RX BIT 8 0099 +1 250 TI1 BIT 099H ; UART 1 TX INTERRUPT FLAG 0098 +1 251 RI1 BIT 098H ; UART 1 RX INTERRUPT FLAG +1 252 +1 253 ; IE 0A8H 00AF +1 254 EA BIT 0AFH ; GLOBAL INTERRUPT ENABLE 00AD +1 255 ET2 BIT 0ADH ; TIMER 2 INTERRUPT ENABLE 00AC +1 256 ES0 BIT 0ACH ; UART0 INTERRUPT ENABLE A51 MACRO ASSEMBLER BLINK 04/24/2006 14:29:40 PAGE 5 00AB +1 257 ET1 BIT 0ABH ; TIMER 1 INTERRUPT ENABLE 00AA +1 258 EX1 BIT 0AAH ; EXTERNAL INTERRUPT 1 ENABLE 00A9 +1 259 ET0 BIT 0A9H ; TIMER 0 INTERRUPT ENABLE 00A8 +1 260 EX0 BIT 0A8H ; EXTERNAL INTERRUPT 0 ENABLE +1 261 +1 262 ; IP 0B8H 00BD +1 263 PT2 BIT 0BDH ; TIMER 2 PRIORITY 00BC +1 264 PS BIT 0BCH ; SERIAL PORT PRIORITY 00BB +1 265 PT1 BIT 0BBH ; TIMER 1 PRIORITY 00BA +1 266 PX1 BIT 0BAH ; EXTERNAL INTERRUPT 1 PRIORITY 00B9 +1 267 PT0 BIT 0B9H ; TIMER 0 PRIORITY 00B8 +1 268 PX0 BIT 0B8H ; EXTERNAL INTERRUPT 0 PRIORITY +1 269 +1 270 ; SMB0CN 0C0H 00C7 +1 271 BUSY BIT 0C7H ; SMBUS 0 BUSY 00C6 +1 272 ENSMB BIT 0C6H ; SMBUS 0 ENABLE 00C5 +1 273 STA BIT 0C5H ; SMBUS 0 START FLAG 00C4 +1 274 STO BIT 0C4H ; SMBUS 0 STOP FLAG 00C3 +1 275 SI BIT 0C3H ; SMBUS 0 INTERRUPT PENDING FLAG 00C2 +1 276 AA BIT 0C2H ; SMBUS 0 ASSERT/ACKNOWLEDGE FLAG 00C1 +1 277 SMBFTE BIT 0C1H ; SMBUS 0 FREE TIMER ENABLE 00C0 +1 278 SMBTOE BIT 0C0H ; SMBUS 0 TIMEOUT ENABLE +1 279 +1 280 ; MAC0STA 0C0H 00C3 +1 281 MAC0HO BIT 0C3H ; MAC0 HARD OVERFLOW 00C2 +1 282 MAC0Z BIT 0C2H ; MAC0 ZERO 00C1 +1 283 MAC0SO BIT 0C1H ; MAC0 SOFT OVERFLOW 00C0 +1 284 MAC0N BIT 0C0H ; MAC0 NEGATIVE +1 285 +1 286 ; TMR2CN 0C8H 00CF +1 287 TF2 BIT 0CFH ; TIMER 2 OVERFLOW FLAG 00CE +1 288 EXF2 BIT 0CEH ; TIMER 2 EXTERNAL FLAG 00CB +1 289 EXEN2 BIT 0CBH ; TIMER 2 EXTERNAL ENABLE FLAG 00CA +1 290 TR2 BIT 0CAH ; TIMER 2 ON/OFF CONTROL 00C9 +1 291 CT2 BIT 0C9H ; TIMER 2 COUNTER SELECT 00C8 +1 292 CPRL2 BIT 0C8H ; TIMER 2 CAPTURE SELECT +1 293 +1 294 ; TMR3CN 0C8H 00CF +1 295 TF3 BIT 0CFH ; TIMER 3 OVERFLOW FLAG 00CE +1 296 EXF3 BIT 0CEH ; TIMER 3 EXTERNAL FLAG 00CB +1 297 EXEN3 BIT 0CBH ; TIMER 3 EXTERNAL ENABLE FLAG 00CA +1 298 TR3 BIT 0CAH ; TIMER 3 ON/OFF CONTROL 00C9 +1 299 CT3 BIT 0C9H ; TIMER 3 COUNTER SELECT 00C8 +1 300 CPRL3 BIT 0C8H ; TIMER 3 CAPTURE SELECT +1 301 +1 302 ; TMR4CN 0C8H 00CF +1 303 TF4 BIT 0CFH ; TIMER 4 OVERFLOW FLAG 00CE +1 304 EXF4 BIT 0CEH ; TIMER 4 EXTERNAL FLAG 00CB +1 305 EXEN4 BIT 0CBH ; TIMER 4 EXTERNAL ENABLE FLAG 00CA +1 306 TR4 BIT 0CAH ; TIMER 4 ON/OFF CONTROL 00C9 +1 307 CT4 BIT 0C9H ; TIMER 4 COUNTER SELECT 00C8 +1 308 CPRL4 BIT 0C8H ; TIMER 4 CAPTURE SELECT +1 309 +1 310 ; PSW 0D0H 00D7 +1 311 CY BIT 0D7H ; CARRY FLAG 00D6 +1 312 AC BIT 0D6H ; AUXILIARY CARRY FLAG 00D5 +1 313 F0 BIT 0D5H ; USER FLAG 0 00D4 +1 314 RS1 BIT 0D4H ; REGISTER BANK SELECT 1 00D3 +1 315 RS0 BIT 0D3H ; REGISTER BANK SELECT 0 00D2 +1 316 OV BIT 0D2H ; OVERFLOW FLAG 00D1 +1 317 F1 BIT 0D1H ; USER FLAG 1 00D0 +1 318 P BIT 0D0H ; ACCUMULATOR PARITY FLAG +1 319 +1 320 ; PCA0CN 0D8H 00DF +1 321 CF BIT 0DFH ; PCA 0 COUNTER OVERFLOW FLAG 00DE +1 322 CR BIT 0DEH ; PCA 0 COUNTER RUN CONTROL BIT A51 MACRO ASSEMBLER BLINK 04/24/2006 14:29:40 PAGE 6 00DD +1 323 CCF5 BIT 0DDH ; PCA 0 MODULE 5 INTERRUPT FLAG 00DC +1 324 CCF4 BIT 0DCH ; PCA 0 MODULE 4 INTERRUPT FLAG 00DB +1 325 CCF3 BIT 0DBH ; PCA 0 MODULE 3 INTERRUPT FLAG 00DA +1 326 CCF2 BIT 0DAH ; PCA 0 MODULE 2 INTERRUPT FLAG 00D9 +1 327 CCF1 BIT 0D9H ; PCA 0 MODULE 1 INTERRUPT FLAG 00D8 +1 328 CCF0 BIT 0D8H ; PCA 0 MODULE 0 INTERRUPT FLAG +1 329 +1 330 ; ADC0CN 0E8H 00EF +1 331 AD0EN BIT 0EFH ; ADC 0 ENABLE 00EE +1 332 AD0TM BIT 0EEH ; ADC 0 TRACK MODE 00ED +1 333 AD0INT BIT 0EDH ; ADC 0 EOC INTERRUPT FLAG 00EC +1 334 AD0BUSY BIT 0ECH ; ADC 0 BUSY FLAG 00EB +1 335 AD0CM1 BIT 0EBH ; ADC 0 CONVERT START MODE BIT 1 00EA +1 336 AD0CM0 BIT 0EAH ; ADC 0 CONVERT START MODE BIT 0 00E9 +1 337 AD0WINT BIT 0E9H ; ADC 0 WINDOW INTERRUPT FLAG 00E8 +1 338 AD0LJST BIT 0E8H ; ADC 0 LEFT JUSTIFY DATA BIT +1 339 +1 340 ; ADC2CN 0E8H 00EF +1 341 AD2EN BIT 0EFH ; ADC 2 ENABLE 00EE +1 342 AD2TM BIT 0EEH ; ADC 2 TRACK MODE 00ED +1 343 AD2INT BIT 0EDH ; ADC 2 EOC INTERRUPT FLAG 00EC +1 344 AD2BUSY BIT 0ECH ; ADC 2 BUSY FLAG 00EB +1 345 AD2CM2 BIT 0EBH ; ADC 2 CONVERT START MODE BIT 2 00EA +1 346 AD2CM1 BIT 0EAH ; ADC 2 CONVERT START MODE BIT 1 00E9 +1 347 AD2CM0 BIT 0E9H ; ADC 2 CONVERT START MODE BIT 0 00E8 +1 348 AD2WINT BIT 0E8H ; ADC 2 WINDOW INTERRUPT FLAG +1 349 +1 350 ; SPI0CN 0F8H 00FF +1 351 SPIF BIT 0FFH ; SPI 0 INTERRUPT FLAG 00FE +1 352 WCOL BIT 0FEH ; SPI 0 WRITE COLLISION FLAG 00FD +1 353 MODF BIT 0FDH ; SPI 0 MODE FAULT FLAG 00FC +1 354 RXOVRN BIT 0FCH ; SPI 0 RX OVERRUN FLAG 00FB +1 355 NSSMD1 BIT 0FBH ; SPI 0 SLAVE SELECT MODE 1 00FA +1 356 NSSMD0 BIT 0FAH ; SPI 0 SLAVE SELECT MODE 0 00F9 +1 357 TXBMT BIT 0F9H ; SPI 0 TX BUFFER EMPTY FLAG 00F8 +1 358 SPIEN BIT 0F8H ; SPI 0 SPI ENABLE +1 359 +1 360 ; +1 361 ;------------------------------------------------------------------------------ +1 362 ; SFR PAGE DEFINITIONS +1 363 ; 000F +1 364 CONFIG_PAGE EQU 0FH ; SYSTEM AND PORT CONFIGURATION PAGE 0000 +1 365 LEGACY_PAGE EQU 00H ; LEGACY SFR PAGE 0000 +1 366 TIMER01_PAGE EQU 00H ; TIMER 0 AND TIMER 1 0001 +1 367 CPT0_PAGE EQU 01H ; COMPARATOR 0 0002 +1 368 CPT1_PAGE EQU 02H ; COMPARATOR 1 0000 +1 369 UART0_PAGE EQU 00H ; UART 0 0001 +1 370 UART1_PAGE EQU 01H ; UART 1 0000 +1 371 SPI0_PAGE EQU 00H ; SPI 0 0000 +1 372 EMI0_PAGE EQU 00H ; EXTERNAL MEMORY INTERFACE 0000 +1 373 ADC0_PAGE EQU 00H ; ADC 0 0002 +1 374 ADC2_PAGE EQU 02H ; ADC 2 0000 +1 375 SMB0_PAGE EQU 00H ; SMBUS 0 0000 +1 376 TMR2_PAGE EQU 00H ; TIMER 2 0001 +1 377 TMR3_PAGE EQU 01H ; TIMER 3 0002 +1 378 TMR4_PAGE EQU 02H ; TIMER 4 0000 +1 379 DAC0_PAGE EQU 00H ; DAC 0 0001 +1 380 DAC1_PAGE EQU 01H ; DAC 1 0000 +1 381 PCA0_PAGE EQU 00H ; PCA 0 000F +1 382 PLL0_PAGE EQU 0FH ; PLL 0 0003 +1 383 MAC0_PAGE EQU 03H ; MAC 0 384 385 ;----------------------------------------------------------------------------- 386 ; EQUATES 387 ;----------------------------------------------------------------------------- 388 A51 MACRO ASSEMBLER BLINK 04/24/2006 14:29:40 PAGE 7 0096 389 GREEN_LED equ P1.6 ; Port I/O pin connected to Green LED. 390 391 ;----------------------------------------------------------------------------- 392 ; RESET and INTERRUPT VECTORS 393 ;----------------------------------------------------------------------------- 394 395 ; Reset Vector ---- 396 cseg AT 0 0000 020000 F 397 ljmp Main ; Locate a jump to the start of code at 398 ; the reset vector. 399 400 ;----------------------------------------------------------------------------- 401 ; CODE SEGMENT 402 ;----------------------------------------------------------------------------- 403 404 405 Blink segment CODE 406 ---- 407 rseg Blink ; Switch to this code segment. 408 using 0 ; Specify register bank for the following 409 ; program code. 410 0000 411 Main: ; Disable the WDT. (IRQs not enabled at this point.) 412 ; If interrupts were enabled, we would need to explicitly disable 413 ; them so that the 2nd move to WDTCN occurs no more than four clock 414 ; cycles after the first move to WDTCN. 415 0000 75FFDE 416 mov WDTCN, #0DEh 0003 75FFAD 417 mov WDTCN, #0ADh 418 419 ; Use SFRs on the Configuration Page 0006 75840F 420 mov SFRPAGE, #CONFIG_PAGE 421 422 ; Enable the Port I/O Crossbar 0009 75E340 423 mov XBR2, #40h 424 425 ; Set P1.6 (LED) as digital output in push-pull mode. 000C 43A540 426 orl P1MDOUT,#40h 427 428 ; Initialize LED to OFF 000F C296 429 clr GREEN_LED 430 431 ; Simple delay loop. 0011 7F03 432 Loop2: mov R7, #03h 0013 7E00 433 Loop1: mov R6, #00h 0015 7D00 434 Loop0: mov R5, #00h 0017 DDFE 435 djnz R5, $ 0019 DEFA 436 djnz R6, Loop0 001B DFF6 437 djnz R7, Loop1 001D B296 438 cpl GREEN_LED ; Toggle LED. 001F 80F0 439 jmp Loop2 440 441 442 ;----------------------------------------------------------------------------- 443 ; End of file. 444 445 END A51 MACRO ASSEMBLER BLINK 04/24/2006 14:29:40 PAGE 8 XREF SYMBOL TABLE LISTING ---- ------ ----- ------- N A M E T Y P E V A L U E ATTRIBUTES / REFERENCES AA . . . . . . . . B ADDR 00C0H.2 A 276# AC . . . . . . . . B ADDR 00D0H.6 A 312# ACC. . . . . . . . D ADDR 00E0H A 166# AD0BUSY. . . . . . B ADDR 00E8H.4 A 334# AD0CM0 . . . . . . B ADDR 00E8H.2 A 336# AD0CM1 . . . . . . B ADDR 00E8H.3 A 335# AD0EN. . . . . . . B ADDR 00E8H.7 A 331# AD0INT . . . . . . B ADDR 00E8H.5 A 333# AD0LJST. . . . . . B ADDR 00E8H.0 A 338# AD0TM. . . . . . . B ADDR 00E8H.6 A 332# AD0WINT. . . . . . B ADDR 00E8H.1 A 337# AD2BUSY. . . . . . B ADDR 00E8H.4 A 344# AD2CM0 . . . . . . B ADDR 00E8H.1 A 347# AD2CM1 . . . . . . B ADDR 00E8H.2 A 346# AD2CM2 . . . . . . B ADDR 00E8H.3 A 345# AD2EN. . . . . . . B ADDR 00E8H.7 A 341# AD2INT . . . . . . B ADDR 00E8H.5 A 343# AD2TM. . . . . . . B ADDR 00E8H.6 A 342# AD2WINT. . . . . . B ADDR 00E8H.0 A 348# ADC0CF . . . . . . D ADDR 00BCH A 108# ADC0CN . . . . . . D ADDR 00E8H A 174# ADC0GTH. . . . . . D ADDR 00C5H A 123# ADC0GTL. . . . . . D ADDR 00C4H A 121# ADC0H. . . . . . . D ADDR 00BFH A 112# ADC0L. . . . . . . D ADDR 00BEH A 110# ADC0LTH. . . . . . D ADDR 00C7H A 126# ADC0LTL. . . . . . D ADDR 00C6H A 124# ADC0_PAGE. . . . . N NUMB 0000H A 373# ADC2 . . . . . . . D ADDR 00BEH A 111# ADC2CF . . . . . . D ADDR 00BCH A 109# ADC2CN . . . . . . D ADDR 00E8H A 175# ADC2GT . . . . . . D ADDR 00C4H A 122# ADC2LT . . . . . . D ADDR 00C6H A 125# ADC2_PAGE. . . . . N NUMB 0002H A 374# AMX0CF . . . . . . D ADDR 00BAH A 104# AMX0SL . . . . . . D ADDR 00BBH A 106# AMX2CF . . . . . . D ADDR 00BAH A 105# AMX2SL . . . . . . D ADDR 00BBH A 107# B. . . . . . . . . D ADDR 00F0H A 184# BLINK. . . . . . . C SEG 0021H REL=UNIT 405# 407 BUSY . . . . . . . B ADDR 00C0H.7 A 271# CCF0 . . . . . . . B ADDR 00D8H.0 A 328# CCF1 . . . . . . . B ADDR 00D8H.1 A 327# CCF2 . . . . . . . B ADDR 00D8H.2 A 326# CCF3 . . . . . . . B ADDR 00D8H.3 A 325# CCF4 . . . . . . . B ADDR 00D8H.4 A 324# CCF5 . . . . . . . B ADDR 00D8H.5 A 323# CCH0CN . . . . . . D ADDR 00A1H A 86# CCH0LC . . . . . . D ADDR 00A3H A 90# CCH0MA . . . . . . D ADDR 009AH A 77# CCH0TN . . . . . . D ADDR 00A2H A 88# CF . . . . . . . . B ADDR 00D8H.7 A 321# CKCON. . . . . . . D ADDR 008EH A 57# CLKSEL . . . . . . D ADDR 0097H A 71# CONFIG_PAGE. . . . N NUMB 000FH A 364# 420 CP0EN. . . . . . . B ADDR 0088H.7 A 212# CP0FIF . . . . . . B ADDR 0088H.4 A 215# CP0HYN0. . . . . . B ADDR 0088H.0 A 219# CP0HYN1. . . . . . B ADDR 0088H.1 A 218# CP0HYP0. . . . . . B ADDR 0088H.2 A 217# A51 MACRO ASSEMBLER BLINK 04/24/2006 14:29:40 PAGE 9 CP0HYP1. . . . . . B ADDR 0088H.3 A 216# CP0OUT . . . . . . B ADDR 0088H.6 A 213# CP0RIF . . . . . . B ADDR 0088H.5 A 214# CP1EN. . . . . . . B ADDR 0088H.7 A 222# CP1FIF . . . . . . B ADDR 0088H.4 A 225# CP1HYN0. . . . . . B ADDR 0088H.0 A 229# CP1HYN1. . . . . . B ADDR 0088H.1 A 228# CP1HYP0. . . . . . B ADDR 0088H.2 A 227# CP1HYP1. . . . . . B ADDR 0088H.3 A 226# CP1OUT . . . . . . B ADDR 0088H.6 A 223# CP1RIF . . . . . . B ADDR 0088H.5 A 224# CPRL2. . . . . . . B ADDR 00C8H.0 A 292# CPRL3. . . . . . . B ADDR 00C8H.0 A 300# CPRL4. . . . . . . B ADDR 00C8H.0 A 308# CPT0CN . . . . . . D ADDR 0088H A 42# CPT0MD . . . . . . D ADDR 0089H A 46# CPT0_PAGE. . . . . N NUMB 0001H A 367# CPT1CN . . . . . . D ADDR 0088H A 43# CPT1MD . . . . . . D ADDR 0089H A 47# CPT1_PAGE. . . . . N NUMB 0002H A 368# CR . . . . . . . . B ADDR 00D8H.6 A 322# CT2. . . . . . . . B ADDR 00C8H.1 A 291# CT3. . . . . . . . B ADDR 00C8H.1 A 299# CT4. . . . . . . . B ADDR 00C8H.1 A 307# CY . . . . . . . . B ADDR 00D0H.7 A 311# DAC0CN . . . . . . D ADDR 00D4H A 155# DAC0H. . . . . . . D ADDR 00D3H A 153# DAC0L. . . . . . . D ADDR 00D2H A 151# DAC0_PAGE. . . . . N NUMB 0000H A 379# DAC1CN . . . . . . D ADDR 00D4H A 156# DAC1H. . . . . . . D ADDR 00D3H A 154# DAC1L. . . . . . . D ADDR 00D2H A 152# DAC1_PAGE. . . . . N NUMB 0001H A 380# DPH. . . . . . . . D ADDR 0083H A 36# DPL. . . . . . . . D ADDR 0082H A 35# EA . . . . . . . . B ADDR 00A8H.7 A 254# EIE1 . . . . . . . D ADDR 00E6H A 172# EIE2 . . . . . . . D ADDR 00E7H A 173# EIP1 . . . . . . . D ADDR 00F6H A 185# EIP2 . . . . . . . D ADDR 00F7H A 186# EMI0CF . . . . . . D ADDR 00A3H A 89# EMI0CN . . . . . . D ADDR 00A2H A 87# EMI0TC . . . . . . D ADDR 00A1H A 85# EMI0_PAGE. . . . . N NUMB 0000H A 372# ENSMB. . . . . . . B ADDR 00C0H.6 A 272# ES0. . . . . . . . B ADDR 00A8H.4 A 256# ET0. . . . . . . . B ADDR 00A8H.1 A 259# ET1. . . . . . . . B ADDR 00A8H.3 A 257# ET2. . . . . . . . B ADDR 00A8H.5 A 255# EX0. . . . . . . . B ADDR 00A8H.0 A 260# EX1. . . . . . . . B ADDR 00A8H.2 A 258# EXEN2. . . . . . . B ADDR 00C8H.3 A 289# EXEN3. . . . . . . B ADDR 00C8H.3 A 297# EXEN4. . . . . . . B ADDR 00C8H.3 A 305# EXF2 . . . . . . . B ADDR 00C8H.6 A 288# EXF3 . . . . . . . B ADDR 00C8H.6 A 296# EXF4 . . . . . . . B ADDR 00C8H.6 A 304# F0 . . . . . . . . B ADDR 00D0H.5 A 313# F1 . . . . . . . . B ADDR 00D0H.1 A 317# FLACL. . . . . . . D ADDR 00B7H A 100# FLHBUSY. . . . . . B ADDR 0088H.0 A 232# FLSCL. . . . . . . D ADDR 00B7H A 101# FLSTAT . . . . . . D ADDR 0088H A 41# GREEN_LED. . . . . B ADDR 0090H.6 A 389# 429 438 IE . . . . . . . . D ADDR 00A8H A 95# IE0. . . . . . . . B ADDR 0088H.1 A 208# A51 MACRO ASSEMBLER BLINK 04/24/2006 14:29:40 PAGE 10 IE1. . . . . . . . B ADDR 0088H.3 A 206# IP . . . . . . . . D ADDR 00B8H A 102# IT0. . . . . . . . B ADDR 0088H.0 A 209# IT1. . . . . . . . B ADDR 0088H.2 A 207# LEGACY_PAGE. . . . N NUMB 0000H A 365# LOOP0. . . . . . . C ADDR 0015H R SEG=BLINK 434# 436 LOOP1. . . . . . . C ADDR 0013H R SEG=BLINK 433# 437 LOOP2. . . . . . . C ADDR 0011H R SEG=BLINK 432# 439 MAC0ACC0 . . . . . D ADDR 0093H A 65# MAC0ACC1 . . . . . D ADDR 0094H A 66# MAC0ACC2 . . . . . D ADDR 0095H A 67# MAC0ACC3 . . . . . D ADDR 0096H A 69# MAC0AH . . . . . . D ADDR 00C2H A 117# MAC0AL . . . . . . D ADDR 00C1H A 115# MAC0BH . . . . . . D ADDR 0092H A 64# MAC0BL . . . . . . D ADDR 0091H A 63# MAC0CF . . . . . . D ADDR 00C3H A 119# MAC0HO . . . . . . B ADDR 00C0H.3 A 281# MAC0N. . . . . . . B ADDR 00C0H.0 A 284# MAC0OVR. . . . . . D ADDR 0097H A 70# MAC0RNDH . . . . . D ADDR 00CFH A 147# MAC0RNDL . . . . . D ADDR 00CEH A 146# MAC0SO . . . . . . B ADDR 00C0H.1 A 283# MAC0STA. . . . . . D ADDR 00C0H A 113# MAC0Z. . . . . . . B ADDR 00C0H.2 A 282# MAC0_PAGE. . . . . N NUMB 0003H A 383# MAIN . . . . . . . C ADDR 0000H R SEG=BLINK 397 411# MCE1 . . . . . . . B ADDR 0098H.5 A 246# MODF . . . . . . . B ADDR 00F8H.5 A 353# NSSMD0 . . . . . . B ADDR 00F8H.2 A 356# NSSMD1 . . . . . . B ADDR 00F8H.3 A 355# OSCICL . . . . . . D ADDR 008BH A 51# OSCICN . . . . . . D ADDR 008AH A 49# OSCXCN . . . . . . D ADDR 008CH A 53# OV . . . . . . . . B ADDR 00D0H.2 A 316# P. . . . . . . . . B ADDR 00D0H.0 A 318# P0 . . . . . . . . D ADDR 0080H A 33# P0MDOUT. . . . . . D ADDR 00A4H A 91# P1 . . . . . . . . D ADDR 0090H A 61# 389 P1MDIN . . . . . . D ADDR 00ADH A 97# P1MDOUT. . . . . . D ADDR 00A5H A 92# 426 P2 . . . . . . . . D ADDR 00A0H A 84# P2MDOUT. . . . . . D ADDR 00A6H A 93# P3 . . . . . . . . D ADDR 00B0H A 98# P3MDOUT. . . . . . D ADDR 00A7H A 94# P4 . . . . . . . . D ADDR 00C8H A 127# P4MDOUT. . . . . . D ADDR 009CH A 79# P5 . . . . . . . . D ADDR 00D8H A 157# P5MDOUT. . . . . . D ADDR 009DH A 80# P6 . . . . . . . . D ADDR 00E8H A 176# P6MDOUT. . . . . . D ADDR 009EH A 82# P7 . . . . . . . . D ADDR 00F8H A 187# P7MDOUT. . . . . . D ADDR 009FH A 83# PCA0CN . . . . . . D ADDR 00D8H A 158# PCA0CPH0 . . . . . D ADDR 00FCH A 192# PCA0CPH1 . . . . . D ADDR 00FEH A 194# PCA0CPH2 . . . . . D ADDR 00EAH A 178# PCA0CPH3 . . . . . D ADDR 00ECH A 180# PCA0CPH4 . . . . . D ADDR 00EEH A 182# PCA0CPH5 . . . . . D ADDR 00E2H A 169# PCA0CPL0 . . . . . D ADDR 00FBH A 191# PCA0CPL1 . . . . . D ADDR 00FDH A 193# PCA0CPL2 . . . . . D ADDR 00E9H A 177# PCA0CPL3 . . . . . D ADDR 00EBH A 179# PCA0CPL4 . . . . . D ADDR 00EDH A 181# PCA0CPL5 . . . . . D ADDR 00E1H A 168# A51 MACRO ASSEMBLER BLINK 04/24/2006 14:29:40 PAGE 11 PCA0CPM0 . . . . . D ADDR 00DAH A 160# PCA0CPM1 . . . . . D ADDR 00DBH A 161# PCA0CPM2 . . . . . D ADDR 00DCH A 162# PCA0CPM3 . . . . . D ADDR 00DDH A 163# PCA0CPM4 . . . . . D ADDR 00DEH A 164# PCA0CPM5 . . . . . D ADDR 00DFH A 165# PCA0H. . . . . . . D ADDR 00FAH A 190# PCA0L. . . . . . . D ADDR 00F9H A 189# PCA0MD . . . . . . D ADDR 00D9H A 159# PCA0_PAGE. . . . . N NUMB 0000H A 381# PCON . . . . . . . D ADDR 0087H A 40# PLL0CN . . . . . . D ADDR 0089H A 48# PLL0DIV. . . . . . D ADDR 008DH A 56# PLL0FLT. . . . . . D ADDR 008FH A 60# PLL0MUL. . . . . . D ADDR 008EH A 58# PLL0_PAGE. . . . . N NUMB 000FH A 382# PS . . . . . . . . B ADDR 00B8H.4 A 264# PSBANK . . . . . . D ADDR 00B1H A 99# PSCTL. . . . . . . D ADDR 008FH A 59# PSW. . . . . . . . D ADDR 00D0H A 149# PT0. . . . . . . . B ADDR 00B8H.1 A 267# PT1. . . . . . . . B ADDR 00B8H.3 A 265# PT2. . . . . . . . B ADDR 00B8H.5 A 263# PX0. . . . . . . . B ADDR 00B8H.0 A 268# PX1. . . . . . . . B ADDR 00B8H.2 A 266# RB80 . . . . . . . B ADDR 0098H.2 A 240# RB81 . . . . . . . B ADDR 0098H.2 A 249# RCAP2H . . . . . . D ADDR 00CBH A 137# RCAP2L . . . . . . D ADDR 00CAH A 134# RCAP3H . . . . . . D ADDR 00CBH A 138# RCAP3L . . . . . . D ADDR 00CAH A 135# RCAP4H . . . . . . D ADDR 00CBH A 139# RCAP4L . . . . . . D ADDR 00CAH A 136# REF0CN . . . . . . D ADDR 00D1H A 150# REN0 . . . . . . . B ADDR 0098H.4 A 238# REN1 . . . . . . . B ADDR 0098H.4 A 247# RI0. . . . . . . . B ADDR 0098H.0 A 242# RI1. . . . . . . . B ADDR 0098H.0 A 251# RS0. . . . . . . . B ADDR 00D0H.3 A 315# RS1. . . . . . . . B ADDR 00D0H.4 A 314# RSTSRC . . . . . . D ADDR 00EFH A 183# RXOVRN . . . . . . B ADDR 00F8H.4 A 354# S1MODE . . . . . . B ADDR 0098H.7 A 245# SADDR0 . . . . . . D ADDR 00A9H A 96# SADEN0 . . . . . . D ADDR 00B9H A 103# SBUF0. . . . . . . D ADDR 0099H A 74# SBUF1. . . . . . . D ADDR 0099H A 75# SCON0. . . . . . . D ADDR 0098H A 72# SCON1. . . . . . . D ADDR 0098H A 73# SFRLAST. . . . . . D ADDR 0086H A 39# SFRNEXT. . . . . . D ADDR 0085H A 38# SFRPAGE. . . . . . D ADDR 0084H A 37# 420 SFRPGCN. . . . . . D ADDR 0096H A 68# SI . . . . . . . . B ADDR 00C0H.3 A 275# SM00 . . . . . . . B ADDR 0098H.7 A 235# SM10 . . . . . . . B ADDR 0098H.6 A 236# SM20 . . . . . . . B ADDR 0098H.5 A 237# SMB0ADR. . . . . . D ADDR 00C3H A 120# SMB0CN . . . . . . D ADDR 00C0H A 114# SMB0CR . . . . . . D ADDR 00CFH A 148# SMB0DAT. . . . . . D ADDR 00C2H A 118# SMB0STA. . . . . . D ADDR 00C1H A 116# SMB0_PAGE. . . . . N NUMB 0000H A 375# SMBFTE . . . . . . B ADDR 00C0H.1 A 277# SMBTOE . . . . . . B ADDR 00C0H.0 A 278# SP . . . . . . . . D ADDR 0081H A 34# A51 MACRO ASSEMBLER BLINK 04/24/2006 14:29:40 PAGE 12 SPI0CFG. . . . . . D ADDR 009AH A 76# SPI0CKR. . . . . . D ADDR 009DH A 81# SPI0CN . . . . . . D ADDR 00F8H A 188# SPI0DAT. . . . . . D ADDR 009BH A 78# SPI0_PAGE. . . . . N NUMB 0000H A 371# SPIEN. . . . . . . B ADDR 00F8H.0 A 358# SPIF . . . . . . . B ADDR 00F8H.7 A 351# SSTA0. . . . . . . D ADDR 0091H A 62# STA. . . . . . . . B ADDR 00C0H.5 A 273# STO. . . . . . . . B ADDR 00C0H.4 A 274# TB80 . . . . . . . B ADDR 0098H.3 A 239# TB81 . . . . . . . B ADDR 0098H.3 A 248# TCON . . . . . . . D ADDR 0088H A 44# TF0. . . . . . . . B ADDR 0088H.5 A 204# TF1. . . . . . . . B ADDR 0088H.7 A 202# TF2. . . . . . . . B ADDR 00C8H.7 A 287# TF3. . . . . . . . B ADDR 00C8H.7 A 295# TF4. . . . . . . . B ADDR 00C8H.7 A 303# TH0. . . . . . . . D ADDR 008CH A 54# TH1. . . . . . . . D ADDR 008DH A 55# TI0. . . . . . . . B ADDR 0098H.1 A 241# TI1. . . . . . . . B ADDR 0098H.1 A 250# TIMER01_PAGE . . . N NUMB 0000H A 366# TL0. . . . . . . . D ADDR 008AH A 50# TL1. . . . . . . . D ADDR 008BH A 52# TMOD . . . . . . . D ADDR 0089H A 45# TMR2CF . . . . . . D ADDR 00C9H A 131# TMR2CN . . . . . . D ADDR 00C8H A 128# TMR2H. . . . . . . D ADDR 00CDH A 143# TMR2L. . . . . . . D ADDR 00CCH A 140# TMR2_PAGE. . . . . N NUMB 0000H A 376# TMR3CF . . . . . . D ADDR 00C9H A 132# TMR3CN . . . . . . D ADDR 00C8H A 129# TMR3H. . . . . . . D ADDR 00CDH A 144# TMR3L. . . . . . . D ADDR 00CCH A 141# TMR3_PAGE. . . . . N NUMB 0001H A 377# TMR4CF . . . . . . D ADDR 00C9H A 133# TMR4CN . . . . . . D ADDR 00C8H A 130# TMR4H. . . . . . . D ADDR 00CDH A 145# TMR4L. . . . . . . D ADDR 00CCH A 142# TMR4_PAGE. . . . . N NUMB 0002H A 378# TR0. . . . . . . . B ADDR 0088H.4 A 205# TR1. . . . . . . . B ADDR 0088H.6 A 203# TR2. . . . . . . . B ADDR 00C8H.2 A 290# TR3. . . . . . . . B ADDR 00C8H.2 A 298# TR4. . . . . . . . B ADDR 00C8H.2 A 306# TXBMT. . . . . . . B ADDR 00F8H.1 A 357# UART0_PAGE . . . . N NUMB 0000H A 369# UART1_PAGE . . . . N NUMB 0001H A 370# WCOL . . . . . . . B ADDR 00F8H.6 A 352# WDTCN. . . . . . . D ADDR 00FFH A 195# 416 417 XBR0 . . . . . . . D ADDR 00E1H A 167# XBR1 . . . . . . . D ADDR 00E2H A 170# XBR2 . . . . . . . D ADDR 00E3H A 171# 423 REGISTER BANK(S) USED: 0 ASSEMBLY COMPLETE. 0 WARNING(S), 0 ERROR(S)