A51 MACRO ASSEMBLER INOUT32 04/25/2006 10:33:45 PAGE 1 MACRO ASSEMBLER A51 V7.04a OBJECT MODULE PLACED IN inout32.OBJ ASSEMBLER INVOKED BY: F:\SiLabs\MCU\IDEfiles\C51\BIN\a51.exe inout32.asm XR GEN DB EP NOMOD51 LOC OBJ LINE SOURCE 1 ;----------------------------------------------------------------------------- 2 ; 4/25/2006 sjd 3 ; 4 ; 5 ; 6 ; FILE NAME : INOUT32.ASM 7 ; TARGET MCU : C8051F120 8 ; DESCRIPTION : This program illustrates how to configure the 9 ; Crossbar, read and write to port 3 & 2 10 ; I/O pins. 11 ; 12 ; 13 ; NOTES: 14 ; 15 ; (1) This note intentionally left blank. 16 ; 17 ; 18 ;----------------------------------------------------------------------------- 19 20 21 ;----------------------------------------------------------------------------- 22 ; EQUATES 23 ;----------------------------------------------------------------------------- 24 25 ;$include (c8051f120.inc) ; Include register definition file. +1 26 ;--------------------------------------------------------------------------- +1 27 ; +1 28 ; +1 29 ; +1 30 ; +1 31 ; FILE NAME: C8051F120.INC +1 32 ; TARGET MCUs: C8051F120, F121, F122, F123, F124, F125, F126, F127 +1 33 ; DESCRIPTION: Register/bit definitions for the C8051F120 product family. +1 34 ; +1 35 ; REVISION 1.6 +1 36 ; +1 37 ;--------------------------------------------------------------------------- +1 38 +1 39 ;REGISTER DEFINITIONS +1 40 ; 0080 +1 41 P0 DATA 080H ; PORT 0 LATCH 0081 +1 42 SP DATA 081H ; STACK POINTER 0082 +1 43 DPL DATA 082H ; DATA POINTER LOW BYTE 0083 +1 44 DPH DATA 083H ; DATA POINTER HIGH BYTE 0084 +1 45 SFRPAGE DATA 084H ; SFR PAGE SELECT 0085 +1 46 SFRNEXT DATA 085H ; SFR STACK NEXT PAGE 0086 +1 47 SFRLAST DATA 086H ; SFR STACK LAST PAGE 0087 +1 48 PCON DATA 087H ; POWER CONTROL 0088 +1 49 FLSTAT DATA 088H ; FLASH STATUS 0088 +1 50 CPT0CN DATA 088H ; COMPARATOR 0 CONTROL 0088 +1 51 CPT1CN DATA 088H ; COMPARATOR 1 CONTROL 0088 +1 52 TCON DATA 088H ; TIMER/COUNTER CONTROL 0089 +1 53 TMOD DATA 089H ; TIMER/COUNTER MODE 0089 +1 54 CPT0MD DATA 089H ; COMPARATOR 0 CONFIGURATION 0089 +1 55 CPT1MD DATA 089H ; COMPARATOR 1 CONFIGURATION 0089 +1 56 PLL0CN DATA 089H ; PLL CONTROL 008A +1 57 OSCICN DATA 08AH ; INTERNAL OSCILLATOR CONTROL 008A +1 58 TL0 DATA 08AH ; TIMER/COUNTER 0 LOW BYTE A51 MACRO ASSEMBLER INOUT32 04/25/2006 10:33:45 PAGE 2 008B +1 59 OSCICL DATA 08BH ; INTERNAL OSCILLATOR CALIBRATION 008B +1 60 TL1 DATA 08BH ; TIMER/COUNTER 1 LOW BYTE 008C +1 61 OSCXCN DATA 08CH ; EXTERNAL OSCILLATOR CONTROL 008C +1 62 TH0 DATA 08CH ; TIMER/COUNTER 0 HIGH BYTE 008D +1 63 TH1 DATA 08DH ; TIMER/COUNTER 1 HIGH BYTE 008D +1 64 PLL0DIV DATA 08DH ; PLL DIVIDER 008E +1 65 CKCON DATA 08EH ; CLOCK CONTROL 008E +1 66 PLL0MUL DATA 08EH ; PLL MULTIPLIER 008F +1 67 PSCTL DATA 08FH ; FLASH WRITE/ERASE CONTROL 008F +1 68 PLL0FLT DATA 08FH ; PLL FILTER 0090 +1 69 P1 DATA 090H ; PORT 1 LATCH 0091 +1 70 SSTA0 DATA 091H ; UART 0 STATUS 0091 +1 71 MAC0BL DATA 091H ; MAC0 B REGISTER LOW BYTE 0092 +1 72 MAC0BH DATA 092H ; MAC0 B REGISTER HIGH BYTE 0093 +1 73 MAC0ACC0 DATA 093H ; MAC0 ACCUMULATOR BYTE 0 0094 +1 74 MAC0ACC1 DATA 094H ; MAC0 ACCUMULATOR BYTE 1 0095 +1 75 MAC0ACC2 DATA 095H ; MAC0 ACCUMULATOR BYTE 2 0096 +1 76 SFRPGCN DATA 096H ; SFR PAGE CONTROL 0096 +1 77 MAC0ACC3 DATA 096H ; MAC0 ACCUMULATOR BYTE 3 0097 +1 78 MAC0OVR DATA 097H ; MAC0 ACCUMULATOR OVERFLOW BYTE 0097 +1 79 CLKSEL DATA 097H ; SYSTEM CLOCK SELECT 0098 +1 80 SCON0 DATA 098H ; UART 0 CONTROL 0098 +1 81 SCON1 DATA 098H ; UART 1 CONTROL 0099 +1 82 SBUF0 DATA 099H ; UART 0 DATA BUFFER 0099 +1 83 SBUF1 DATA 099H ; UART 1 DATA BUFFER 009A +1 84 SPI0CFG DATA 09AH ; SPI CONFIGURATION 009A +1 85 CCH0MA DATA 09AH ; CACHE MISS ACCUMULATOR 009B +1 86 SPI0DAT DATA 09BH ; SPI DATA 009C +1 87 P4MDOUT DATA 09CH ; PORT 4 OUTPUT MODE CONFIGURATION 009D +1 88 P5MDOUT DATA 09DH ; PORT 5 OUTPUT MODE CONFIGURATION 009D +1 89 SPI0CKR DATA 09DH ; SPI CLOCK RATE CONTROL 009E +1 90 P6MDOUT DATA 09EH ; PORT 6 OUTPUT MODE CONFIGURATION 009F +1 91 P7MDOUT DATA 09FH ; PORT 7 OUTPUT MODE CONFIGURATION 00A0 +1 92 P2 DATA 0A0H ; PORT 2 LATCH 00A1 +1 93 EMI0TC DATA 0A1H ; EMIF TIMING CONTROL 00A1 +1 94 CCH0CN DATA 0A1H ; CACHE CONTROL 00A2 +1 95 EMI0CN DATA 0A2H ; EMIF CONTROL 00A2 +1 96 CCH0TN DATA 0A2H ; CACHE TUNING 00A3 +1 97 EMI0CF DATA 0A3H ; EMIF CONFIGURATION 00A3 +1 98 CCH0LC DATA 0A3H ; CACHE LOCK 00A4 +1 99 P0MDOUT DATA 0A4H ; PORT 0 OUTPUT MODE CONFIGURATION 00A5 +1 100 P1MDOUT DATA 0A5H ; PORT 1 OUTPUT MODE CONFIGURATION 00A6 +1 101 P2MDOUT DATA 0A6H ; PORT 2 OUTPUT MODE CONFIGURATION 00A7 +1 102 P3MDOUT DATA 0A7H ; PORT 3 OUTPUT MODE CONFIGURATION 00A8 +1 103 IE DATA 0A8H ; INTERRUPT ENABLE 00A9 +1 104 SADDR0 DATA 0A9H ; UART 0 SLAVE ADDRESS 00AD +1 105 P1MDIN DATA 0ADH ; PORT 1 INPUT MODE 00B0 +1 106 P3 DATA 0B0H ; PORT 3 LATCH 00B1 +1 107 PSBANK DATA 0B1H ; FLASH BANK SELECT 00B7 +1 108 FLACL DATA 0B7H ; FLASH ACCESS LIMIT 00B7 +1 109 FLSCL DATA 0B7H ; FLASH SCALE 00B8 +1 110 IP DATA 0B8H ; INTERRUPT PRIORITY 00B9 +1 111 SADEN0 DATA 0B9H ; UART 0 SLAVE ADDRESS MASK 00BA +1 112 AMX0CF DATA 0BAH ; ADC0 MULTIPLEXER CONFIGURATION 00BA +1 113 AMX2CF DATA 0BAH ; ADC2 MULTIPLEXER CONFIGURATION 00BB +1 114 AMX0SL DATA 0BBH ; ADC0 MULTIPLEXER CHANNEL SELECT 00BB +1 115 AMX2SL DATA 0BBH ; ADC2 MULTIPLEXER CHANNEL SELECT 00BC +1 116 ADC0CF DATA 0BCH ; ADC0 CONFIGURATION 00BC +1 117 ADC2CF DATA 0BCH ; ADC2 CONFIGURATION 00BE +1 118 ADC0L DATA 0BEH ; ADC0 DATA WORD LOW BYTE 00BE +1 119 ADC2 DATA 0BEH ; ADC2DATA WORD 00BF +1 120 ADC0H DATA 0BFH ; ADC0 DATA WORD HIGH BYTE 00C0 +1 121 MAC0STA DATA 0C0H ; MAC0 STATUS 00C0 +1 122 SMB0CN DATA 0C0H ; SMBUS CONTROL 00C1 +1 123 MAC0AL DATA 0C1H ; MAC0 A REGISTER LOW BYTE 00C1 +1 124 SMB0STA DATA 0C1H ; SMBUS STATUS A51 MACRO ASSEMBLER INOUT32 04/25/2006 10:33:45 PAGE 3 00C2 +1 125 MAC0AH DATA 0C2H ; MAC0 A REGISTER HIGH BYTE 00C2 +1 126 SMB0DAT DATA 0C2H ; SMBUS DATA 00C3 +1 127 MAC0CF DATA 0C3H ; MAC0 CONFIGURATION REGISTER 00C3 +1 128 SMB0ADR DATA 0C3H ; SMBUS SLAVE ADDRESS 00C4 +1 129 ADC0GTL DATA 0C4H ; ADC0 GREATER-THAN LOW BYTE 00C4 +1 130 ADC2GT DATA 0C4H ; ADC2 GREATER-THAN 00C5 +1 131 ADC0GTH DATA 0C5H ; ADC0 GREATER-THAN HIGH BYTE 00C6 +1 132 ADC0LTL DATA 0C6H ; ADC0 LESS-THAN LOW BYTE 00C6 +1 133 ADC2LT DATA 0C6H ; ADC2 LESS-THAN 00C7 +1 134 ADC0LTH DATA 0C7H ; ADC0 LESS-THAN HIGH BYTE 00C8 +1 135 P4 DATA 0C8H ; PORT 4 LATCH 00C8 +1 136 TMR2CN DATA 0C8H ; TIMER/COUNTER 2 CONTROL 00C8 +1 137 TMR3CN DATA 0C8H ; TIMER 3 CONTROL 00C8 +1 138 TMR4CN DATA 0C8H ; TIMER/COUNTER 4 CONTROL 00C9 +1 139 TMR2CF DATA 0C9H ; TIMER/COUNTER 2 CONFIGURATION 00C9 +1 140 TMR3CF DATA 0C9H ; TIMER 3 CONFIGURATION 00C9 +1 141 TMR4CF DATA 0C9H ; TIMER/COUNTER 4 CONFIGURATION 00CA +1 142 RCAP2L DATA 0CAH ; TIMER/COUNTER 2 CAPTURE/RELOAD LOW BYTE 00CA +1 143 RCAP3L DATA 0CAH ; TIMER 3 CAPTURE/RELOAD LOW BYTE 00CA +1 144 RCAP4L DATA 0CAH ; TIMER/COUNTER 4 CAPTURE/RELOAD LOW BYTE 00CB +1 145 RCAP2H DATA 0CBH ; TIMER/COUNTER 2 CAPTURE/RELOAD HIGH BYTE 00CB +1 146 RCAP3H DATA 0CBH ; TIMER 3 CAPTURE/RELOAD HIGH BYTE 00CB +1 147 RCAP4H DATA 0CBH ; TIMER/COUNTER 4 CAPTURE/RELOAD HIGH BYTE 00CC +1 148 TMR2L DATA 0CCH ; TIMER/COUNTER 2 LOW BYTE 00CC +1 149 TMR3L DATA 0CCH ; TIMER 3 LOW BYTE 00CC +1 150 TMR4L DATA 0CCH ; TIMER/COUNTER 4 LOW BYTE 00CD +1 151 TMR2H DATA 0CDH ; TIMER/COUNTER 2 HIGH BYTE 00CD +1 152 TMR3H DATA 0CDH ; TIMER 3 HIGH BYTE 00CD +1 153 TMR4H DATA 0CDH ; TIMER/COUNTER 4 HIGH BYTE 00CE +1 154 MAC0RNDL DATA 0CEH ; MAC0 ROUNDING REGISTER LOW BYTE 00CF +1 155 MAC0RNDH DATA 0CFH ; MAC0 ROUNDING REGISTER HIGH BYTE 00CF +1 156 SMB0CR DATA 0CFH ; SMBUS CLOCK RATE 00D0 +1 157 PSW DATA 0D0H ; PROGRAM STATUS WORD 00D1 +1 158 REF0CN DATA 0D1H ; VOLTAGE REFERENCE CONTROL 00D2 +1 159 DAC0L DATA 0D2H ; DAC0 LOW BYTE 00D2 +1 160 DAC1L DATA 0D2H ; DAC1 LOW BYTE 00D3 +1 161 DAC0H DATA 0D3H ; DAC0 HIGH BYTE 00D3 +1 162 DAC1H DATA 0D3H ; DAC1 HIGH BYTE 00D4 +1 163 DAC0CN DATA 0D4H ; DAC0 CONTROL 00D4 +1 164 DAC1CN DATA 0D4H ; DAC1 CONTROL 00D8 +1 165 P5 DATA 0D8H ; PORT 5 LATCH 00D8 +1 166 PCA0CN DATA 0D8H ; PCA CONTROL 00D9 +1 167 PCA0MD DATA 0D9H ; PCA MODE 00DA +1 168 PCA0CPM0 DATA 0DAH ; PCA MODULE 0 MODE 00DB +1 169 PCA0CPM1 DATA 0DBH ; PCA MODULE 1 MODE REGISTER 00DC +1 170 PCA0CPM2 DATA 0DCH ; PCA MODULE 2 MODE 00DD +1 171 PCA0CPM3 DATA 0DDH ; PCA MODULE 3 MODE 00DE +1 172 PCA0CPM4 DATA 0DEH ; PCA MODULE 4 MODE 00DF +1 173 PCA0CPM5 DATA 0DFH ; PCA MODULE 5 MODE 00E0 +1 174 ACC DATA 0E0H ; ACCUMULATOR 00E1 +1 175 XBR0 DATA 0E1H ; PORT I/O CROSSBAR CONTROL 0 00E1 +1 176 PCA0CPL5 DATA 0E1H ; PCA MODULE 5 CAPTURE/COMPARE LOW BYTE 00E2 +1 177 PCA0CPH5 DATA 0E2H ; PCA MODULE 5 CAPTURE/COMPARE HIGH BYTE 00E2 +1 178 XBR1 DATA 0E2H ; PORT I/O CROSSBAR CONTROL 1 00E3 +1 179 XBR2 DATA 0E3H ; PORT I/O CROSSBAR CONTROL 2 00E6 +1 180 EIE1 DATA 0E6H ; EXTENDED INTERRUPT ENABLE 1 00E7 +1 181 EIE2 DATA 0E7H ; EXTENDED INTERRUPT ENABLE 2 00E8 +1 182 ADC0CN DATA 0E8H ; ADC0 CONTROL 00E8 +1 183 ADC2CN DATA 0E8H ; ADC2 CONTROL 00E8 +1 184 P6 DATA 0E8H ; PORT 6 LATCH 00E9 +1 185 PCA0CPL2 DATA 0E9H ; PCA MODULE 2 CAPTURE/COMPARE LOW BYTE 00EA +1 186 PCA0CPH2 DATA 0EAH ; PCA MODULE 2 CAPTURE/COMPARE HIGH BYTE 00EB +1 187 PCA0CPL3 DATA 0EBH ; PCA MODULE 3 CAPTURE/COMPARE LOW BYTE 00EC +1 188 PCA0CPH3 DATA 0ECH ; PCA MODULE 3 CAPTURE/COMPARE HIGH BYTE 00ED +1 189 PCA0CPL4 DATA 0EDH ; PCA MODULE 4 CAPTURE/COMPARE LOW BYTE 00EE +1 190 PCA0CPH4 DATA 0EEH ; PCA MODULE 4 CAPTURE/COMPARE HIGH BYTE A51 MACRO ASSEMBLER INOUT32 04/25/2006 10:33:45 PAGE 4 00EF +1 191 RSTSRC DATA 0EFH ; RESET SOURCE 00F0 +1 192 B DATA 0F0H ; B REGISTER 00F6 +1 193 EIP1 DATA 0F6H ; EXTERNAL INTERRUPT PRIORITY 1 00F7 +1 194 EIP2 DATA 0F7H ; EXTERNAL INTERRUPT PRIORITY 2 00F8 +1 195 P7 DATA 0F8H ; PORT 7 LATCH 00F8 +1 196 SPI0CN DATA 0F8H ; SPI CONTROL 00F9 +1 197 PCA0L DATA 0F9H ; PCA COUNTER LOW BYTE 00FA +1 198 PCA0H DATA 0FAH ; PCA COUNTER HIGH BYTE 00FB +1 199 PCA0CPL0 DATA 0FBH ; PCA MODULE 0 CAPTURE/COMPARE LOW BYTE 00FC +1 200 PCA0CPH0 DATA 0FCH ; PCA MODULE 0 CAPTURE/COMPARE HIGH BYTE 00FD +1 201 PCA0CPL1 DATA 0FDH ; PCA MODULE 1 CAPTURE/COMPARE LOW BYTE 00FE +1 202 PCA0CPH1 DATA 0FEH ; PCA MODULE 1 CAPTURE/COMPARE HIGH BYTE 00FF +1 203 WDTCN DATA 0FFH ; WATCHDOG TIMER CONTROL +1 204 +1 205 ; +1 206 ;------------------------------------------------------------------------------ +1 207 ;BIT DEFINITIONS +1 208 ; +1 209 ; TCON 088H 008F +1 210 TF1 BIT 08FH ; TIMER 1 OVERFLOW FLAG 008E +1 211 TR1 BIT 08EH ; TIMER 1 ON/OFF CONTROL 008D +1 212 TF0 BIT 08DH ; TIMER 0 OVERFLOW FLAG 008C +1 213 TR0 BIT 08CH ; TIMER 0 ON/OFF CONTROL 008B +1 214 IE1 BIT 08BH ; EXT. INTERRUPT 1 EDGE FLAG 008A +1 215 IT1 BIT 08AH ; EXT. INTERRUPT 1 TYPE 0089 +1 216 IE0 BIT 089H ; EXT. INTERRUPT 0 EDGE FLAG 0088 +1 217 IT0 BIT 088H ; EXT. INTERRUPT 0 TYPE +1 218 +1 219 ; CPT0CN 088H 008F +1 220 CP0EN BIT 08FH ; COMPARATOR 0 ENABLE 008E +1 221 CP0OUT BIT 08EH ; COMPARATOR 0 OUTPUT 008D +1 222 CP0RIF BIT 08DH ; COMPARATOR 0 RISING EDGE INTERRUPT 008C +1 223 CP0FIF BIT 08CH ; COMPARATOR 0 FALLING EDGE INTERRUPT 008B +1 224 CP0HYP1 BIT 08BH ; COMPARATOR 0 POSITIVE HYSTERISIS 1 008A +1 225 CP0HYP0 BIT 08AH ; COMPARATOR 0 POSITIVE HYSTERISIS 0 0089 +1 226 CP0HYN1 BIT 089H ; COMPARATOR 0 NEGATIVE HYSTERISIS 1 0088 +1 227 CP0HYN0 BIT 088H ; COMPARATOR 0 NEGATIVE HYSTERISIS 0 +1 228 +1 229 ; CPT1CN 088H 008F +1 230 CP1EN BIT 08FH ; COMPARATOR 1 ENABLE 008E +1 231 CP1OUT BIT 08EH ; COMPARATOR 1 OUTPUT 008D +1 232 CP1RIF BIT 08DH ; COMPARATOR 1 RISING EDGE INTERRUPT 008C +1 233 CP1FIF BIT 08CH ; COMPARATOR 1 FALLING EDGE INTERRUPT 008B +1 234 CP1HYP1 BIT 08BH ; COMPARATOR 1 POSITIVE HYSTERISIS 1 008A +1 235 CP1HYP0 BIT 08AH ; COMPARATOR 1 POSITIVE HYSTERISIS 0 0089 +1 236 CP1HYN1 BIT 089H ; COMPARATOR 1 NEGATIVE HYSTERISIS 1 0088 +1 237 CP1HYN0 BIT 088H ; COMPARATOR 1 NEGATIVE HYSTERISIS 0 +1 238 +1 239 ; FLSTAT 088H 0088 +1 240 FLHBUSY BIT 088H ; FLASH BUSY +1 241 +1 242 ; SCON0 098H 009F +1 243 SM00 BIT 09FH ; UART 0 MODE 0 009E +1 244 SM10 BIT 09EH ; UART 0 MODE 1 009D +1 245 SM20 BIT 09DH ; UART 0 MULTIPROCESSOR EN 009C +1 246 REN0 BIT 09CH ; UART 0 RX ENABLE 009B +1 247 TB80 BIT 09BH ; UART 0 TX BIT 8 009A +1 248 RB80 BIT 09AH ; UART 0 RX BIT 8 0099 +1 249 TI0 BIT 099H ; UART 0 TX INTERRUPT FLAG 0098 +1 250 RI0 BIT 098H ; UART 0 RX INTERRUPT FLAG +1 251 +1 252 ; SCON1 098H 009F +1 253 S1MODE BIT 09FH ; UART 1 MODE 009D +1 254 MCE1 BIT 09DH ; UART 1 MCE 009C +1 255 REN1 BIT 09CH ; UART 1 RX ENABLE 009B +1 256 TB81 BIT 09BH ; UART 1 TX BIT 8 A51 MACRO ASSEMBLER INOUT32 04/25/2006 10:33:45 PAGE 5 009A +1 257 RB81 BIT 09AH ; UART 1 RX BIT 8 0099 +1 258 TI1 BIT 099H ; UART 1 TX INTERRUPT FLAG 0098 +1 259 RI1 BIT 098H ; UART 1 RX INTERRUPT FLAG +1 260 +1 261 ; IE 0A8H 00AF +1 262 EA BIT 0AFH ; GLOBAL INTERRUPT ENABLE 00AD +1 263 ET2 BIT 0ADH ; TIMER 2 INTERRUPT ENABLE 00AC +1 264 ES0 BIT 0ACH ; UART0 INTERRUPT ENABLE 00AB +1 265 ET1 BIT 0ABH ; TIMER 1 INTERRUPT ENABLE 00AA +1 266 EX1 BIT 0AAH ; EXTERNAL INTERRUPT 1 ENABLE 00A9 +1 267 ET0 BIT 0A9H ; TIMER 0 INTERRUPT ENABLE 00A8 +1 268 EX0 BIT 0A8H ; EXTERNAL INTERRUPT 0 ENABLE +1 269 +1 270 ; IP 0B8H 00BD +1 271 PT2 BIT 0BDH ; TIMER 2 PRIORITY 00BC +1 272 PS BIT 0BCH ; SERIAL PORT PRIORITY 00BB +1 273 PT1 BIT 0BBH ; TIMER 1 PRIORITY 00BA +1 274 PX1 BIT 0BAH ; EXTERNAL INTERRUPT 1 PRIORITY 00B9 +1 275 PT0 BIT 0B9H ; TIMER 0 PRIORITY 00B8 +1 276 PX0 BIT 0B8H ; EXTERNAL INTERRUPT 0 PRIORITY +1 277 +1 278 ; SMB0CN 0C0H 00C7 +1 279 BUSY BIT 0C7H ; SMBUS 0 BUSY 00C6 +1 280 ENSMB BIT 0C6H ; SMBUS 0 ENABLE 00C5 +1 281 STA BIT 0C5H ; SMBUS 0 START FLAG 00C4 +1 282 STO BIT 0C4H ; SMBUS 0 STOP FLAG 00C3 +1 283 SI BIT 0C3H ; SMBUS 0 INTERRUPT PENDING FLAG 00C2 +1 284 AA BIT 0C2H ; SMBUS 0 ASSERT/ACKNOWLEDGE FLAG 00C1 +1 285 SMBFTE BIT 0C1H ; SMBUS 0 FREE TIMER ENABLE 00C0 +1 286 SMBTOE BIT 0C0H ; SMBUS 0 TIMEOUT ENABLE +1 287 +1 288 ; MAC0STA 0C0H 00C3 +1 289 MAC0HO BIT 0C3H ; MAC0 HARD OVERFLOW 00C2 +1 290 MAC0Z BIT 0C2H ; MAC0 ZERO 00C1 +1 291 MAC0SO BIT 0C1H ; MAC0 SOFT OVERFLOW 00C0 +1 292 MAC0N BIT 0C0H ; MAC0 NEGATIVE +1 293 +1 294 ; TMR2CN 0C8H 00CF +1 295 TF2 BIT 0CFH ; TIMER 2 OVERFLOW FLAG 00CE +1 296 EXF2 BIT 0CEH ; TIMER 2 EXTERNAL FLAG 00CB +1 297 EXEN2 BIT 0CBH ; TIMER 2 EXTERNAL ENABLE FLAG 00CA +1 298 TR2 BIT 0CAH ; TIMER 2 ON/OFF CONTROL 00C9 +1 299 CT2 BIT 0C9H ; TIMER 2 COUNTER SELECT 00C8 +1 300 CPRL2 BIT 0C8H ; TIMER 2 CAPTURE SELECT +1 301 +1 302 ; TMR3CN 0C8H 00CF +1 303 TF3 BIT 0CFH ; TIMER 3 OVERFLOW FLAG 00CE +1 304 EXF3 BIT 0CEH ; TIMER 3 EXTERNAL FLAG 00CB +1 305 EXEN3 BIT 0CBH ; TIMER 3 EXTERNAL ENABLE FLAG 00CA +1 306 TR3 BIT 0CAH ; TIMER 3 ON/OFF CONTROL 00C9 +1 307 CT3 BIT 0C9H ; TIMER 3 COUNTER SELECT 00C8 +1 308 CPRL3 BIT 0C8H ; TIMER 3 CAPTURE SELECT +1 309 +1 310 ; TMR4CN 0C8H 00CF +1 311 TF4 BIT 0CFH ; TIMER 4 OVERFLOW FLAG 00CE +1 312 EXF4 BIT 0CEH ; TIMER 4 EXTERNAL FLAG 00CB +1 313 EXEN4 BIT 0CBH ; TIMER 4 EXTERNAL ENABLE FLAG 00CA +1 314 TR4 BIT 0CAH ; TIMER 4 ON/OFF CONTROL 00C9 +1 315 CT4 BIT 0C9H ; TIMER 4 COUNTER SELECT 00C8 +1 316 CPRL4 BIT 0C8H ; TIMER 4 CAPTURE SELECT +1 317 +1 318 ; PSW 0D0H 00D7 +1 319 CY BIT 0D7H ; CARRY FLAG 00D6 +1 320 AC BIT 0D6H ; AUXILIARY CARRY FLAG 00D5 +1 321 F0 BIT 0D5H ; USER FLAG 0 00D4 +1 322 RS1 BIT 0D4H ; REGISTER BANK SELECT 1 A51 MACRO ASSEMBLER INOUT32 04/25/2006 10:33:45 PAGE 6 00D3 +1 323 RS0 BIT 0D3H ; REGISTER BANK SELECT 0 00D2 +1 324 OV BIT 0D2H ; OVERFLOW FLAG 00D1 +1 325 F1 BIT 0D1H ; USER FLAG 1 00D0 +1 326 P BIT 0D0H ; ACCUMULATOR PARITY FLAG +1 327 +1 328 ; PCA0CN 0D8H 00DF +1 329 CF BIT 0DFH ; PCA 0 COUNTER OVERFLOW FLAG 00DE +1 330 CR BIT 0DEH ; PCA 0 COUNTER RUN CONTROL BIT 00DD +1 331 CCF5 BIT 0DDH ; PCA 0 MODULE 5 INTERRUPT FLAG 00DC +1 332 CCF4 BIT 0DCH ; PCA 0 MODULE 4 INTERRUPT FLAG 00DB +1 333 CCF3 BIT 0DBH ; PCA 0 MODULE 3 INTERRUPT FLAG 00DA +1 334 CCF2 BIT 0DAH ; PCA 0 MODULE 2 INTERRUPT FLAG 00D9 +1 335 CCF1 BIT 0D9H ; PCA 0 MODULE 1 INTERRUPT FLAG 00D8 +1 336 CCF0 BIT 0D8H ; PCA 0 MODULE 0 INTERRUPT FLAG +1 337 +1 338 ; ADC0CN 0E8H 00EF +1 339 AD0EN BIT 0EFH ; ADC 0 ENABLE 00EE +1 340 AD0TM BIT 0EEH ; ADC 0 TRACK MODE 00ED +1 341 AD0INT BIT 0EDH ; ADC 0 EOC INTERRUPT FLAG 00EC +1 342 AD0BUSY BIT 0ECH ; ADC 0 BUSY FLAG 00EB +1 343 AD0CM1 BIT 0EBH ; ADC 0 CONVERT START MODE BIT 1 00EA +1 344 AD0CM0 BIT 0EAH ; ADC 0 CONVERT START MODE BIT 0 00E9 +1 345 AD0WINT BIT 0E9H ; ADC 0 WINDOW INTERRUPT FLAG 00E8 +1 346 AD0LJST BIT 0E8H ; ADC 0 LEFT JUSTIFY DATA BIT +1 347 +1 348 ; ADC2CN 0E8H 00EF +1 349 AD2EN BIT 0EFH ; ADC 2 ENABLE 00EE +1 350 AD2TM BIT 0EEH ; ADC 2 TRACK MODE 00ED +1 351 AD2INT BIT 0EDH ; ADC 2 EOC INTERRUPT FLAG 00EC +1 352 AD2BUSY BIT 0ECH ; ADC 2 BUSY FLAG 00EB +1 353 AD2CM2 BIT 0EBH ; ADC 2 CONVERT START MODE BIT 2 00EA +1 354 AD2CM1 BIT 0EAH ; ADC 2 CONVERT START MODE BIT 1 00E9 +1 355 AD2CM0 BIT 0E9H ; ADC 2 CONVERT START MODE BIT 0 00E8 +1 356 AD2WINT BIT 0E8H ; ADC 2 WINDOW INTERRUPT FLAG +1 357 +1 358 ; SPI0CN 0F8H 00FF +1 359 SPIF BIT 0FFH ; SPI 0 INTERRUPT FLAG 00FE +1 360 WCOL BIT 0FEH ; SPI 0 WRITE COLLISION FLAG 00FD +1 361 MODF BIT 0FDH ; SPI 0 MODE FAULT FLAG 00FC +1 362 RXOVRN BIT 0FCH ; SPI 0 RX OVERRUN FLAG 00FB +1 363 NSSMD1 BIT 0FBH ; SPI 0 SLAVE SELECT MODE 1 00FA +1 364 NSSMD0 BIT 0FAH ; SPI 0 SLAVE SELECT MODE 0 00F9 +1 365 TXBMT BIT 0F9H ; SPI 0 TX BUFFER EMPTY FLAG 00F8 +1 366 SPIEN BIT 0F8H ; SPI 0 SPI ENABLE +1 367 +1 368 ; +1 369 ;------------------------------------------------------------------------------ +1 370 ; SFR PAGE DEFINITIONS +1 371 ; 000F +1 372 CONFIG_PAGE EQU 0FH ; SYSTEM AND PORT CONFIGURATION PAGE 0000 +1 373 LEGACY_PAGE EQU 00H ; LEGACY SFR PAGE 0000 +1 374 TIMER01_PAGE EQU 00H ; TIMER 0 AND TIMER 1 0001 +1 375 CPT0_PAGE EQU 01H ; COMPARATOR 0 0002 +1 376 CPT1_PAGE EQU 02H ; COMPARATOR 1 0000 +1 377 UART0_PAGE EQU 00H ; UART 0 0001 +1 378 UART1_PAGE EQU 01H ; UART 1 0000 +1 379 SPI0_PAGE EQU 00H ; SPI 0 0000 +1 380 EMI0_PAGE EQU 00H ; EXTERNAL MEMORY INTERFACE 0000 +1 381 ADC0_PAGE EQU 00H ; ADC 0 0002 +1 382 ADC2_PAGE EQU 02H ; ADC 2 0000 +1 383 SMB0_PAGE EQU 00H ; SMBUS 0 0000 +1 384 TMR2_PAGE EQU 00H ; TIMER 2 0001 +1 385 TMR3_PAGE EQU 01H ; TIMER 3 0002 +1 386 TMR4_PAGE EQU 02H ; TIMER 4 0000 +1 387 DAC0_PAGE EQU 00H ; DAC 0 0001 +1 388 DAC1_PAGE EQU 01H ; DAC 1 A51 MACRO ASSEMBLER INOUT32 04/25/2006 10:33:45 PAGE 7 0000 +1 389 PCA0_PAGE EQU 00H ; PCA 0 000F +1 390 PLL0_PAGE EQU 0FH ; PLL 0 0003 +1 391 MAC0_PAGE EQU 03H ; MAC 0 392 393 394 ;----------------------------------------------------------------------------- 395 ; VARIABLES 396 ;----------------------------------------------------------------------------- 397 398 ;----------------------------------------------------------------------------- 399 ; RESET and INTERRUPT VECTORS 400 ;----------------------------------------------------------------------------- 401 402 403 ; Reset Vector ---- 404 cseg AT 0 0000 020000 F 405 ljmp Main ; Locate a jump to the start of code at 406 ; the reset vector. 407 408 ;----------------------------------------------------------------------------- 409 ; CODE SEGMENT 410 ;----------------------------------------------------------------------------- 411 412 Code_Seg segment CODE 413 ---- 414 rseg Code_Seg ; Switch to this code segment. 415 using 0 ; Specify register bank for the following 416 ; program code. 417 418 ; Use SFRs on the Configuration Page 0000 75840F 419 Main: mov SFRPAGE, #CONFIG_PAGE 420 421 ; Enable the Port I/O Crossbar 0003 75E340 422 mov XBR2, #40h 423 424 ; P3 input, P2 output. 425 ; loop. 0006 AFB0 426 Loop: mov R7, P3 ; read port3 0008 8FA0 427 mov P2, R7 ; write port2 000A 80FA 428 jmp Loop 429 430 431 ;----------------------------------------------------------------------------- 432 ; End of file. 433 434 END A51 MACRO ASSEMBLER INOUT32 04/25/2006 10:33:45 PAGE 8 XREF SYMBOL TABLE LISTING ---- ------ ----- ------- N A M E T Y P E V A L U E ATTRIBUTES / REFERENCES AA . . . . . . . . B ADDR 00C0H.2 A 284# AC . . . . . . . . B ADDR 00D0H.6 A 320# ACC. . . . . . . . D ADDR 00E0H A 174# AD0BUSY. . . . . . B ADDR 00E8H.4 A 342# AD0CM0 . . . . . . B ADDR 00E8H.2 A 344# AD0CM1 . . . . . . B ADDR 00E8H.3 A 343# AD0EN. . . . . . . B ADDR 00E8H.7 A 339# AD0INT . . . . . . B ADDR 00E8H.5 A 341# AD0LJST. . . . . . B ADDR 00E8H.0 A 346# AD0TM. . . . . . . B ADDR 00E8H.6 A 340# AD0WINT. . . . . . B ADDR 00E8H.1 A 345# AD2BUSY. . . . . . B ADDR 00E8H.4 A 352# AD2CM0 . . . . . . B ADDR 00E8H.1 A 355# AD2CM1 . . . . . . B ADDR 00E8H.2 A 354# AD2CM2 . . . . . . B ADDR 00E8H.3 A 353# AD2EN. . . . . . . B ADDR 00E8H.7 A 349# AD2INT . . . . . . B ADDR 00E8H.5 A 351# AD2TM. . . . . . . B ADDR 00E8H.6 A 350# AD2WINT. . . . . . B ADDR 00E8H.0 A 356# ADC0CF . . . . . . D ADDR 00BCH A 116# ADC0CN . . . . . . D ADDR 00E8H A 182# ADC0GTH. . . . . . D ADDR 00C5H A 131# ADC0GTL. . . . . . D ADDR 00C4H A 129# ADC0H. . . . . . . D ADDR 00BFH A 120# ADC0L. . . . . . . D ADDR 00BEH A 118# ADC0LTH. . . . . . D ADDR 00C7H A 134# ADC0LTL. . . . . . D ADDR 00C6H A 132# ADC0_PAGE. . . . . N NUMB 0000H A 381# ADC2 . . . . . . . D ADDR 00BEH A 119# ADC2CF . . . . . . D ADDR 00BCH A 117# ADC2CN . . . . . . D ADDR 00E8H A 183# ADC2GT . . . . . . D ADDR 00C4H A 130# ADC2LT . . . . . . D ADDR 00C6H A 133# ADC2_PAGE. . . . . N NUMB 0002H A 382# AMX0CF . . . . . . D ADDR 00BAH A 112# AMX0SL . . . . . . D ADDR 00BBH A 114# AMX2CF . . . . . . D ADDR 00BAH A 113# AMX2SL . . . . . . D ADDR 00BBH A 115# B. . . . . . . . . D ADDR 00F0H A 192# BUSY . . . . . . . B ADDR 00C0H.7 A 279# CCF0 . . . . . . . B ADDR 00D8H.0 A 336# CCF1 . . . . . . . B ADDR 00D8H.1 A 335# CCF2 . . . . . . . B ADDR 00D8H.2 A 334# CCF3 . . . . . . . B ADDR 00D8H.3 A 333# CCF4 . . . . . . . B ADDR 00D8H.4 A 332# CCF5 . . . . . . . B ADDR 00D8H.5 A 331# CCH0CN . . . . . . D ADDR 00A1H A 94# CCH0LC . . . . . . D ADDR 00A3H A 98# CCH0MA . . . . . . D ADDR 009AH A 85# CCH0TN . . . . . . D ADDR 00A2H A 96# CF . . . . . . . . B ADDR 00D8H.7 A 329# CKCON. . . . . . . D ADDR 008EH A 65# CLKSEL . . . . . . D ADDR 0097H A 79# CODE_SEG . . . . . C SEG 000CH REL=UNIT 412# 414 CONFIG_PAGE. . . . N NUMB 000FH A 372# 419 CP0EN. . . . . . . B ADDR 0088H.7 A 220# CP0FIF . . . . . . B ADDR 0088H.4 A 223# CP0HYN0. . . . . . B ADDR 0088H.0 A 227# CP0HYN1. . . . . . B ADDR 0088H.1 A 226# CP0HYP0. . . . . . B ADDR 0088H.2 A 225# A51 MACRO ASSEMBLER INOUT32 04/25/2006 10:33:45 PAGE 9 CP0HYP1. . . . . . B ADDR 0088H.3 A 224# CP0OUT . . . . . . B ADDR 0088H.6 A 221# CP0RIF . . . . . . B ADDR 0088H.5 A 222# CP1EN. . . . . . . B ADDR 0088H.7 A 230# CP1FIF . . . . . . B ADDR 0088H.4 A 233# CP1HYN0. . . . . . B ADDR 0088H.0 A 237# CP1HYN1. . . . . . B ADDR 0088H.1 A 236# CP1HYP0. . . . . . B ADDR 0088H.2 A 235# CP1HYP1. . . . . . B ADDR 0088H.3 A 234# CP1OUT . . . . . . B ADDR 0088H.6 A 231# CP1RIF . . . . . . B ADDR 0088H.5 A 232# CPRL2. . . . . . . B ADDR 00C8H.0 A 300# CPRL3. . . . . . . B ADDR 00C8H.0 A 308# CPRL4. . . . . . . B ADDR 00C8H.0 A 316# CPT0CN . . . . . . D ADDR 0088H A 50# CPT0MD . . . . . . D ADDR 0089H A 54# CPT0_PAGE. . . . . N NUMB 0001H A 375# CPT1CN . . . . . . D ADDR 0088H A 51# CPT1MD . . . . . . D ADDR 0089H A 55# CPT1_PAGE. . . . . N NUMB 0002H A 376# CR . . . . . . . . B ADDR 00D8H.6 A 330# CT2. . . . . . . . B ADDR 00C8H.1 A 299# CT3. . . . . . . . B ADDR 00C8H.1 A 307# CT4. . . . . . . . B ADDR 00C8H.1 A 315# CY . . . . . . . . B ADDR 00D0H.7 A 319# DAC0CN . . . . . . D ADDR 00D4H A 163# DAC0H. . . . . . . D ADDR 00D3H A 161# DAC0L. . . . . . . D ADDR 00D2H A 159# DAC0_PAGE. . . . . N NUMB 0000H A 387# DAC1CN . . . . . . D ADDR 00D4H A 164# DAC1H. . . . . . . D ADDR 00D3H A 162# DAC1L. . . . . . . D ADDR 00D2H A 160# DAC1_PAGE. . . . . N NUMB 0001H A 388# DPH. . . . . . . . D ADDR 0083H A 44# DPL. . . . . . . . D ADDR 0082H A 43# EA . . . . . . . . B ADDR 00A8H.7 A 262# EIE1 . . . . . . . D ADDR 00E6H A 180# EIE2 . . . . . . . D ADDR 00E7H A 181# EIP1 . . . . . . . D ADDR 00F6H A 193# EIP2 . . . . . . . D ADDR 00F7H A 194# EMI0CF . . . . . . D ADDR 00A3H A 97# EMI0CN . . . . . . D ADDR 00A2H A 95# EMI0TC . . . . . . D ADDR 00A1H A 93# EMI0_PAGE. . . . . N NUMB 0000H A 380# ENSMB. . . . . . . B ADDR 00C0H.6 A 280# ES0. . . . . . . . B ADDR 00A8H.4 A 264# ET0. . . . . . . . B ADDR 00A8H.1 A 267# ET1. . . . . . . . B ADDR 00A8H.3 A 265# ET2. . . . . . . . B ADDR 00A8H.5 A 263# EX0. . . . . . . . B ADDR 00A8H.0 A 268# EX1. . . . . . . . B ADDR 00A8H.2 A 266# EXEN2. . . . . . . B ADDR 00C8H.3 A 297# EXEN3. . . . . . . B ADDR 00C8H.3 A 305# EXEN4. . . . . . . B ADDR 00C8H.3 A 313# EXF2 . . . . . . . B ADDR 00C8H.6 A 296# EXF3 . . . . . . . B ADDR 00C8H.6 A 304# EXF4 . . . . . . . B ADDR 00C8H.6 A 312# F0 . . . . . . . . B ADDR 00D0H.5 A 321# F1 . . . . . . . . B ADDR 00D0H.1 A 325# FLACL. . . . . . . D ADDR 00B7H A 108# FLHBUSY. . . . . . B ADDR 0088H.0 A 240# FLSCL. . . . . . . D ADDR 00B7H A 109# FLSTAT . . . . . . D ADDR 0088H A 49# IE . . . . . . . . D ADDR 00A8H A 103# IE0. . . . . . . . B ADDR 0088H.1 A 216# IE1. . . . . . . . B ADDR 0088H.3 A 214# A51 MACRO ASSEMBLER INOUT32 04/25/2006 10:33:45 PAGE 10 IP . . . . . . . . D ADDR 00B8H A 110# IT0. . . . . . . . B ADDR 0088H.0 A 217# IT1. . . . . . . . B ADDR 0088H.2 A 215# LEGACY_PAGE. . . . N NUMB 0000H A 373# LOOP . . . . . . . C ADDR 0006H R SEG=CODE_SEG 426# 428 MAC0ACC0 . . . . . D ADDR 0093H A 73# MAC0ACC1 . . . . . D ADDR 0094H A 74# MAC0ACC2 . . . . . D ADDR 0095H A 75# MAC0ACC3 . . . . . D ADDR 0096H A 77# MAC0AH . . . . . . D ADDR 00C2H A 125# MAC0AL . . . . . . D ADDR 00C1H A 123# MAC0BH . . . . . . D ADDR 0092H A 72# MAC0BL . . . . . . D ADDR 0091H A 71# MAC0CF . . . . . . D ADDR 00C3H A 127# MAC0HO . . . . . . B ADDR 00C0H.3 A 289# MAC0N. . . . . . . B ADDR 00C0H.0 A 292# MAC0OVR. . . . . . D ADDR 0097H A 78# MAC0RNDH . . . . . D ADDR 00CFH A 155# MAC0RNDL . . . . . D ADDR 00CEH A 154# MAC0SO . . . . . . B ADDR 00C0H.1 A 291# MAC0STA. . . . . . D ADDR 00C0H A 121# MAC0Z. . . . . . . B ADDR 00C0H.2 A 290# MAC0_PAGE. . . . . N NUMB 0003H A 391# MAIN . . . . . . . C ADDR 0000H R SEG=CODE_SEG 405 419# MCE1 . . . . . . . B ADDR 0098H.5 A 254# MODF . . . . . . . B ADDR 00F8H.5 A 361# NSSMD0 . . . . . . B ADDR 00F8H.2 A 364# NSSMD1 . . . . . . B ADDR 00F8H.3 A 363# OSCICL . . . . . . D ADDR 008BH A 59# OSCICN . . . . . . D ADDR 008AH A 57# OSCXCN . . . . . . D ADDR 008CH A 61# OV . . . . . . . . B ADDR 00D0H.2 A 324# P. . . . . . . . . B ADDR 00D0H.0 A 326# P0 . . . . . . . . D ADDR 0080H A 41# P0MDOUT. . . . . . D ADDR 00A4H A 99# P1 . . . . . . . . D ADDR 0090H A 69# P1MDIN . . . . . . D ADDR 00ADH A 105# P1MDOUT. . . . . . D ADDR 00A5H A 100# P2 . . . . . . . . D ADDR 00A0H A 92# 427 P2MDOUT. . . . . . D ADDR 00A6H A 101# P3 . . . . . . . . D ADDR 00B0H A 106# 426 P3MDOUT. . . . . . D ADDR 00A7H A 102# P4 . . . . . . . . D ADDR 00C8H A 135# P4MDOUT. . . . . . D ADDR 009CH A 87# P5 . . . . . . . . D ADDR 00D8H A 165# P5MDOUT. . . . . . D ADDR 009DH A 88# P6 . . . . . . . . D ADDR 00E8H A 184# P6MDOUT. . . . . . D ADDR 009EH A 90# P7 . . . . . . . . D ADDR 00F8H A 195# P7MDOUT. . . . . . D ADDR 009FH A 91# PCA0CN . . . . . . D ADDR 00D8H A 166# PCA0CPH0 . . . . . D ADDR 00FCH A 200# PCA0CPH1 . . . . . D ADDR 00FEH A 202# PCA0CPH2 . . . . . D ADDR 00EAH A 186# PCA0CPH3 . . . . . D ADDR 00ECH A 188# PCA0CPH4 . . . . . D ADDR 00EEH A 190# PCA0CPH5 . . . . . D ADDR 00E2H A 177# PCA0CPL0 . . . . . D ADDR 00FBH A 199# PCA0CPL1 . . . . . D ADDR 00FDH A 201# PCA0CPL2 . . . . . D ADDR 00E9H A 185# PCA0CPL3 . . . . . D ADDR 00EBH A 187# PCA0CPL4 . . . . . D ADDR 00EDH A 189# PCA0CPL5 . . . . . D ADDR 00E1H A 176# PCA0CPM0 . . . . . D ADDR 00DAH A 168# PCA0CPM1 . . . . . D ADDR 00DBH A 169# PCA0CPM2 . . . . . D ADDR 00DCH A 170# A51 MACRO ASSEMBLER INOUT32 04/25/2006 10:33:45 PAGE 11 PCA0CPM3 . . . . . D ADDR 00DDH A 171# PCA0CPM4 . . . . . D ADDR 00DEH A 172# PCA0CPM5 . . . . . D ADDR 00DFH A 173# PCA0H. . . . . . . D ADDR 00FAH A 198# PCA0L. . . . . . . D ADDR 00F9H A 197# PCA0MD . . . . . . D ADDR 00D9H A 167# PCA0_PAGE. . . . . N NUMB 0000H A 389# PCON . . . . . . . D ADDR 0087H A 48# PLL0CN . . . . . . D ADDR 0089H A 56# PLL0DIV. . . . . . D ADDR 008DH A 64# PLL0FLT. . . . . . D ADDR 008FH A 68# PLL0MUL. . . . . . D ADDR 008EH A 66# PLL0_PAGE. . . . . N NUMB 000FH A 390# PS . . . . . . . . B ADDR 00B8H.4 A 272# PSBANK . . . . . . D ADDR 00B1H A 107# PSCTL. . . . . . . D ADDR 008FH A 67# PSW. . . . . . . . D ADDR 00D0H A 157# PT0. . . . . . . . B ADDR 00B8H.1 A 275# PT1. . . . . . . . B ADDR 00B8H.3 A 273# PT2. . . . . . . . B ADDR 00B8H.5 A 271# PX0. . . . . . . . B ADDR 00B8H.0 A 276# PX1. . . . . . . . B ADDR 00B8H.2 A 274# RB80 . . . . . . . B ADDR 0098H.2 A 248# RB81 . . . . . . . B ADDR 0098H.2 A 257# RCAP2H . . . . . . D ADDR 00CBH A 145# RCAP2L . . . . . . D ADDR 00CAH A 142# RCAP3H . . . . . . D ADDR 00CBH A 146# RCAP3L . . . . . . D ADDR 00CAH A 143# RCAP4H . . . . . . D ADDR 00CBH A 147# RCAP4L . . . . . . D ADDR 00CAH A 144# REF0CN . . . . . . D ADDR 00D1H A 158# REN0 . . . . . . . B ADDR 0098H.4 A 246# REN1 . . . . . . . B ADDR 0098H.4 A 255# RI0. . . . . . . . B ADDR 0098H.0 A 250# RI1. . . . . . . . B ADDR 0098H.0 A 259# RS0. . . . . . . . B ADDR 00D0H.3 A 323# RS1. . . . . . . . B ADDR 00D0H.4 A 322# RSTSRC . . . . . . D ADDR 00EFH A 191# RXOVRN . . . . . . B ADDR 00F8H.4 A 362# S1MODE . . . . . . B ADDR 0098H.7 A 253# SADDR0 . . . . . . D ADDR 00A9H A 104# SADEN0 . . . . . . D ADDR 00B9H A 111# SBUF0. . . . . . . D ADDR 0099H A 82# SBUF1. . . . . . . D ADDR 0099H A 83# SCON0. . . . . . . D ADDR 0098H A 80# SCON1. . . . . . . D ADDR 0098H A 81# SFRLAST. . . . . . D ADDR 0086H A 47# SFRNEXT. . . . . . D ADDR 0085H A 46# SFRPAGE. . . . . . D ADDR 0084H A 45# 419 SFRPGCN. . . . . . D ADDR 0096H A 76# SI . . . . . . . . B ADDR 00C0H.3 A 283# SM00 . . . . . . . B ADDR 0098H.7 A 243# SM10 . . . . . . . B ADDR 0098H.6 A 244# SM20 . . . . . . . B ADDR 0098H.5 A 245# SMB0ADR. . . . . . D ADDR 00C3H A 128# SMB0CN . . . . . . D ADDR 00C0H A 122# SMB0CR . . . . . . D ADDR 00CFH A 156# SMB0DAT. . . . . . D ADDR 00C2H A 126# SMB0STA. . . . . . D ADDR 00C1H A 124# SMB0_PAGE. . . . . N NUMB 0000H A 383# SMBFTE . . . . . . B ADDR 00C0H.1 A 285# SMBTOE . . . . . . B ADDR 00C0H.0 A 286# SP . . . . . . . . D ADDR 0081H A 42# SPI0CFG. . . . . . D ADDR 009AH A 84# SPI0CKR. . . . . . D ADDR 009DH A 89# SPI0CN . . . . . . D ADDR 00F8H A 196# A51 MACRO ASSEMBLER INOUT32 04/25/2006 10:33:45 PAGE 12 SPI0DAT. . . . . . D ADDR 009BH A 86# SPI0_PAGE. . . . . N NUMB 0000H A 379# SPIEN. . . . . . . B ADDR 00F8H.0 A 366# SPIF . . . . . . . B ADDR 00F8H.7 A 359# SSTA0. . . . . . . D ADDR 0091H A 70# STA. . . . . . . . B ADDR 00C0H.5 A 281# STO. . . . . . . . B ADDR 00C0H.4 A 282# TB80 . . . . . . . B ADDR 0098H.3 A 247# TB81 . . . . . . . B ADDR 0098H.3 A 256# TCON . . . . . . . D ADDR 0088H A 52# TF0. . . . . . . . B ADDR 0088H.5 A 212# TF1. . . . . . . . B ADDR 0088H.7 A 210# TF2. . . . . . . . B ADDR 00C8H.7 A 295# TF3. . . . . . . . B ADDR 00C8H.7 A 303# TF4. . . . . . . . B ADDR 00C8H.7 A 311# TH0. . . . . . . . D ADDR 008CH A 62# TH1. . . . . . . . D ADDR 008DH A 63# TI0. . . . . . . . B ADDR 0098H.1 A 249# TI1. . . . . . . . B ADDR 0098H.1 A 258# TIMER01_PAGE . . . N NUMB 0000H A 374# TL0. . . . . . . . D ADDR 008AH A 58# TL1. . . . . . . . D ADDR 008BH A 60# TMOD . . . . . . . D ADDR 0089H A 53# TMR2CF . . . . . . D ADDR 00C9H A 139# TMR2CN . . . . . . D ADDR 00C8H A 136# TMR2H. . . . . . . D ADDR 00CDH A 151# TMR2L. . . . . . . D ADDR 00CCH A 148# TMR2_PAGE. . . . . N NUMB 0000H A 384# TMR3CF . . . . . . D ADDR 00C9H A 140# TMR3CN . . . . . . D ADDR 00C8H A 137# TMR3H. . . . . . . D ADDR 00CDH A 152# TMR3L. . . . . . . D ADDR 00CCH A 149# TMR3_PAGE. . . . . N NUMB 0001H A 385# TMR4CF . . . . . . D ADDR 00C9H A 141# TMR4CN . . . . . . D ADDR 00C8H A 138# TMR4H. . . . . . . D ADDR 00CDH A 153# TMR4L. . . . . . . D ADDR 00CCH A 150# TMR4_PAGE. . . . . N NUMB 0002H A 386# TR0. . . . . . . . B ADDR 0088H.4 A 213# TR1. . . . . . . . B ADDR 0088H.6 A 211# TR2. . . . . . . . B ADDR 00C8H.2 A 298# TR3. . . . . . . . B ADDR 00C8H.2 A 306# TR4. . . . . . . . B ADDR 00C8H.2 A 314# TXBMT. . . . . . . B ADDR 00F8H.1 A 365# UART0_PAGE . . . . N NUMB 0000H A 377# UART1_PAGE . . . . N NUMB 0001H A 378# WCOL . . . . . . . B ADDR 00F8H.6 A 360# WDTCN. . . . . . . D ADDR 00FFH A 203# XBR0 . . . . . . . D ADDR 00E1H A 175# XBR1 . . . . . . . D ADDR 00E2H A 178# XBR2 . . . . . . . D ADDR 00E3H A 179# 422 REGISTER BANK(S) USED: 0 ASSEMBLY COMPLETE. 0 WARNING(S), 0 ERROR(S)