A51 MACRO ASSEMBLER MEM_TEST 04/28/2006 09:23:49 PAGE 1 MACRO ASSEMBLER A51 V7.04a OBJECT MODULE PLACED IN mem_test.OBJ ASSEMBLER INVOKED BY: F:\SiLabs\MCU\IDEfiles\C51\BIN\a51.exe mem_test.asm XR GEN DB EP NOMOD51 LOC OBJ LINE SOURCE 1 ;----------------------------------------------------------------------------- 2 ; 3 ; 4/26/2006 sjd 4 ; 5 ; FILE NAME : MEM_TEST.ASM 6 ; TARGET MCU : C8051F120 7 ; DESCRIPTION : This program disables the watchdog timer and writes value in 8 ; acc A to address po inted to by DPTR in external SRAM on 9 ; plug-in board AB1. 10 ; 11 ; NOTES: 12 ; (1) /WE = P4.7 (/WR) 13 ; (2) /CE = P4.4 (J1 closed on AB1 board) 14 ; (3) /OE = P4.6 (/RD) 15 ; (4) D0-D7 = P7.0-P7.7 (DATA bus) 16 ; (5) A0-A7 = P6.0-P6.7 (ADR bus lo byte) 17 ; (6) A8-A15 = P5.0-P5.7 (ADR bus hi byte) 18 ; (7) A16 = P4.5 (BANK select) 19 ; 20 ; 21 ;----------------------------------------------------------------------------- 22 23 ;$include (c8051F120.inc) ; Include register definition file +1 24 ;--------------------------------------------------------------------------- +1 25 ; +1 26 ; +1 27 ; +1 28 ; +1 29 ; FILE NAME: C8051F120.INC +1 30 ; TARGET MCUs: C8051F120, F121, F122, F123, F124, F125, F126, F127 +1 31 ; DESCRIPTION: Register/bit definitions for the C8051F120 product family. +1 32 ; +1 33 ; REVISION 1.6 +1 34 ; +1 35 ;--------------------------------------------------------------------------- +1 36 +1 37 ;REGISTER DEFINITIONS +1 38 ; 0080 +1 39 P0 DATA 080H ; PORT 0 LATCH 0081 +1 40 SP DATA 081H ; STACK POINTER 0082 +1 41 DPL DATA 082H ; DATA POINTER LOW BYTE 0083 +1 42 DPH DATA 083H ; DATA POINTER HIGH BYTE 0084 +1 43 SFRPAGE DATA 084H ; SFR PAGE SELECT 0085 +1 44 SFRNEXT DATA 085H ; SFR STACK NEXT PAGE 0086 +1 45 SFRLAST DATA 086H ; SFR STACK LAST PAGE 0087 +1 46 PCON DATA 087H ; POWER CONTROL 0088 +1 47 FLSTAT DATA 088H ; FLASH STATUS 0088 +1 48 CPT0CN DATA 088H ; COMPARATOR 0 CONTROL 0088 +1 49 CPT1CN DATA 088H ; COMPARATOR 1 CONTROL 0088 +1 50 TCON DATA 088H ; TIMER/COUNTER CONTROL 0089 +1 51 TMOD DATA 089H ; TIMER/COUNTER MODE 0089 +1 52 CPT0MD DATA 089H ; COMPARATOR 0 CONFIGURATION 0089 +1 53 CPT1MD DATA 089H ; COMPARATOR 1 CONFIGURATION 0089 +1 54 PLL0CN DATA 089H ; PLL CONTROL 008A +1 55 OSCICN DATA 08AH ; INTERNAL OSCILLATOR CONTROL 008A +1 56 TL0 DATA 08AH ; TIMER/COUNTER 0 LOW BYTE 008B +1 57 OSCICL DATA 08BH ; INTERNAL OSCILLATOR CALIBRATION A51 MACRO ASSEMBLER MEM_TEST 04/28/2006 09:23:49 PAGE 2 008B +1 58 TL1 DATA 08BH ; TIMER/COUNTER 1 LOW BYTE 008C +1 59 OSCXCN DATA 08CH ; EXTERNAL OSCILLATOR CONTROL 008C +1 60 TH0 DATA 08CH ; TIMER/COUNTER 0 HIGH BYTE 008D +1 61 TH1 DATA 08DH ; TIMER/COUNTER 1 HIGH BYTE 008D +1 62 PLL0DIV DATA 08DH ; PLL DIVIDER 008E +1 63 CKCON DATA 08EH ; CLOCK CONTROL 008E +1 64 PLL0MUL DATA 08EH ; PLL MULTIPLIER 008F +1 65 PSCTL DATA 08FH ; FLASH WRITE/ERASE CONTROL 008F +1 66 PLL0FLT DATA 08FH ; PLL FILTER 0090 +1 67 P1 DATA 090H ; PORT 1 LATCH 0091 +1 68 SSTA0 DATA 091H ; UART 0 STATUS 0091 +1 69 MAC0BL DATA 091H ; MAC0 B REGISTER LOW BYTE 0092 +1 70 MAC0BH DATA 092H ; MAC0 B REGISTER HIGH BYTE 0093 +1 71 MAC0ACC0 DATA 093H ; MAC0 ACCUMULATOR BYTE 0 0094 +1 72 MAC0ACC1 DATA 094H ; MAC0 ACCUMULATOR BYTE 1 0095 +1 73 MAC0ACC2 DATA 095H ; MAC0 ACCUMULATOR BYTE 2 0096 +1 74 SFRPGCN DATA 096H ; SFR PAGE CONTROL 0096 +1 75 MAC0ACC3 DATA 096H ; MAC0 ACCUMULATOR BYTE 3 0097 +1 76 MAC0OVR DATA 097H ; MAC0 ACCUMULATOR OVERFLOW BYTE 0097 +1 77 CLKSEL DATA 097H ; SYSTEM CLOCK SELECT 0098 +1 78 SCON0 DATA 098H ; UART 0 CONTROL 0098 +1 79 SCON1 DATA 098H ; UART 1 CONTROL 0099 +1 80 SBUF0 DATA 099H ; UART 0 DATA BUFFER 0099 +1 81 SBUF1 DATA 099H ; UART 1 DATA BUFFER 009A +1 82 SPI0CFG DATA 09AH ; SPI CONFIGURATION 009A +1 83 CCH0MA DATA 09AH ; CACHE MISS ACCUMULATOR 009B +1 84 SPI0DAT DATA 09BH ; SPI DATA 009C +1 85 P4MDOUT DATA 09CH ; PORT 4 OUTPUT MODE CONFIGURATION 009D +1 86 P5MDOUT DATA 09DH ; PORT 5 OUTPUT MODE CONFIGURATION 009D +1 87 SPI0CKR DATA 09DH ; SPI CLOCK RATE CONTROL 009E +1 88 P6MDOUT DATA 09EH ; PORT 6 OUTPUT MODE CONFIGURATION 009F +1 89 P7MDOUT DATA 09FH ; PORT 7 OUTPUT MODE CONFIGURATION 00A0 +1 90 P2 DATA 0A0H ; PORT 2 LATCH 00A1 +1 91 EMI0TC DATA 0A1H ; EMIF TIMING CONTROL 00A1 +1 92 CCH0CN DATA 0A1H ; CACHE CONTROL 00A2 +1 93 EMI0CN DATA 0A2H ; EMIF CONTROL 00A2 +1 94 CCH0TN DATA 0A2H ; CACHE TUNING 00A3 +1 95 EMI0CF DATA 0A3H ; EMIF CONFIGURATION 00A3 +1 96 CCH0LC DATA 0A3H ; CACHE LOCK 00A4 +1 97 P0MDOUT DATA 0A4H ; PORT 0 OUTPUT MODE CONFIGURATION 00A5 +1 98 P1MDOUT DATA 0A5H ; PORT 1 OUTPUT MODE CONFIGURATION 00A6 +1 99 P2MDOUT DATA 0A6H ; PORT 2 OUTPUT MODE CONFIGURATION 00A7 +1 100 P3MDOUT DATA 0A7H ; PORT 3 OUTPUT MODE CONFIGURATION 00A8 +1 101 IE DATA 0A8H ; INTERRUPT ENABLE 00A9 +1 102 SADDR0 DATA 0A9H ; UART 0 SLAVE ADDRESS 00AD +1 103 P1MDIN DATA 0ADH ; PORT 1 INPUT MODE 00B0 +1 104 P3 DATA 0B0H ; PORT 3 LATCH 00B1 +1 105 PSBANK DATA 0B1H ; FLASH BANK SELECT 00B7 +1 106 FLACL DATA 0B7H ; FLASH ACCESS LIMIT 00B7 +1 107 FLSCL DATA 0B7H ; FLASH SCALE 00B8 +1 108 IP DATA 0B8H ; INTERRUPT PRIORITY 00B9 +1 109 SADEN0 DATA 0B9H ; UART 0 SLAVE ADDRESS MASK 00BA +1 110 AMX0CF DATA 0BAH ; ADC0 MULTIPLEXER CONFIGURATION 00BA +1 111 AMX2CF DATA 0BAH ; ADC2 MULTIPLEXER CONFIGURATION 00BB +1 112 AMX0SL DATA 0BBH ; ADC0 MULTIPLEXER CHANNEL SELECT 00BB +1 113 AMX2SL DATA 0BBH ; ADC2 MULTIPLEXER CHANNEL SELECT 00BC +1 114 ADC0CF DATA 0BCH ; ADC0 CONFIGURATION 00BC +1 115 ADC2CF DATA 0BCH ; ADC2 CONFIGURATION 00BE +1 116 ADC0L DATA 0BEH ; ADC0 DATA WORD LOW BYTE 00BE +1 117 ADC2 DATA 0BEH ; ADC2DATA WORD 00BF +1 118 ADC0H DATA 0BFH ; ADC0 DATA WORD HIGH BYTE 00C0 +1 119 MAC0STA DATA 0C0H ; MAC0 STATUS 00C0 +1 120 SMB0CN DATA 0C0H ; SMBUS CONTROL 00C1 +1 121 MAC0AL DATA 0C1H ; MAC0 A REGISTER LOW BYTE 00C1 +1 122 SMB0STA DATA 0C1H ; SMBUS STATUS 00C2 +1 123 MAC0AH DATA 0C2H ; MAC0 A REGISTER HIGH BYTE A51 MACRO ASSEMBLER MEM_TEST 04/28/2006 09:23:49 PAGE 3 00C2 +1 124 SMB0DAT DATA 0C2H ; SMBUS DATA 00C3 +1 125 MAC0CF DATA 0C3H ; MAC0 CONFIGURATION REGISTER 00C3 +1 126 SMB0ADR DATA 0C3H ; SMBUS SLAVE ADDRESS 00C4 +1 127 ADC0GTL DATA 0C4H ; ADC0 GREATER-THAN LOW BYTE 00C4 +1 128 ADC2GT DATA 0C4H ; ADC2 GREATER-THAN 00C5 +1 129 ADC0GTH DATA 0C5H ; ADC0 GREATER-THAN HIGH BYTE 00C6 +1 130 ADC0LTL DATA 0C6H ; ADC0 LESS-THAN LOW BYTE 00C6 +1 131 ADC2LT DATA 0C6H ; ADC2 LESS-THAN 00C7 +1 132 ADC0LTH DATA 0C7H ; ADC0 LESS-THAN HIGH BYTE 00C8 +1 133 P4 DATA 0C8H ; PORT 4 LATCH 00C8 +1 134 TMR2CN DATA 0C8H ; TIMER/COUNTER 2 CONTROL 00C8 +1 135 TMR3CN DATA 0C8H ; TIMER 3 CONTROL 00C8 +1 136 TMR4CN DATA 0C8H ; TIMER/COUNTER 4 CONTROL 00C9 +1 137 TMR2CF DATA 0C9H ; TIMER/COUNTER 2 CONFIGURATION 00C9 +1 138 TMR3CF DATA 0C9H ; TIMER 3 CONFIGURATION 00C9 +1 139 TMR4CF DATA 0C9H ; TIMER/COUNTER 4 CONFIGURATION 00CA +1 140 RCAP2L DATA 0CAH ; TIMER/COUNTER 2 CAPTURE/RELOAD LOW BYTE 00CA +1 141 RCAP3L DATA 0CAH ; TIMER 3 CAPTURE/RELOAD LOW BYTE 00CA +1 142 RCAP4L DATA 0CAH ; TIMER/COUNTER 4 CAPTURE/RELOAD LOW BYTE 00CB +1 143 RCAP2H DATA 0CBH ; TIMER/COUNTER 2 CAPTURE/RELOAD HIGH BYTE 00CB +1 144 RCAP3H DATA 0CBH ; TIMER 3 CAPTURE/RELOAD HIGH BYTE 00CB +1 145 RCAP4H DATA 0CBH ; TIMER/COUNTER 4 CAPTURE/RELOAD HIGH BYTE 00CC +1 146 TMR2L DATA 0CCH ; TIMER/COUNTER 2 LOW BYTE 00CC +1 147 TMR3L DATA 0CCH ; TIMER 3 LOW BYTE 00CC +1 148 TMR4L DATA 0CCH ; TIMER/COUNTER 4 LOW BYTE 00CD +1 149 TMR2H DATA 0CDH ; TIMER/COUNTER 2 HIGH BYTE 00CD +1 150 TMR3H DATA 0CDH ; TIMER 3 HIGH BYTE 00CD +1 151 TMR4H DATA 0CDH ; TIMER/COUNTER 4 HIGH BYTE 00CE +1 152 MAC0RNDL DATA 0CEH ; MAC0 ROUNDING REGISTER LOW BYTE 00CF +1 153 MAC0RNDH DATA 0CFH ; MAC0 ROUNDING REGISTER HIGH BYTE 00CF +1 154 SMB0CR DATA 0CFH ; SMBUS CLOCK RATE 00D0 +1 155 PSW DATA 0D0H ; PROGRAM STATUS WORD 00D1 +1 156 REF0CN DATA 0D1H ; VOLTAGE REFERENCE CONTROL 00D2 +1 157 DAC0L DATA 0D2H ; DAC0 LOW BYTE 00D2 +1 158 DAC1L DATA 0D2H ; DAC1 LOW BYTE 00D3 +1 159 DAC0H DATA 0D3H ; DAC0 HIGH BYTE 00D3 +1 160 DAC1H DATA 0D3H ; DAC1 HIGH BYTE 00D4 +1 161 DAC0CN DATA 0D4H ; DAC0 CONTROL 00D4 +1 162 DAC1CN DATA 0D4H ; DAC1 CONTROL 00D8 +1 163 P5 DATA 0D8H ; PORT 5 LATCH 00D8 +1 164 PCA0CN DATA 0D8H ; PCA CONTROL 00D9 +1 165 PCA0MD DATA 0D9H ; PCA MODE 00DA +1 166 PCA0CPM0 DATA 0DAH ; PCA MODULE 0 MODE 00DB +1 167 PCA0CPM1 DATA 0DBH ; PCA MODULE 1 MODE REGISTER 00DC +1 168 PCA0CPM2 DATA 0DCH ; PCA MODULE 2 MODE 00DD +1 169 PCA0CPM3 DATA 0DDH ; PCA MODULE 3 MODE 00DE +1 170 PCA0CPM4 DATA 0DEH ; PCA MODULE 4 MODE 00DF +1 171 PCA0CPM5 DATA 0DFH ; PCA MODULE 5 MODE 00E0 +1 172 ACC DATA 0E0H ; ACCUMULATOR 00E1 +1 173 XBR0 DATA 0E1H ; PORT I/O CROSSBAR CONTROL 0 00E1 +1 174 PCA0CPL5 DATA 0E1H ; PCA MODULE 5 CAPTURE/COMPARE LOW BYTE 00E2 +1 175 PCA0CPH5 DATA 0E2H ; PCA MODULE 5 CAPTURE/COMPARE HIGH BYTE 00E2 +1 176 XBR1 DATA 0E2H ; PORT I/O CROSSBAR CONTROL 1 00E3 +1 177 XBR2 DATA 0E3H ; PORT I/O CROSSBAR CONTROL 2 00E6 +1 178 EIE1 DATA 0E6H ; EXTENDED INTERRUPT ENABLE 1 00E7 +1 179 EIE2 DATA 0E7H ; EXTENDED INTERRUPT ENABLE 2 00E8 +1 180 ADC0CN DATA 0E8H ; ADC0 CONTROL 00E8 +1 181 ADC2CN DATA 0E8H ; ADC2 CONTROL 00E8 +1 182 P6 DATA 0E8H ; PORT 6 LATCH 00E9 +1 183 PCA0CPL2 DATA 0E9H ; PCA MODULE 2 CAPTURE/COMPARE LOW BYTE 00EA +1 184 PCA0CPH2 DATA 0EAH ; PCA MODULE 2 CAPTURE/COMPARE HIGH BYTE 00EB +1 185 PCA0CPL3 DATA 0EBH ; PCA MODULE 3 CAPTURE/COMPARE LOW BYTE 00EC +1 186 PCA0CPH3 DATA 0ECH ; PCA MODULE 3 CAPTURE/COMPARE HIGH BYTE 00ED +1 187 PCA0CPL4 DATA 0EDH ; PCA MODULE 4 CAPTURE/COMPARE LOW BYTE 00EE +1 188 PCA0CPH4 DATA 0EEH ; PCA MODULE 4 CAPTURE/COMPARE HIGH BYTE 00EF +1 189 RSTSRC DATA 0EFH ; RESET SOURCE A51 MACRO ASSEMBLER MEM_TEST 04/28/2006 09:23:49 PAGE 4 00F0 +1 190 B DATA 0F0H ; B REGISTER 00F6 +1 191 EIP1 DATA 0F6H ; EXTERNAL INTERRUPT PRIORITY 1 00F7 +1 192 EIP2 DATA 0F7H ; EXTERNAL INTERRUPT PRIORITY 2 00F8 +1 193 P7 DATA 0F8H ; PORT 7 LATCH 00F8 +1 194 SPI0CN DATA 0F8H ; SPI CONTROL 00F9 +1 195 PCA0L DATA 0F9H ; PCA COUNTER LOW BYTE 00FA +1 196 PCA0H DATA 0FAH ; PCA COUNTER HIGH BYTE 00FB +1 197 PCA0CPL0 DATA 0FBH ; PCA MODULE 0 CAPTURE/COMPARE LOW BYTE 00FC +1 198 PCA0CPH0 DATA 0FCH ; PCA MODULE 0 CAPTURE/COMPARE HIGH BYTE 00FD +1 199 PCA0CPL1 DATA 0FDH ; PCA MODULE 1 CAPTURE/COMPARE LOW BYTE 00FE +1 200 PCA0CPH1 DATA 0FEH ; PCA MODULE 1 CAPTURE/COMPARE HIGH BYTE 00FF +1 201 WDTCN DATA 0FFH ; WATCHDOG TIMER CONTROL +1 202 +1 203 ; +1 204 ;------------------------------------------------------------------------------ +1 205 ;BIT DEFINITIONS +1 206 ; +1 207 ; TCON 088H 008F +1 208 TF1 BIT 08FH ; TIMER 1 OVERFLOW FLAG 008E +1 209 TR1 BIT 08EH ; TIMER 1 ON/OFF CONTROL 008D +1 210 TF0 BIT 08DH ; TIMER 0 OVERFLOW FLAG 008C +1 211 TR0 BIT 08CH ; TIMER 0 ON/OFF CONTROL 008B +1 212 IE1 BIT 08BH ; EXT. INTERRUPT 1 EDGE FLAG 008A +1 213 IT1 BIT 08AH ; EXT. INTERRUPT 1 TYPE 0089 +1 214 IE0 BIT 089H ; EXT. INTERRUPT 0 EDGE FLAG 0088 +1 215 IT0 BIT 088H ; EXT. INTERRUPT 0 TYPE +1 216 +1 217 ; CPT0CN 088H 008F +1 218 CP0EN BIT 08FH ; COMPARATOR 0 ENABLE 008E +1 219 CP0OUT BIT 08EH ; COMPARATOR 0 OUTPUT 008D +1 220 CP0RIF BIT 08DH ; COMPARATOR 0 RISING EDGE INTERRUPT 008C +1 221 CP0FIF BIT 08CH ; COMPARATOR 0 FALLING EDGE INTERRUPT 008B +1 222 CP0HYP1 BIT 08BH ; COMPARATOR 0 POSITIVE HYSTERISIS 1 008A +1 223 CP0HYP0 BIT 08AH ; COMPARATOR 0 POSITIVE HYSTERISIS 0 0089 +1 224 CP0HYN1 BIT 089H ; COMPARATOR 0 NEGATIVE HYSTERISIS 1 0088 +1 225 CP0HYN0 BIT 088H ; COMPARATOR 0 NEGATIVE HYSTERISIS 0 +1 226 +1 227 ; CPT1CN 088H 008F +1 228 CP1EN BIT 08FH ; COMPARATOR 1 ENABLE 008E +1 229 CP1OUT BIT 08EH ; COMPARATOR 1 OUTPUT 008D +1 230 CP1RIF BIT 08DH ; COMPARATOR 1 RISING EDGE INTERRUPT 008C +1 231 CP1FIF BIT 08CH ; COMPARATOR 1 FALLING EDGE INTERRUPT 008B +1 232 CP1HYP1 BIT 08BH ; COMPARATOR 1 POSITIVE HYSTERISIS 1 008A +1 233 CP1HYP0 BIT 08AH ; COMPARATOR 1 POSITIVE HYSTERISIS 0 0089 +1 234 CP1HYN1 BIT 089H ; COMPARATOR 1 NEGATIVE HYSTERISIS 1 0088 +1 235 CP1HYN0 BIT 088H ; COMPARATOR 1 NEGATIVE HYSTERISIS 0 +1 236 +1 237 ; FLSTAT 088H 0088 +1 238 FLHBUSY BIT 088H ; FLASH BUSY +1 239 +1 240 ; SCON0 098H 009F +1 241 SM00 BIT 09FH ; UART 0 MODE 0 009E +1 242 SM10 BIT 09EH ; UART 0 MODE 1 009D +1 243 SM20 BIT 09DH ; UART 0 MULTIPROCESSOR EN 009C +1 244 REN0 BIT 09CH ; UART 0 RX ENABLE 009B +1 245 TB80 BIT 09BH ; UART 0 TX BIT 8 009A +1 246 RB80 BIT 09AH ; UART 0 RX BIT 8 0099 +1 247 TI0 BIT 099H ; UART 0 TX INTERRUPT FLAG 0098 +1 248 RI0 BIT 098H ; UART 0 RX INTERRUPT FLAG +1 249 +1 250 ; SCON1 098H 009F +1 251 S1MODE BIT 09FH ; UART 1 MODE 009D +1 252 MCE1 BIT 09DH ; UART 1 MCE 009C +1 253 REN1 BIT 09CH ; UART 1 RX ENABLE 009B +1 254 TB81 BIT 09BH ; UART 1 TX BIT 8 009A +1 255 RB81 BIT 09AH ; UART 1 RX BIT 8 A51 MACRO ASSEMBLER MEM_TEST 04/28/2006 09:23:49 PAGE 5 0099 +1 256 TI1 BIT 099H ; UART 1 TX INTERRUPT FLAG 0098 +1 257 RI1 BIT 098H ; UART 1 RX INTERRUPT FLAG +1 258 +1 259 ; IE 0A8H 00AF +1 260 EA BIT 0AFH ; GLOBAL INTERRUPT ENABLE 00AD +1 261 ET2 BIT 0ADH ; TIMER 2 INTERRUPT ENABLE 00AC +1 262 ES0 BIT 0ACH ; UART0 INTERRUPT ENABLE 00AB +1 263 ET1 BIT 0ABH ; TIMER 1 INTERRUPT ENABLE 00AA +1 264 EX1 BIT 0AAH ; EXTERNAL INTERRUPT 1 ENABLE 00A9 +1 265 ET0 BIT 0A9H ; TIMER 0 INTERRUPT ENABLE 00A8 +1 266 EX0 BIT 0A8H ; EXTERNAL INTERRUPT 0 ENABLE +1 267 +1 268 ; IP 0B8H 00BD +1 269 PT2 BIT 0BDH ; TIMER 2 PRIORITY 00BC +1 270 PS BIT 0BCH ; SERIAL PORT PRIORITY 00BB +1 271 PT1 BIT 0BBH ; TIMER 1 PRIORITY 00BA +1 272 PX1 BIT 0BAH ; EXTERNAL INTERRUPT 1 PRIORITY 00B9 +1 273 PT0 BIT 0B9H ; TIMER 0 PRIORITY 00B8 +1 274 PX0 BIT 0B8H ; EXTERNAL INTERRUPT 0 PRIORITY +1 275 +1 276 ; SMB0CN 0C0H 00C7 +1 277 BUSY BIT 0C7H ; SMBUS 0 BUSY 00C6 +1 278 ENSMB BIT 0C6H ; SMBUS 0 ENABLE 00C5 +1 279 STA BIT 0C5H ; SMBUS 0 START FLAG 00C4 +1 280 STO BIT 0C4H ; SMBUS 0 STOP FLAG 00C3 +1 281 SI BIT 0C3H ; SMBUS 0 INTERRUPT PENDING FLAG 00C2 +1 282 AA BIT 0C2H ; SMBUS 0 ASSERT/ACKNOWLEDGE FLAG 00C1 +1 283 SMBFTE BIT 0C1H ; SMBUS 0 FREE TIMER ENABLE 00C0 +1 284 SMBTOE BIT 0C0H ; SMBUS 0 TIMEOUT ENABLE +1 285 +1 286 ; MAC0STA 0C0H 00C3 +1 287 MAC0HO BIT 0C3H ; MAC0 HARD OVERFLOW 00C2 +1 288 MAC0Z BIT 0C2H ; MAC0 ZERO 00C1 +1 289 MAC0SO BIT 0C1H ; MAC0 SOFT OVERFLOW 00C0 +1 290 MAC0N BIT 0C0H ; MAC0 NEGATIVE +1 291 +1 292 ; TMR2CN 0C8H 00CF +1 293 TF2 BIT 0CFH ; TIMER 2 OVERFLOW FLAG 00CE +1 294 EXF2 BIT 0CEH ; TIMER 2 EXTERNAL FLAG 00CB +1 295 EXEN2 BIT 0CBH ; TIMER 2 EXTERNAL ENABLE FLAG 00CA +1 296 TR2 BIT 0CAH ; TIMER 2 ON/OFF CONTROL 00C9 +1 297 CT2 BIT 0C9H ; TIMER 2 COUNTER SELECT 00C8 +1 298 CPRL2 BIT 0C8H ; TIMER 2 CAPTURE SELECT +1 299 +1 300 ; TMR3CN 0C8H 00CF +1 301 TF3 BIT 0CFH ; TIMER 3 OVERFLOW FLAG 00CE +1 302 EXF3 BIT 0CEH ; TIMER 3 EXTERNAL FLAG 00CB +1 303 EXEN3 BIT 0CBH ; TIMER 3 EXTERNAL ENABLE FLAG 00CA +1 304 TR3 BIT 0CAH ; TIMER 3 ON/OFF CONTROL 00C9 +1 305 CT3 BIT 0C9H ; TIMER 3 COUNTER SELECT 00C8 +1 306 CPRL3 BIT 0C8H ; TIMER 3 CAPTURE SELECT +1 307 +1 308 ; TMR4CN 0C8H 00CF +1 309 TF4 BIT 0CFH ; TIMER 4 OVERFLOW FLAG 00CE +1 310 EXF4 BIT 0CEH ; TIMER 4 EXTERNAL FLAG 00CB +1 311 EXEN4 BIT 0CBH ; TIMER 4 EXTERNAL ENABLE FLAG 00CA +1 312 TR4 BIT 0CAH ; TIMER 4 ON/OFF CONTROL 00C9 +1 313 CT4 BIT 0C9H ; TIMER 4 COUNTER SELECT 00C8 +1 314 CPRL4 BIT 0C8H ; TIMER 4 CAPTURE SELECT +1 315 +1 316 ; PSW 0D0H 00D7 +1 317 CY BIT 0D7H ; CARRY FLAG 00D6 +1 318 AC BIT 0D6H ; AUXILIARY CARRY FLAG 00D5 +1 319 F0 BIT 0D5H ; USER FLAG 0 00D4 +1 320 RS1 BIT 0D4H ; REGISTER BANK SELECT 1 00D3 +1 321 RS0 BIT 0D3H ; REGISTER BANK SELECT 0 A51 MACRO ASSEMBLER MEM_TEST 04/28/2006 09:23:49 PAGE 6 00D2 +1 322 OV BIT 0D2H ; OVERFLOW FLAG 00D1 +1 323 F1 BIT 0D1H ; USER FLAG 1 00D0 +1 324 P BIT 0D0H ; ACCUMULATOR PARITY FLAG +1 325 +1 326 ; PCA0CN 0D8H 00DF +1 327 CF BIT 0DFH ; PCA 0 COUNTER OVERFLOW FLAG 00DE +1 328 CR BIT 0DEH ; PCA 0 COUNTER RUN CONTROL BIT 00DD +1 329 CCF5 BIT 0DDH ; PCA 0 MODULE 5 INTERRUPT FLAG 00DC +1 330 CCF4 BIT 0DCH ; PCA 0 MODULE 4 INTERRUPT FLAG 00DB +1 331 CCF3 BIT 0DBH ; PCA 0 MODULE 3 INTERRUPT FLAG 00DA +1 332 CCF2 BIT 0DAH ; PCA 0 MODULE 2 INTERRUPT FLAG 00D9 +1 333 CCF1 BIT 0D9H ; PCA 0 MODULE 1 INTERRUPT FLAG 00D8 +1 334 CCF0 BIT 0D8H ; PCA 0 MODULE 0 INTERRUPT FLAG +1 335 +1 336 ; ADC0CN 0E8H 00EF +1 337 AD0EN BIT 0EFH ; ADC 0 ENABLE 00EE +1 338 AD0TM BIT 0EEH ; ADC 0 TRACK MODE 00ED +1 339 AD0INT BIT 0EDH ; ADC 0 EOC INTERRUPT FLAG 00EC +1 340 AD0BUSY BIT 0ECH ; ADC 0 BUSY FLAG 00EB +1 341 AD0CM1 BIT 0EBH ; ADC 0 CONVERT START MODE BIT 1 00EA +1 342 AD0CM0 BIT 0EAH ; ADC 0 CONVERT START MODE BIT 0 00E9 +1 343 AD0WINT BIT 0E9H ; ADC 0 WINDOW INTERRUPT FLAG 00E8 +1 344 AD0LJST BIT 0E8H ; ADC 0 LEFT JUSTIFY DATA BIT +1 345 +1 346 ; ADC2CN 0E8H 00EF +1 347 AD2EN BIT 0EFH ; ADC 2 ENABLE 00EE +1 348 AD2TM BIT 0EEH ; ADC 2 TRACK MODE 00ED +1 349 AD2INT BIT 0EDH ; ADC 2 EOC INTERRUPT FLAG 00EC +1 350 AD2BUSY BIT 0ECH ; ADC 2 BUSY FLAG 00EB +1 351 AD2CM2 BIT 0EBH ; ADC 2 CONVERT START MODE BIT 2 00EA +1 352 AD2CM1 BIT 0EAH ; ADC 2 CONVERT START MODE BIT 1 00E9 +1 353 AD2CM0 BIT 0E9H ; ADC 2 CONVERT START MODE BIT 0 00E8 +1 354 AD2WINT BIT 0E8H ; ADC 2 WINDOW INTERRUPT FLAG +1 355 +1 356 ; SPI0CN 0F8H 00FF +1 357 SPIF BIT 0FFH ; SPI 0 INTERRUPT FLAG 00FE +1 358 WCOL BIT 0FEH ; SPI 0 WRITE COLLISION FLAG 00FD +1 359 MODF BIT 0FDH ; SPI 0 MODE FAULT FLAG 00FC +1 360 RXOVRN BIT 0FCH ; SPI 0 RX OVERRUN FLAG 00FB +1 361 NSSMD1 BIT 0FBH ; SPI 0 SLAVE SELECT MODE 1 00FA +1 362 NSSMD0 BIT 0FAH ; SPI 0 SLAVE SELECT MODE 0 00F9 +1 363 TXBMT BIT 0F9H ; SPI 0 TX BUFFER EMPTY FLAG 00F8 +1 364 SPIEN BIT 0F8H ; SPI 0 SPI ENABLE +1 365 +1 366 ; +1 367 ;------------------------------------------------------------------------------ +1 368 ; SFR PAGE DEFINITIONS +1 369 ; 000F +1 370 CONFIG_PAGE EQU 0FH ; SYSTEM AND PORT CONFIGURATION PAGE 0000 +1 371 LEGACY_PAGE EQU 00H ; LEGACY SFR PAGE 0000 +1 372 TIMER01_PAGE EQU 00H ; TIMER 0 AND TIMER 1 0001 +1 373 CPT0_PAGE EQU 01H ; COMPARATOR 0 0002 +1 374 CPT1_PAGE EQU 02H ; COMPARATOR 1 0000 +1 375 UART0_PAGE EQU 00H ; UART 0 0001 +1 376 UART1_PAGE EQU 01H ; UART 1 0000 +1 377 SPI0_PAGE EQU 00H ; SPI 0 0000 +1 378 EMI0_PAGE EQU 00H ; EXTERNAL MEMORY INTERFACE 0000 +1 379 ADC0_PAGE EQU 00H ; ADC 0 0002 +1 380 ADC2_PAGE EQU 02H ; ADC 2 0000 +1 381 SMB0_PAGE EQU 00H ; SMBUS 0 0000 +1 382 TMR2_PAGE EQU 00H ; TIMER 2 0001 +1 383 TMR3_PAGE EQU 01H ; TIMER 3 0002 +1 384 TMR4_PAGE EQU 02H ; TIMER 4 0000 +1 385 DAC0_PAGE EQU 00H ; DAC 0 0001 +1 386 DAC1_PAGE EQU 01H ; DAC 1 0000 +1 387 PCA0_PAGE EQU 00H ; PCA 0 A51 MACRO ASSEMBLER MEM_TEST 04/28/2006 09:23:49 PAGE 7 000F +1 388 PLL0_PAGE EQU 0FH ; PLL 0 0003 +1 389 MAC0_PAGE EQU 03H ; MAC 0 390 391 ;----------------------------------------------------------------------------- 392 ; EQUATES 393 ;----------------------------------------------------------------------------- 394 395 396 ;----------------------------------------------------------------------------- 397 ; VARIABLES 398 ;----------------------------------------------------------------------------- 399 400 401 ;----------------------------------------------------------------------------- 402 ; RESET and INTERRUPT VECTORS 403 ;----------------------------------------------------------------------------- 404 405 ; Reset Vector 0000 406 org 00h 0000 020003 407 ljmp Main 408 409 ;----------------------------------------------------------------------------- 410 ; CODE SEGMENT 411 ;----------------------------------------------------------------------------- 412 0003 413 Main: ; Disable the WDT. (IRQs not enabled at this point.) 414 ; If interrupts were enabled, we would need to explicitly 415 ; disable them so that the 2nd move to WDTCN occurs no more 416 ; than four clock cycles after the first move to WDTCN. 417 0003 75FFDE 418 mov WDTCN, #0DEh 0006 75FFAD 419 mov WDTCN, #0ADh 420 421 ; Use SFRs on Configuration Page 0009 75840F 422 mov SFRPAGE, #CONFIG_PAGE 423 424 ; set up the XBAR 000C 75E342 425 mov XBR2, #42h ; weak pull-ups, XBAR enabl ed, non-multiplexed mode 426 427 ; set SFRs to Legacy Page 000F 758400 428 mov SFRPAGE, #LEGACY_PAGE 0012 75A33F 429 mov EMI0CF, #3Fh ; EMIF active on P4-P7, EMIF in non -multi- 430 ; plexed mode, external XRAM only 431 ; Use SFRs on Configuration Page 432 ; Must be in Configuration Page to read/write to I/O ports 0015 75840F 433 mov SFRPAGE, #CONFIG_PAGE 434 0018 74CF 435 start: mov A, #0CFh ; clr P4.4 for /CE, P4.5 lo for lower 64k of 436 ; external 128k SRAM (bank1) 001A F5C8 437 mov P4, A ; enable ex ternal /CE & lower 64k SRAM 001C E4 438 clr A 001D 7855 439 mov R0, #055h ; value to write into SRAM 001F E8 440 mov A, R0 ; load writ e value 0020 900000 441 mov DPTR, #0000h ; start at addr $00000 0023 F0 442 loop: movx @DPTR, A ; write to SRAM 0024 E0 443 movx A, @DPTR ; read SRAM value 0025 B50056 444 cjne A, 00h, error ; compare rd/wr, jump if error A51 MACRO ASSEMBLER MEM_TEST 04/28/2006 09:23:49 PAGE 8 0028 A3 445 inc DPTR 0029 E583 446 mov A, DPH 002B 4582 447 orl A, DPL 002D 6003 448 jz b155done 002F E8 449 mov A, R0 0030 80F1 450 jmp loop 451 0032 74EF 452 b155done: mov A, #0EFh ; clr P4.4 for /CE, P4.5 hi for upper 64k of 453 ; external 128k SRAM (bank2) 0034 F5C8 454 mov P4, A ; enable ex ternal /CE & upper 64K SRAM 0036 E4 455 clr A 0037 E8 456 mov A, R0 0038 900000 457 mov DPTR, #0000h ; start at addr $10000 003B F0 458 loop1: movx @DPTR, A 003C E0 459 movx A, @DPTR ; read SRAM value 003D B5003E 460 cjne A, 00h, error ; compare rd/wr, jump if error 0040 A3 461 inc DPTR 0041 E583 462 mov A, DPH 0043 4582 463 orl A, DPL 0045 6003 464 jz b255done 0047 E8 465 mov A, R0 0048 80F1 466 jmp loop1 467 004A 74CF 468 b255done: mov A, #0CFh ; clr P4.4 for /CE, P4.5 lo for lower 64k of 469 ; external 128k SRAM (bank1) 004C F5C8 470 mov P4, A ; enable ex ternal /CE & lower 64k SRAM 004E E4 471 clr A 004F 78AA 472 mov R0, #0AAh ; value to write into SRAM 0051 E8 473 mov A, R0 ; load writ e value 0052 900000 474 mov DPTR, #0000h ; start at addr $00000 0055 F0 475 loop2: movx @DPTR, A 0056 E0 476 movx A, @DPTR ; read SRAM value 0057 B50024 477 cjne A, 00h, error ; compare rd/wr, jump if error 005A A3 478 inc DPTR 005B E583 479 mov A, DPH 005D 4582 480 orl A, DPL 005F 6003 481 jz b1AAdone 0061 E8 482 mov A, R0 0062 80F1 483 jmp loop2 484 0064 74EF 485 b1AAdone: mov A, #0EFh ; clr P4.4 for /CE, P4.5 hi for upper 64k of 486 ; external 128k SRAM (bank2) 0066 F5C8 487 mov P4, A ; enable ex ternal /CE & upper 64K SRAM 0068 E4 488 clr A 0069 E8 489 mov A, R0 006A 900000 490 mov DPTR, #0000h ; start at addr $10000 006D F0 491 loop3: movx @DPTR, A 006E E0 492 movx A, @DPTR ; read SRAM value 006F B5000C 493 cjne A, 00h, error ; compare rd/wr, jump if error 0072 A3 494 inc DPTR 0073 E583 495 mov A, DPH 0075 4582 496 orl A, DPL 0077 6003 497 jz b2AAdone 0079 E8 498 mov A, R0 007A 80F1 499 jmp loop3 500 A51 MACRO ASSEMBLER MEM_TEST 04/28/2006 09:23:49 PAGE 9 007C 809A 501 b2AAdone: jmp start 007E 80FE 502 error: jmp $ ; error occured 503 504 505 ;----------------------------------------------------------------------------- 506 ; End of file. 507 508 END A51 MACRO ASSEMBLER MEM_TEST 04/28/2006 09:23:49 PAGE 10 XREF SYMBOL TABLE LISTING ---- ------ ----- ------- N A M E T Y P E V A L U E ATTRIBUTES / REFERENCES AA . . . . . . . . B ADDR 00C0H.2 A 282# AC . . . . . . . . B ADDR 00D0H.6 A 318# ACC. . . . . . . . D ADDR 00E0H A 172# AD0BUSY. . . . . . B ADDR 00E8H.4 A 340# AD0CM0 . . . . . . B ADDR 00E8H.2 A 342# AD0CM1 . . . . . . B ADDR 00E8H.3 A 341# AD0EN. . . . . . . B ADDR 00E8H.7 A 337# AD0INT . . . . . . B ADDR 00E8H.5 A 339# AD0LJST. . . . . . B ADDR 00E8H.0 A 344# AD0TM. . . . . . . B ADDR 00E8H.6 A 338# AD0WINT. . . . . . B ADDR 00E8H.1 A 343# AD2BUSY. . . . . . B ADDR 00E8H.4 A 350# AD2CM0 . . . . . . B ADDR 00E8H.1 A 353# AD2CM1 . . . . . . B ADDR 00E8H.2 A 352# AD2CM2 . . . . . . B ADDR 00E8H.3 A 351# AD2EN. . . . . . . B ADDR 00E8H.7 A 347# AD2INT . . . . . . B ADDR 00E8H.5 A 349# AD2TM. . . . . . . B ADDR 00E8H.6 A 348# AD2WINT. . . . . . B ADDR 00E8H.0 A 354# ADC0CF . . . . . . D ADDR 00BCH A 114# ADC0CN . . . . . . D ADDR 00E8H A 180# ADC0GTH. . . . . . D ADDR 00C5H A 129# ADC0GTL. . . . . . D ADDR 00C4H A 127# ADC0H. . . . . . . D ADDR 00BFH A 118# ADC0L. . . . . . . D ADDR 00BEH A 116# ADC0LTH. . . . . . D ADDR 00C7H A 132# ADC0LTL. . . . . . D ADDR 00C6H A 130# ADC0_PAGE. . . . . N NUMB 0000H A 379# ADC2 . . . . . . . D ADDR 00BEH A 117# ADC2CF . . . . . . D ADDR 00BCH A 115# ADC2CN . . . . . . D ADDR 00E8H A 181# ADC2GT . . . . . . D ADDR 00C4H A 128# ADC2LT . . . . . . D ADDR 00C6H A 131# ADC2_PAGE. . . . . N NUMB 0002H A 380# AMX0CF . . . . . . D ADDR 00BAH A 110# AMX0SL . . . . . . D ADDR 00BBH A 112# AMX2CF . . . . . . D ADDR 00BAH A 111# AMX2SL . . . . . . D ADDR 00BBH A 113# B. . . . . . . . . D ADDR 00F0H A 190# B155DONE . . . . . C ADDR 0032H A 448 452# B1AADONE . . . . . C ADDR 0064H A 481 485# B255DONE . . . . . C ADDR 004AH A 464 468# B2AADONE . . . . . C ADDR 007CH A 497 501# BUSY . . . . . . . B ADDR 00C0H.7 A 277# CCF0 . . . . . . . B ADDR 00D8H.0 A 334# CCF1 . . . . . . . B ADDR 00D8H.1 A 333# CCF2 . . . . . . . B ADDR 00D8H.2 A 332# CCF3 . . . . . . . B ADDR 00D8H.3 A 331# CCF4 . . . . . . . B ADDR 00D8H.4 A 330# CCF5 . . . . . . . B ADDR 00D8H.5 A 329# CCH0CN . . . . . . D ADDR 00A1H A 92# CCH0LC . . . . . . D ADDR 00A3H A 96# CCH0MA . . . . . . D ADDR 009AH A 83# CCH0TN . . . . . . D ADDR 00A2H A 94# CF . . . . . . . . B ADDR 00D8H.7 A 327# CKCON. . . . . . . D ADDR 008EH A 63# CLKSEL . . . . . . D ADDR 0097H A 77# CONFIG_PAGE. . . . N NUMB 000FH A 370# 422 433 CP0EN. . . . . . . B ADDR 0088H.7 A 218# CP0FIF . . . . . . B ADDR 0088H.4 A 221# A51 MACRO ASSEMBLER MEM_TEST 04/28/2006 09:23:49 PAGE 11 CP0HYN0. . . . . . B ADDR 0088H.0 A 225# CP0HYN1. . . . . . B ADDR 0088H.1 A 224# CP0HYP0. . . . . . B ADDR 0088H.2 A 223# CP0HYP1. . . . . . B ADDR 0088H.3 A 222# CP0OUT . . . . . . B ADDR 0088H.6 A 219# CP0RIF . . . . . . B ADDR 0088H.5 A 220# CP1EN. . . . . . . B ADDR 0088H.7 A 228# CP1FIF . . . . . . B ADDR 0088H.4 A 231# CP1HYN0. . . . . . B ADDR 0088H.0 A 235# CP1HYN1. . . . . . B ADDR 0088H.1 A 234# CP1HYP0. . . . . . B ADDR 0088H.2 A 233# CP1HYP1. . . . . . B ADDR 0088H.3 A 232# CP1OUT . . . . . . B ADDR 0088H.6 A 229# CP1RIF . . . . . . B ADDR 0088H.5 A 230# CPRL2. . . . . . . B ADDR 00C8H.0 A 298# CPRL3. . . . . . . B ADDR 00C8H.0 A 306# CPRL4. . . . . . . B ADDR 00C8H.0 A 314# CPT0CN . . . . . . D ADDR 0088H A 48# CPT0MD . . . . . . D ADDR 0089H A 52# CPT0_PAGE. . . . . N NUMB 0001H A 373# CPT1CN . . . . . . D ADDR 0088H A 49# CPT1MD . . . . . . D ADDR 0089H A 53# CPT1_PAGE. . . . . N NUMB 0002H A 374# CR . . . . . . . . B ADDR 00D8H.6 A 328# CT2. . . . . . . . B ADDR 00C8H.1 A 297# CT3. . . . . . . . B ADDR 00C8H.1 A 305# CT4. . . . . . . . B ADDR 00C8H.1 A 313# CY . . . . . . . . B ADDR 00D0H.7 A 317# DAC0CN . . . . . . D ADDR 00D4H A 161# DAC0H. . . . . . . D ADDR 00D3H A 159# DAC0L. . . . . . . D ADDR 00D2H A 157# DAC0_PAGE. . . . . N NUMB 0000H A 385# DAC1CN . . . . . . D ADDR 00D4H A 162# DAC1H. . . . . . . D ADDR 00D3H A 160# DAC1L. . . . . . . D ADDR 00D2H A 158# DAC1_PAGE. . . . . N NUMB 0001H A 386# DPH. . . . . . . . D ADDR 0083H A 42# 446 462 479 495 DPL. . . . . . . . D ADDR 0082H A 41# 447 463 480 496 EA . . . . . . . . B ADDR 00A8H.7 A 260# EIE1 . . . . . . . D ADDR 00E6H A 178# EIE2 . . . . . . . D ADDR 00E7H A 179# EIP1 . . . . . . . D ADDR 00F6H A 191# EIP2 . . . . . . . D ADDR 00F7H A 192# EMI0CF . . . . . . D ADDR 00A3H A 95# 429 EMI0CN . . . . . . D ADDR 00A2H A 93# EMI0TC . . . . . . D ADDR 00A1H A 91# EMI0_PAGE. . . . . N NUMB 0000H A 378# ENSMB. . . . . . . B ADDR 00C0H.6 A 278# ERROR. . . . . . . C ADDR 007EH A 444 460 477 493 502# ES0. . . . . . . . B ADDR 00A8H.4 A 262# ET0. . . . . . . . B ADDR 00A8H.1 A 265# ET1. . . . . . . . B ADDR 00A8H.3 A 263# ET2. . . . . . . . B ADDR 00A8H.5 A 261# EX0. . . . . . . . B ADDR 00A8H.0 A 266# EX1. . . . . . . . B ADDR 00A8H.2 A 264# EXEN2. . . . . . . B ADDR 00C8H.3 A 295# EXEN3. . . . . . . B ADDR 00C8H.3 A 303# EXEN4. . . . . . . B ADDR 00C8H.3 A 311# EXF2 . . . . . . . B ADDR 00C8H.6 A 294# EXF3 . . . . . . . B ADDR 00C8H.6 A 302# EXF4 . . . . . . . B ADDR 00C8H.6 A 310# F0 . . . . . . . . B ADDR 00D0H.5 A 319# F1 . . . . . . . . B ADDR 00D0H.1 A 323# FLACL. . . . . . . D ADDR 00B7H A 106# FLHBUSY. . . . . . B ADDR 0088H.0 A 238# FLSCL. . . . . . . D ADDR 00B7H A 107# A51 MACRO ASSEMBLER MEM_TEST 04/28/2006 09:23:49 PAGE 12 FLSTAT . . . . . . D ADDR 0088H A 47# IE . . . . . . . . D ADDR 00A8H A 101# IE0. . . . . . . . B ADDR 0088H.1 A 214# IE1. . . . . . . . B ADDR 0088H.3 A 212# IP . . . . . . . . D ADDR 00B8H A 108# IT0. . . . . . . . B ADDR 0088H.0 A 215# IT1. . . . . . . . B ADDR 0088H.2 A 213# LEGACY_PAGE. . . . N NUMB 0000H A 371# 428 LOOP . . . . . . . C ADDR 0023H A 442# 450 LOOP1. . . . . . . C ADDR 003BH A 458# 466 LOOP2. . . . . . . C ADDR 0055H A 475# 483 LOOP3. . . . . . . C ADDR 006DH A 491# 499 MAC0ACC0 . . . . . D ADDR 0093H A 71# MAC0ACC1 . . . . . D ADDR 0094H A 72# MAC0ACC2 . . . . . D ADDR 0095H A 73# MAC0ACC3 . . . . . D ADDR 0096H A 75# MAC0AH . . . . . . D ADDR 00C2H A 123# MAC0AL . . . . . . D ADDR 00C1H A 121# MAC0BH . . . . . . D ADDR 0092H A 70# MAC0BL . . . . . . D ADDR 0091H A 69# MAC0CF . . . . . . D ADDR 00C3H A 125# MAC0HO . . . . . . B ADDR 00C0H.3 A 287# MAC0N. . . . . . . B ADDR 00C0H.0 A 290# MAC0OVR. . . . . . D ADDR 0097H A 76# MAC0RNDH . . . . . D ADDR 00CFH A 153# MAC0RNDL . . . . . D ADDR 00CEH A 152# MAC0SO . . . . . . B ADDR 00C0H.1 A 289# MAC0STA. . . . . . D ADDR 00C0H A 119# MAC0Z. . . . . . . B ADDR 00C0H.2 A 288# MAC0_PAGE. . . . . N NUMB 0003H A 389# MAIN . . . . . . . C ADDR 0003H A 407 413# MCE1 . . . . . . . B ADDR 0098H.5 A 252# MODF . . . . . . . B ADDR 00F8H.5 A 359# NSSMD0 . . . . . . B ADDR 00F8H.2 A 362# NSSMD1 . . . . . . B ADDR 00F8H.3 A 361# OSCICL . . . . . . D ADDR 008BH A 57# OSCICN . . . . . . D ADDR 008AH A 55# OSCXCN . . . . . . D ADDR 008CH A 59# OV . . . . . . . . B ADDR 00D0H.2 A 322# P. . . . . . . . . B ADDR 00D0H.0 A 324# P0 . . . . . . . . D ADDR 0080H A 39# P0MDOUT. . . . . . D ADDR 00A4H A 97# P1 . . . . . . . . D ADDR 0090H A 67# P1MDIN . . . . . . D ADDR 00ADH A 103# P1MDOUT. . . . . . D ADDR 00A5H A 98# P2 . . . . . . . . D ADDR 00A0H A 90# P2MDOUT. . . . . . D ADDR 00A6H A 99# P3 . . . . . . . . D ADDR 00B0H A 104# P3MDOUT. . . . . . D ADDR 00A7H A 100# P4 . . . . . . . . D ADDR 00C8H A 133# 437 454 470 487 P4MDOUT. . . . . . D ADDR 009CH A 85# P5 . . . . . . . . D ADDR 00D8H A 163# P5MDOUT. . . . . . D ADDR 009DH A 86# P6 . . . . . . . . D ADDR 00E8H A 182# P6MDOUT. . . . . . D ADDR 009EH A 88# P7 . . . . . . . . D ADDR 00F8H A 193# P7MDOUT. . . . . . D ADDR 009FH A 89# PCA0CN . . . . . . D ADDR 00D8H A 164# PCA0CPH0 . . . . . D ADDR 00FCH A 198# PCA0CPH1 . . . . . D ADDR 00FEH A 200# PCA0CPH2 . . . . . D ADDR 00EAH A 184# PCA0CPH3 . . . . . D ADDR 00ECH A 186# PCA0CPH4 . . . . . D ADDR 00EEH A 188# PCA0CPH5 . . . . . D ADDR 00E2H A 175# PCA0CPL0 . . . . . D ADDR 00FBH A 197# PCA0CPL1 . . . . . D ADDR 00FDH A 199# A51 MACRO ASSEMBLER MEM_TEST 04/28/2006 09:23:49 PAGE 13 PCA0CPL2 . . . . . D ADDR 00E9H A 183# PCA0CPL3 . . . . . D ADDR 00EBH A 185# PCA0CPL4 . . . . . D ADDR 00EDH A 187# PCA0CPL5 . . . . . D ADDR 00E1H A 174# PCA0CPM0 . . . . . D ADDR 00DAH A 166# PCA0CPM1 . . . . . D ADDR 00DBH A 167# PCA0CPM2 . . . . . D ADDR 00DCH A 168# PCA0CPM3 . . . . . D ADDR 00DDH A 169# PCA0CPM4 . . . . . D ADDR 00DEH A 170# PCA0CPM5 . . . . . D ADDR 00DFH A 171# PCA0H. . . . . . . D ADDR 00FAH A 196# PCA0L. . . . . . . D ADDR 00F9H A 195# PCA0MD . . . . . . D ADDR 00D9H A 165# PCA0_PAGE. . . . . N NUMB 0000H A 387# PCON . . . . . . . D ADDR 0087H A 46# PLL0CN . . . . . . D ADDR 0089H A 54# PLL0DIV. . . . . . D ADDR 008DH A 62# PLL0FLT. . . . . . D ADDR 008FH A 66# PLL0MUL. . . . . . D ADDR 008EH A 64# PLL0_PAGE. . . . . N NUMB 000FH A 388# PS . . . . . . . . B ADDR 00B8H.4 A 270# PSBANK . . . . . . D ADDR 00B1H A 105# PSCTL. . . . . . . D ADDR 008FH A 65# PSW. . . . . . . . D ADDR 00D0H A 155# PT0. . . . . . . . B ADDR 00B8H.1 A 273# PT1. . . . . . . . B ADDR 00B8H.3 A 271# PT2. . . . . . . . B ADDR 00B8H.5 A 269# PX0. . . . . . . . B ADDR 00B8H.0 A 274# PX1. . . . . . . . B ADDR 00B8H.2 A 272# RB80 . . . . . . . B ADDR 0098H.2 A 246# RB81 . . . . . . . B ADDR 0098H.2 A 255# RCAP2H . . . . . . D ADDR 00CBH A 143# RCAP2L . . . . . . D ADDR 00CAH A 140# RCAP3H . . . . . . D ADDR 00CBH A 144# RCAP3L . . . . . . D ADDR 00CAH A 141# RCAP4H . . . . . . D ADDR 00CBH A 145# RCAP4L . . . . . . D ADDR 00CAH A 142# REF0CN . . . . . . D ADDR 00D1H A 156# REN0 . . . . . . . B ADDR 0098H.4 A 244# REN1 . . . . . . . B ADDR 0098H.4 A 253# RI0. . . . . . . . B ADDR 0098H.0 A 248# RI1. . . . . . . . B ADDR 0098H.0 A 257# RS0. . . . . . . . B ADDR 00D0H.3 A 321# RS1. . . . . . . . B ADDR 00D0H.4 A 320# RSTSRC . . . . . . D ADDR 00EFH A 189# RXOVRN . . . . . . B ADDR 00F8H.4 A 360# S1MODE . . . . . . B ADDR 0098H.7 A 251# SADDR0 . . . . . . D ADDR 00A9H A 102# SADEN0 . . . . . . D ADDR 00B9H A 109# SBUF0. . . . . . . D ADDR 0099H A 80# SBUF1. . . . . . . D ADDR 0099H A 81# SCON0. . . . . . . D ADDR 0098H A 78# SCON1. . . . . . . D ADDR 0098H A 79# SFRLAST. . . . . . D ADDR 0086H A 45# SFRNEXT. . . . . . D ADDR 0085H A 44# SFRPAGE. . . . . . D ADDR 0084H A 43# 422 428 433 SFRPGCN. . . . . . D ADDR 0096H A 74# SI . . . . . . . . B ADDR 00C0H.3 A 281# SM00 . . . . . . . B ADDR 0098H.7 A 241# SM10 . . . . . . . B ADDR 0098H.6 A 242# SM20 . . . . . . . B ADDR 0098H.5 A 243# SMB0ADR. . . . . . D ADDR 00C3H A 126# SMB0CN . . . . . . D ADDR 00C0H A 120# SMB0CR . . . . . . D ADDR 00CFH A 154# SMB0DAT. . . . . . D ADDR 00C2H A 124# SMB0STA. . . . . . D ADDR 00C1H A 122# A51 MACRO ASSEMBLER MEM_TEST 04/28/2006 09:23:49 PAGE 14 SMB0_PAGE. . . . . N NUMB 0000H A 381# SMBFTE . . . . . . B ADDR 00C0H.1 A 283# SMBTOE . . . . . . B ADDR 00C0H.0 A 284# SP . . . . . . . . D ADDR 0081H A 40# SPI0CFG. . . . . . D ADDR 009AH A 82# SPI0CKR. . . . . . D ADDR 009DH A 87# SPI0CN . . . . . . D ADDR 00F8H A 194# SPI0DAT. . . . . . D ADDR 009BH A 84# SPI0_PAGE. . . . . N NUMB 0000H A 377# SPIEN. . . . . . . B ADDR 00F8H.0 A 364# SPIF . . . . . . . B ADDR 00F8H.7 A 357# SSTA0. . . . . . . D ADDR 0091H A 68# STA. . . . . . . . B ADDR 00C0H.5 A 279# START. . . . . . . C ADDR 0018H A 435# 501 STO. . . . . . . . B ADDR 00C0H.4 A 280# TB80 . . . . . . . B ADDR 0098H.3 A 245# TB81 . . . . . . . B ADDR 0098H.3 A 254# TCON . . . . . . . D ADDR 0088H A 50# TF0. . . . . . . . B ADDR 0088H.5 A 210# TF1. . . . . . . . B ADDR 0088H.7 A 208# TF2. . . . . . . . B ADDR 00C8H.7 A 293# TF3. . . . . . . . B ADDR 00C8H.7 A 301# TF4. . . . . . . . B ADDR 00C8H.7 A 309# TH0. . . . . . . . D ADDR 008CH A 60# TH1. . . . . . . . D ADDR 008DH A 61# TI0. . . . . . . . B ADDR 0098H.1 A 247# TI1. . . . . . . . B ADDR 0098H.1 A 256# TIMER01_PAGE . . . N NUMB 0000H A 372# TL0. . . . . . . . D ADDR 008AH A 56# TL1. . . . . . . . D ADDR 008BH A 58# TMOD . . . . . . . D ADDR 0089H A 51# TMR2CF . . . . . . D ADDR 00C9H A 137# TMR2CN . . . . . . D ADDR 00C8H A 134# TMR2H. . . . . . . D ADDR 00CDH A 149# TMR2L. . . . . . . D ADDR 00CCH A 146# TMR2_PAGE. . . . . N NUMB 0000H A 382# TMR3CF . . . . . . D ADDR 00C9H A 138# TMR3CN . . . . . . D ADDR 00C8H A 135# TMR3H. . . . . . . D ADDR 00CDH A 150# TMR3L. . . . . . . D ADDR 00CCH A 147# TMR3_PAGE. . . . . N NUMB 0001H A 383# TMR4CF . . . . . . D ADDR 00C9H A 139# TMR4CN . . . . . . D ADDR 00C8H A 136# TMR4H. . . . . . . D ADDR 00CDH A 151# TMR4L. . . . . . . D ADDR 00CCH A 148# TMR4_PAGE. . . . . N NUMB 0002H A 384# TR0. . . . . . . . B ADDR 0088H.4 A 211# TR1. . . . . . . . B ADDR 0088H.6 A 209# TR2. . . . . . . . B ADDR 00C8H.2 A 296# TR3. . . . . . . . B ADDR 00C8H.2 A 304# TR4. . . . . . . . B ADDR 00C8H.2 A 312# TXBMT. . . . . . . B ADDR 00F8H.1 A 363# UART0_PAGE . . . . N NUMB 0000H A 375# UART1_PAGE . . . . N NUMB 0001H A 376# WCOL . . . . . . . B ADDR 00F8H.6 A 358# WDTCN. . . . . . . D ADDR 00FFH A 201# 418 419 XBR0 . . . . . . . D ADDR 00E1H A 173# XBR1 . . . . . . . D ADDR 00E2H A 176# XBR2 . . . . . . . D ADDR 00E3H A 177# 425 REGISTER BANK(S) USED: 0 ASSEMBLY COMPLETE. 0 WARNING(S), 0 ERROR(S)