#ifndef ASM_DSM_H #define ASM_DSM_H /* $Id: asm_dsm.h,v 1.6 2000/05/30 22:25:44 garym Exp $ Copyright Motorola, Inc. 1993, 1994 ALL RIGHTS RESERVED You are hereby granted a copyright license to use, modify, and distribute the SOFTWARE so long as this entire notice is retained without alteration in any modified and/or redistributed versions, and that such modified versions are clearly identified as such. No licenses are granted by implication, estoppel or otherwise under any patents or trademarks of Motorola, Inc. The SOFTWARE is provided on an "AS IS" basis and without warranty. To the maximum extent permitted by applicable law, MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) AND ANY ACCOMPANYING WRITTEN MATERIALS. To the maximum extent permitted by applicable law, IN NO EVENT SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. Motorola assumes no responsibility for the maintenance and support of the SOFTWARE. */ /* 0 1 2 3 4 5 6 7 8 012345678901234567890123456789012345678901234567890123456789012345678901234567890 */ /* ----------------------------------------------------------------------- */ /* file: disassembler.h purpose: This file contains declarations and such for the disassembler. inputs: NONE! outputs: NONE! return: NONE! modification history: 6/1/93 MH Added flag LE_ENVIRON to determine if we are assembling/disassembling little-endian opcodes. Also added SWITCH_ENDIAN macro. This macro converts a 32-bit value to/from little-endian. 1/19/93 MH */ /* ----------------------------------------------------------------------- */ /* Define some constants to represent the different forms of instructions. The kludge of the mnemonic-opcode mapping on the PowerPC architecture makes it difficult for me to explain why there are "forms" of instructions, but there are... */ #include "config.h" #define I 0 #define B 1 #define SC 2 #define D 3 #define DS 4 #define X 5 #define XL 6 #define XFX 7 #define XFL 8 #define XS 9 #define XO 10 #define A 11 #define M 12 #define MD 13 #define MDS 14 #define VX 15 #define VA 16 #define VXR 17 /* Define some constants to represent the different forms of simplified mnemonics...these will be used WITHIN the regular form routines to set up the mnemonics correctly for the simplified versions... */ #define smI 80 #define smB 81 #define smS 82 #define smD 83 #define smDS 84 #define smX 85 #define smXL 86 #define smXFX 87 #define smXFL 88 #define smXS 89 #define smXO 90 #define smA 91 #define smM 92 #define smMD 93 #define smMDS 94 #define smBC 100 #define smBCA 120 #define smBCLR 130 #define smBCCTR 140 #define smBCL 150 #define smBCLA 160 #define smBCLRL 170 #define smBCCTRL 180 #define smVX 190 #define smVXR 200 /* Uncomment this next line ONLY if we are building this code to run on a little- endian platform. I need this because I can only assemble/disassemble big- endian opcodes. */ /* #define LE_ENVIRON */ /* =================================================================== */ /* ============== Begin "define" for some useful macros ============== */ /* =================================================================== */ /* This first set of defines are for extracting fields. The defines for inserting fields are just below this first list. */ /* Extract bit 10 from opcode... some smX and smD need it */ #define EXTRACT_SECONDARY_BIT10( opcode ) ( ( opcode & 0x00200000 ) >> 21 ) /* Extract bits 21:31 for branch comparisons */ #define EXTRACT_SECONDARY_LK( opcode ) ( ( opcode & 0x000007FF ) >> 0 ) /* Extract bits 0:15 for do_simplified_branch routine */ #define EXTRACT_SPECIAL( opcode ) ( ( opcode & 0xffff0000 ) >> 16 ) /* Extract just bits 21:30 from smM type */ #define EXTRACT_SECONDARY1_smM( opcode ) ( ( opcode & 0x000007fe ) >> 1 ) /* Extract just bits 16:20 */ #define EXTRACT_SECONDARY2_smM( opcode ) ( ( opcode & 0x0000f800 ) >> 11 ) /* Extract just bits 16:25 from smM type */ #define EXTRACT_SECONDARY3_smM( opcode ) ( ( opcode & 0x0000ffc0 ) >> 6 ) /* Extract just bits 21:25 from smM type */ #define EXTRACT_SECONDARY4_smM( opcode ) ( ( opcode & 0x000007c0 ) >> 6 ) /* Extract just bits 26:30 from smM type */ #define EXTRACT_SECONDARY5_smM( opcode ) ( ( opcode & 0x0000003e ) >> 1 ) /* Extract LK field */ #define EXTRACT_LK( opcode ) ( ( opcode & 0x1 ) >> 0 ) /* Extract AA field */ #define EXTRACT_AA( opcode ) ( ( opcode & 0x2 ) >> 1 ) /* Extract LK and AA field */ #define EXTRACT_LK_AA( opcode ) ( ( opcode & 0x3 ) >> 0 ) /* Extract OE field - bit 21 - from XO form */ #define EXTRACT_OE( opcode ) ( ( opcode & 0x00000400 ) >> 10 ) /* Extract primary opcode (bits 0:5) */ #define EXTRACT_PRIMARY( opcode ) ( ( opcode & 0xFC000000 ) >> 26 ) /* Extract primary opcode+ (bits 0:10) */ /* MATT added this 8/31/95 */ #define EXTRACT_PRIMARY_B( opcode ) ( ( opcode & 0xFFE00000 ) >> 21 ) /* Extract secondary opcode for SC form instructions (bit 30 ) */ #define EXTRACT_SECONDARY_SC( opcode ) ( ( opcode & 0x00000002 ) >> 1 ) /* Extract secondary opcode for DS form instructions (bits 30:31 ) */ #define EXTRACT_SECONDARY_DS( opcode ) ( ( opcode & 0x00000003 ) >> 0 ) /* Extract secondary opcode for X form instructions (bits 21:30 ) */ #define EXTRACT_SECONDARY_X( opcode ) ( ( opcode & 0x000007FE ) >> 1 ) /* Extract secondary opcode for XL form instructions (bits 21:30 ) */ #define EXTRACT_SECONDARY_XL( opcode ) ( ( opcode & 0x000007FE ) >> 1 ) /* Extract bits 6:30...ISYNC instruction has 000 and then 150 as secondary */ /* Extract secondary opcode for V_ form instructions (bits 21:31 ) */ #define EXTRACT_SECONDARY_V( opcode ) ( ( opcode & 0x000007FF ) >> 0 ) #define EXTRACT_ISYNC_BITS( opcode ) ( ( opcode & 0x03FFFFFE ) >> 1 ) /* Extract secondary opcode for XFX form instructions (bits 21:30 ) */ #define EXTRACT_SECONDARY_XFX( opcode ) ( ( opcode & 0x000007FE ) >> 1 ) /* Extract secondary opcode for smXFX form instructions (bits 11:30 ) */ #define EXTRACT_SECONDARY_smXFX( opcode ) ( ( opcode & 0x001FFFFE ) >> 1 ) /* Extract secondary opcode for XFL form instructions (bits 21:30 ) */ #define EXTRACT_SECONDARY_XFL( opcode ) ( ( opcode & 0x000007FE ) >> 1 ) /* Extract secondary opcode for XS form instructions (bits 21:29 ) */ #define EXTRACT_SECONDARY_XS( opcode ) ( ( opcode & 0x000007FC ) >> 2 ) /* Extract secondary opcode for XO form instructions (bits 22:30 ) */ #define EXTRACT_SECONDARY_XO( opcode ) ( ( opcode & 0x000003FE ) >> 1 ) /* Extract secondary opcode for smXO form instructions (bits 21:31) */ #define EXTRACT_SECONDARY_smXO( opcode ) ( ( opcode & 0x07FF ) >> 0 ) /* Extract secondary opcode for A form instructions (bits 26:30 ) */ #define EXTRACT_SECONDARY_A( opcode ) ( ( opcode & 0x0000003E ) >> 1 ) /* Extract secondary opcode for MD form instructions (bits 27:29 ) */ #define EXTRACT_SECONDARY_MD( opcode ) ( ( opcode & 0x0000001C ) >> 2 ) /* Extract secondary opcode for MDS form instructions (bits 27:30 ) */ #define EXTRACT_SECONDARY_MDS( opcode ) ( ( opcode & 0x0000001E ) >> 1 ) /* Extract BA Field (bits 11:15) */ #define EXTRACT_BA( opcode ) ( ( opcode & 0x001F0000 ) >> 16 ) /* Extract BB Field (bits 16:20) */ #define EXTRACT_BB( opcode ) ( ( opcode & 0x0000F800 ) >> 11 ) /* Extract BD Field (bits 16:29) */ /* NOTE: BD field is a little strange. We need to append 0b00 onto the least-significant bits of this field before we return it, just as the processor does. */ #define EXTRACT_BD( opcode ) ( ( ( opcode & 0x0000FFFC ) >> 2 ) << 2 ) /* Extract BF Field (bits 6:8) */ #define EXTRACT_BF( opcode ) ( ( opcode & 0x03800000 ) >> 23 ) /* Extract BFA Field (bits 11:13) */ #define EXTRACT_BFA( opcode ) ( ( opcode & 0x001C0000 ) >> 18 ) /* Extract BI Field (bits 11:15) */ #define EXTRACT_BI( opcode ) ( ( opcode & 0x001F0000 ) >> 16 ) /* Extract BO Field (bits 6:10) */ #define EXTRACT_BO( opcode ) ( ( opcode & 0x03E00000 ) >> 21 ) /* Extract BT Field (bits 6:10) */ #define EXTRACT_BT( opcode ) ( ( opcode & 0x03E00000 ) >> 21 ) /* Extract D Field (bits 16:31) */ #define EXTRACT_D( opcode ) ( ( opcode & 0x0000FFFF ) >> 0 ) /* Extract NOP test bits (bits 6:31) */ #define EXTRACT_NOP( opcode ) ( ( opcode & 0x03FFFFFF ) >> 0 ) /* Extract DS Field (bits 16:29) */ /* NOTE: DS field is a little strange. We need to append 0b00 onto the least-significant bits of this field before we return it, just as the processor does. */ #define EXTRACT_DS( opcode ) ( ( ( opcode & 0x0000FFFC ) >> 2 ) << 2 ) /* Extract FLM Field (bits 7:14) */ #define EXTRACT_FLM( opcode ) ( ( opcode & 0x01FE0000 ) >> 17 ) /* Extract FRA Field (bits 11:15) */ #define EXTRACT_FRA( opcode ) ( ( opcode & 0x001F0000 ) >> 16 ) /* Extract FRB Field (bits 16:20) */ #define EXTRACT_FRB( opcode ) ( ( opcode & 0x0000F800 ) >> 11 ) /* Extract FRC Field (bits 21:25) */ #define EXTRACT_FRC( opcode ) ( ( opcode & 0x000007C0 ) >> 6 ) /* Extract FRS Field (bits 6:10) */ #define EXTRACT_FRS( opcode ) ( ( opcode & 0x03E00000 ) >> 21 ) /* Extract FRT Field (bits 6:10) */ #define EXTRACT_FRT( opcode ) ( ( opcode & 0x03E00000 ) >> 21 ) /* Extract FXM Field (bits 12:19) */ #define EXTRACT_FXM( opcode ) ( ( opcode & 0x000FF000 ) >> 12 ) /* Extract L Field (bits 10) */ #define EXTRACT_L( opcode ) ( ( opcode & 0x00200000 ) >> 21 ) /* Extract LI Field (bits 6:29) */ /* NOTE: BD field is a little strange. We need to append 0b00 onto the least-significant bits of this field before we return it, just as the processor does. */ #define EXTRACT_LI( opcode ) ( ( ( opcode & 0x03FFFFFC ) >> 2 ) << 2 ) /* Extract MBE Field (bits 21:30) */ #define EXTRACT_MBE( opcode ) ( ( opcode & 0x07FE ) >> 1 ) /* Extract MB Field (bits 21:26) */ #define EXTRACT_MB( opcode ) ( ( opcode & 0x000007E0 ) >> 5 ) /* Extract MB Field (bits 21:25) */ #define EXTRACT_MB_smM( opcode ) ( ( opcode & 0x000007C0 ) >> 6 ) /* Extract ME Field (bits 21:26) */ #define EXTRACT_ME( opcode ) ( ( opcode & 0x000007E0 ) >> 5 ) /* Extract ME Field (bits 26:30) */ #define EXTRACT_ME_smM( opcode ) ( ( opcode & 0x0000003E ) >> 1 ) /* Extract NB Field (bits 16:20) */ #define EXTRACT_NB( opcode ) ( ( opcode & 0x0000F800 ) >> 11 ) /* Extract RA Field (bits 11:15) */ #define EXTRACT_RA( opcode ) ( ( opcode & 0x001F0000 ) >> 16 ) /* Extract RB Field (bits 16:20) */ #define EXTRACT_RB( opcode ) ( ( opcode & 0x0000F800 ) >> 11 ) /* Extract RC Field (bit 31) */ #define EXTRACT_RC( opcode ) ( opcode & 0x00000001 ) /* Extract RS Field (bits 6:10) */ #define EXTRACT_RS( opcode ) ( ( opcode & 0x03E00000 ) >> 21 ) /* Extract RT Field (bits 6:10) */ #define EXTRACT_RT( opcode ) ( ( opcode & 0x03E00000 ) >> 21 ) /* Extract SH Field (bits 16:20) */ #define EXTRACT_SH32( opcode ) ( ( opcode & 0x0000F800 ) >> 11 ) /* Extract SH Field (bits 16:20 & 30) */ #define EXTRACT_SH64( opcode ) ( ( ( opcode & 0xF800 ) >> 11 ) + ( ( opcode & 0x2 ) << 4 ) ) /* Extract SI Field (bits 16:31) */ #define EXTRACT_SI( opcode ) ( ( opcode & 0x0000FFFF ) >> 0 ) /* Extract SPR Field (bits 11:20) */ /* Ha! Yet another kludge in this mnemonic-opcode mapping! Yes, that's right! We need to split this 10-bit field into 2 5-bit blocks, then swap those blocks. Gruesome, huh? */ #define EXTRACT_SPR( opcode ) ( ( ( opcode & 0x001F0000 ) >> 16 ) + ( ( opcode & 0x0000F800 ) >> 6 ) ) /* Extract TO Field (bits 6:10) */ #define EXTRACT_TO( opcode ) ( ( opcode & 0x03E00000 ) >> 21 ) /* Extract U Field (bits 16:19) */ #define EXTRACT_U( opcode ) ( ( opcode & 0x0000F000 ) >> 12 ) /* Extract UI Field (bits 16:31) */ #define EXTRACT_UI( opcode ) ( ( opcode & 0x0000FFFF ) >> 0 ) /* ================================== Begin defines for inserting fields ================================== */ /* Insert LK field */ #define INSERT_LK( opcode, field ) ( opcode | ( ( field & 0x1 ) << 0 ) ) /* Insert AA field */ #define INSERT_AA( opcode, field ) ( opcode | ( ( field & 0x2 ) << 1 ) ) /* Insert BA Field (bits 11:15) */ #define INSERT_BA( opcode, field ) ( opcode | ( ( field & 0x1F ) << 16 ) ) /* Insert BB Field (bits 16:20) */ #define INSERT_BB( opcode, field ) ( opcode | ( ( field & 0x1F ) << 11 ) ) /* Insert BD Field (bits 16:29) */ /* NOTE: BD field is a little strange. We need to hack off the 2 the least-significant bits of this field before we insert it. The processor will append 0b00 onto this field when it's extracted. */ #define INSERT_BD( opcode, field ) ( opcode | ( ( ( field >> 2 ) & 0x3FFF ) << 2 ) ) /* Insert BF Field (bits 6:8) */ #define INSERT_BF( opcode, field ) ( opcode | ( ( field & 0x7 ) << 23 ) ) /* Insert BFA Field (bits 11:13) */ #define INSERT_BFA( opcode, field ) ( opcode | ( ( field & 0x7 ) << 18 ) ) /* Insert BI Field (bits 11:15) */ #define INSERT_BI( opcode, field ) ( opcode | ( ( field & 0x1F ) << 16 ) ) /* Insert BO Field (bits 6:10) */ #define INSERT_BO( opcode, field ) ( opcode | ( ( field & 0x1F ) << 21 ) ) /* Insert BT Field (bits 6:10) */ #define INSERT_BT( opcode, field ) ( opcode | ( ( field & 0x1F ) << 21 ) ) /* Insert D Field (bits 16:31) */ #define INSERT_D( opcode, field ) ( opcode | ( ( field & 0xFFFF ) << 0 ) ) /* Insert DS Field (bits 16:29) */ /* NOTE: BD field is a little strange. We need to hack off the 2 the least-significant bits of this field before we insert it. The processor will append 0b00 onto this field when it's extracted. */ #define INSERT_DS( opcode, field ) ( opcode | ( ( ( field >> 2 ) & 0x3FFF ) << 2 ) ) /* Insert FLM Field (bits 7:14) */ #define INSERT_FLM( opcode, field ) ( opcode | ( ( field & 0xFF ) << 17 ) ) /* Insert FRA Field (bits 11:15) */ #define INSERT_FRA( opcode, field ) ( opcode | ( ( field & 0x1F ) << 16 ) ) /* Insert FRB Field (bits 16:20) */ #define INSERT_FRB( opcode, field ) ( opcode | ( ( field & 0x1F ) << 11 ) ) /* Insert FRC Field (bits 21:25) */ #define INSERT_FRC( opcode, field ) ( opcode | ( ( field & 0x1F ) << 6 ) ) /* Insert SH Field (bits 21:25) for VSLDOI*/ #define INSERT_VAS( opcode, field ) ( opcode | ( ( field & 0x0F ) << 6 ) ) /* Insert FRS Field (bits 6:10) */ #define INSERT_FRS( opcode, field ) ( opcode | ( ( field & 0x1F ) << 21 ) ) /* Insert FRT Field (bits 6:10) */ #define INSERT_FRT( opcode, field ) ( opcode | ( ( field & 0x1F ) << 21 ) ) /* Insert FXM Field (bits 12:19) */ #define INSERT_FXM( opcode, field ) ( opcode | ( ( field & 0xFF ) << 12 ) ) /* Insert L Field (bits 10) */ #define INSERT_L( opcode, field ) ( opcode | ( ( field & 0x1 ) << 21 ) ) /* Insert LI Field (bits 6:29) */ /* NOTE: BD field is a little strange. We need to hack off the 2 the least-significant bits of this field before we insert it. The processor will append 0b00 onto this field when it's extracted. */ #define INSERT_LI( opcode, field ) ( opcode | ( ( ( field >> 2 ) & 0xFFFFFF ) << 2 ) ) /* Insert MBE Field (bits 21:30) */ #define INSERT_MBE( opcode, field ) ( opcode | ( ( field & 0x3FF ) << 1 ) ) /* Insert MB Field (bits 21:26) */ #define INSERT_MB( opcode, field ) ( opcode | ( ( field & 0x3F ) << 5 ) ) /* Insert ME Field (bits 21:26) */ #define INSERT_ME( opcode, field ) ( opcode | ( ( field & 0x3F ) << 5 ) ) /* Insert NB Field (bits 16:20) */ #define INSERT_NB( opcode, field ) ( opcode | ( ( field & 0x1F ) << 11 ) ) /* Insert MB Field (bits 21:25) */ #define INSERT_MB_smM( opcode, field ) ( opcode | ( ( field & 0x1F ) << 6 ) ) /* Insert ME Field (bits 26:30) */ #define INSERT_ME_smM( opcode, field ) ( opcode | ( ( field & 0x1F ) << 1 ) ) /* Insert RA Field (bits 11:15) */ #define INSERT_RA( opcode, field ) ( opcode | ( ( field & 0x1F ) << 16 ) ) /* Insert RB Field (bits 16:20) */ #define INSERT_RB( opcode, field ) ( opcode | ( ( field & 0x1F ) << 11 ) ) /* Insert RC Field (bit 31) */ #define INSERT_RC( opcode, field ) ( opcode | ( field & 0x1 ) ) /* Insert RS Field (bits 6:10) */ #define INSERT_RS( opcode, field ) ( opcode | ( ( field & 0x1F ) << 21 ) ) /* Insert RT Field (bits 6:10) */ #define INSERT_RT( opcode, field ) ( opcode | ( ( field & 0x1F ) << 21 ) ) /* Insert SH Field (bits 16:20) */ #define INSERT_SH32( opcode, field ) ( opcode | ( ( field & 0x1F ) << 11 ) ) /* Insert SH Field (bits 16:20 & 30) */ #define INSERT_SH64( opcode, field ) ( opcode | ( ( ( field & 0x1F ) << 11 ) + ( ( field & 0x20 ) >> 4 ) ) ) /* Insert SI Field (bits 16:31) */ #define INSERT_SI( opcode, field ) ( opcode | ( ( field & 0xFFFF ) << 0 ) ) /* Insert SPR Field (bits 11:20) */ /* Ha! Yet another kludge in this mnemonic-opcode mapping! Yes, that's right! We need to split this 10-bit field into 2 5-bit blocks, then swap those blocks. Gruesome, huh? */ #define INSERT_SPR( opcode, field ) ( opcode | ( ( ( field & 0x1F ) << 16 ) + ( ( field & 0x3E0 ) << 6 ) ) ) /* Insert TO Field (bits 6:10) */ #define INSERT_TO( opcode, field ) ( opcode | ( ( field & 0x1F ) << 21 ) ) /* Insert U Field (bits 16:19) */ #define INSERT_U( opcode, field ) ( opcode | ( ( field & 0xF ) << 12 ) ) /* Insert UI Field (bits 16:31) */ #define INSERT_UI( opcode, field ) ( opcode | ( ( field & 0xFFFF ) << 0 ) ) /* Insert UI Field (bits 11:15) */ #define INSERT_VUI( opcode, field ) ( opcode | ( ( field & 0x1F ) << 16 ) ) /* Insert SI Field (bits 11:15) */ #define INSERT_VSI( opcode, field ) ( opcode | ( ( field & 0x1F ) << 16 ) ) /* Insert STRM Field (bits 6:10) */ #define INSERT_STRM( opcode, field ) ( opcode | ( ( field & 0x03 ) << 21 ) ) /* This last macro is used when we want to assemble/disassemble little-endian opcodes. All these do is shuffle the bytes in the 32-bit opcode. Fortunately we use the same algorithm to convert from big to little endian as we do to convert from little to big, so we only need 1 macro. */ #define SWITCH_ENDIAN( opcode ) ( ( ( opcode & 0x000000FF ) << 24 ) | \ ( ( opcode & 0x0000FF00 ) << 8 ) | \ ( ( opcode & 0x00FF0000 ) >> 8 ) | \ ( ( opcode & 0xFF000000 ) >> 24 ) \ ) /* =================================================================== */ /* =============== End "define" for some useful macros =============== */ /* =================================================================== */ /* This noise is so that I can use this .h file with a lot of .c files and have them all deal with the declaration properly. These defines shouldn't need to be changed */ #ifndef IN_ASSEMBLER_DISASSEMBLER #define WHERE extern #else #define WHERE #endif /* =================================================================== */ /* ===================== Prototype Our Functions ===================== */ /* =================================================================== */ WHERE STATUS do_simplified_branch(); WHERE STATUS GOPRINT_SPR(); WHERE STATUS special_search_ops_and_mnemonics(); WHERE STATUS assemble(); WHERE STATUS assemble_a_mnemonic(); WHERE STATUS init_ops_and_mnemonics(); WHERE STATUS pull_next_word(); WHERE STATUS pull_next_word_2(); WHERE STATUS pull_register(); WHERE STATUS pull_immediate(); WHERE STATUS pull_immediate_branch(); WHERE STATUS pull_immediate_cr(); WHERE STATUS disassemble(); WHERE STATUS disassemble_an_opcode(); WHERE STATUS search_ops_and_mnemonics(); /* This is the number of mnemonics recognized by this assembler/disassembler. */ #define MAXBRANCHLABEL 40 #define NSYM 0 /* No symbol defined */ #define USYM 1 /* User symbol */ #define DSYM 2 /* DINK symbol */ typedef struct { /* This structure will hold a single element of an array used to assemble and disassemble PowerPC opcodes. */ /* This field will be a unique token which represents a PowerPC instruction mnemonic */ char mnemonic[15]; /* This field will be the 32-bit opcode for the mnemonic. The 32-bit opcode will include the primary 6-bit opcode, the secondary opcode, and assumes all register bitfields are zeroed-out. */ unsigned long opcode; /* The "form" of an instruction tells me what fields need to be decoded within the instruction. For example, an I Form means that there is an immediate field embedded within the opcode. This field is in bits 6:29. The "form" field of this structure will be defined as follows: 0 I Form 1 B Form 2 SC Form 3 D Form 4 DS Form 5 X Form 6 XL Form 7 XFX Form 8 XFL Form 9 XS Form 10 XO Form 11 A Form 12 M Form 13 MD Form 14 MDS Form 15 VX Form 16 VA Form 17 VXR Form plus the simplified mnemonics! */ unsigned char form; } asm_dasm_element; /* This structure will hold a single element of a branch label */ typedef struct { char name[15]; /* lable name */ unsigned long address; /* 32-bit address for the branch */ int label_type; /* User label or DINK label */ } label_array_element; WHERE STATUS branchtable_init(); WHERE STATUS branchtable_list(); #undef WHERE typedef unsigned int (*OPA_FUNC)( unsigned long ); typedef struct _altvec_disass_struc { unsigned int mask; /* mask of the instruction opcode */ unsigned int opcode; /* result of masking opcode with mask */ unsigned short num_opa; /* number of operand of this instruction */ unsigned char fmt[80]; /* disassemble output format */ /* maximum 4 operands per instruction */ OPA_FUNC opa_func[4]; } ALTVEC_DISASS_STRUC; #endif