/* file: bigbend.h */ /* This file contains defines for the Big Bend PReP-compliant board. This includes the 105, the UMC UM8886, and the NS PC87323VUL. */ #include "config.h" #define BB_BE /* current values (_V) shown for r/w regs are those given at reset. */ /* value for PIC1 was suggested at meeting w/ Mike Becker. */ #ifdef BB_BE /* bytes for addresses and data values must be swapped before writing them to the 105. However, writes to go out over the PCI bus do not need any byte- swapping; they will go through just fine. */ #define VID 0x0000 #define DID 0x0200 #define PCI_CR 0x0400 #define PCI_CR_V 0x0600 /* 2 bytes */ #define PCI_SR 0x0600 #define RID 0x0800 #define SPINT 0x0900 #define SUBCLASSCODE 0x0a00 #define CLASSCODE 0x0b00 #define CACHELINESIZE 0x0c00 #define LATENCYTIMER 0x0d00 #define HEADERTYPE 0x0e00 #define BISTCONTROL 0x0f00 #define INTERRUPTLINE 0x3c00 #define INTERRUPTPIN 0x3d00 #define MINGNT 0x3e00 #define MAXGNT 0x3f00 #define BRIDGENUMBER 0x4000 #define SUBORDBUSNUM 0x4100 #define DISCONNECTCNT 0x4200 #define SPECIALCYCLEAR 0x4400 #define POWERMGMTCONF 0x7000 #define PMC_V 0x0000 /* 2 bytes */ /* need initial values for mem bank starts and ends and enable */ #define MEMSTARTADDR1 0x8000 /* 4 bytes */ #define MSA1_V1 0x0000 #define MSA1_V2 0x0000 #define MEMSTARTADDR2 0x8400 #define MEMENDADDR1 0x9000 #define MEA1_V1 0x0700 #define MEA1_V2 0x0000 #define MEMENDADDR2 0x9400 #define MEMENABLE 0xa000 /* 1 byte */ #define ME_V 0x01 #define PROCINTCONF1 0xa800 /* #define PIC1_V 0x100091ff default */ /* 4 bytes */ #define PIC1_V1 0x180a #define PREP_PIC1_V2 0x91ff #define CHRP_PIC1_V2 0x90ff #define PROCINTCONF2 0xac00 /* 4 bytes */ #define PIC2_V1 0x0c06 #define PIC2_V2 0x0c00 #define ERRORENABLE1 0xc000 #define ERRORDETECT1 0xc100 #define ERRORENABLE2 0xc400 #define ERRORDETECT2 0xc500 #define CPU_PCI_EAR 0xc800 /* need initial values for mem bank configs */ #define MEMCONTCONF8A 0xf000 /* 4 bytes */ #define MCC8A_V1 0x0100 /* #define MCC8A_V2 0x82ff */ #define MCC8A_V2 0x8aff #define MEMCONTCONF8B 0xf400 #define MCC8B_V1 0xf707 #define MCC8B_V2 0x0000 #define MEMCONTCONF9A 0xf800 #define MCC9A_V1 0x14d3 #define MCC9A_V2 0x0200 #define MEMCONTCONF9B 0xfc00 #define MCC9B_V1 0x0000 #define MCC9B_V2 0x0000 #endif /* UMC UM8886 ISA Bridge Controller */ /* all values in BE. writes to go to UMC part must set AD[11]. */ #define UM_BASE 0x8080 #define UM_VID 0x0800 /* 2 bytes */ #define UM_DID 0x0802 #define UM_CR 0x0804 #define UM_DSR 0x0806 #define UM_RID_CC 0x0808 /* 4 bytes */ #define UM_PCI_CR 0x0840 /* 1 byte */ #define UM_PCI_ACR 0x0841 #define UM_PCI_APCR 0x0842 #define UM_AB_RCR 0x0843 #define UM_CD_RCR 0x0844 #define UM_SGRB_ADDR 0x0845 #define UM_PCI_IRER 0x0846 #define UM_PROG_REG 0x0847 #define UM_PCI_BMCR 0x0850 #define UM_PCI_BTMR 0x0851 #define UM_NPCI_BMBSR 0x0852 #define UM_NPCI_BMB1SAR 0x0853 #define UM_NPCI_BMB2SAR 0x0854 #define UM_ISA_MPR 0x0855 #define UM_ISA_CDR 0x0856 #define UM_ISA_IORTR 0x0857 #define UM_PMU_OMCR 0x0870 /* 7 bytes */ #define UM_PMU_SMCR 0x0880 /* 2 bytes */ #define UM_PMU_ICR 0x0890 /* 3 bytes */ #define UM_PMU_ECR 0x08a0 /* 1 byte */ #define UM_PMU_MISC1 0x08a2 /* 3 bytes */ #define UM_PMU_MISC2 0x08a8 /* 1 byte */ /* NS PC87323VUL SuperI/O */ /* we ought to be able to just directly write to these offsets. */ #define IO_BASE 0x8000 #define IO_IND_ADDR 0x0398 #define IO_DAT_ADDR 0x0399 /* FER, PTR, and FAR have preset values on reset from CFG0-4. */ /* all I really care about is getting UART1 set up. */ #define IO_FER 0x0000 #define IO_FAR 0x0001 #define IO_PTR 0x0002 #define IO_FCR 0x0003 #define IO_FCR_V 0x00 #define IO_PCR 0x0004 #define IO_PCR_V 0x80 #define IO_KRR 0x0005 #define IO_KRR_V 0x00 #define IO_TUP 0x0007 #define IO_SID 0x0008 #define IO_ASC 0x0009 /* this stuff is important to initialize the DUART channels */ #define Scale 0x01L /* distance between port addresses */ #define COM1 0x000003f8 /* Keyboard */ #define COM2 0x000002f8 /* Host */ /* Port Definitions relative to base COM port addresses */ #define DataIn (0x00*Scale) /* data input port */ #define DataOut (0x00*Scale) /* data output port */ #define BaudLsb (0x00*Scale) /* baud rate divisor least significant byte */ #define BaudMsb (0x01*Scale) /* baud rate divisor most significant byte */ #define Ier (0x01*Scale) /* interrupt enable register */ #define Iir (0x02*Scale) /* interrupt identification register */ #define Lcr (0x03*Scale) /* line control register */ #define Mcr (0x04*Scale) /* modem control register */ #define Lsr (0x05*Scale) /* line status register */ #define Msr (0x06*Scale) /* modem status register */ /* Bit Definitions for above ports */ #define LcrDlab 0x80 /* b7: enable baud rate divisor registers */ #define LcrDflt 0x03 /* b6-0: no parity, 1 stop, 8 data */ #define McrRts 0x02 /* b1: request to send (I am ready to xmit) */ #define McrDtr 0x01 /* b0: data terminal ready (I am alive ready to rcv) */ #define McrDflt (McrRts|McrDtr) #define LsrTxD 0x6000 /* b5: transmit holding register empty (i.e. xmit OK!)*/ /* b6: transmitter empty */ #define LsrRxD 0x0100 /* b0: received data ready (i.e. got a byte!) */ #define MsrRi 0x0040 /* b6: ring indicator (other guy is ready to rcv) */ #define MsrDsr 0x0020 /* b5: data set ready (other guy is alive ready to rcv */ #define MsrCts 0x0010 /* b4: clear to send (other guy is ready to rcv) */ #define IerRda 0xf /* b0: Enable received data available interrupt */ /******************************************************************/