/*	Copyright Motorola, Inc. 1993, 1994
	ALL RIGHTS RESERVED

	You are hereby granted a copyright license to use, modify, and 
	distribute the SOFTWARE so long as this entire notice is retained 
	without alteration in any modified and/or redistributed versions, 
	and that such modified versions are clearly identified as such.  
	No licenses are granted by implication, estoppel or otherwise under 
	any patents or trademarks of Motorola, Inc.

	The SOFTWARE is provided on an "AS IS" basis and without warranty.  
	To the maximum extent permitted by applicable law, MOTOROLA DISCLAIMS 
	ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING IMPLIED 
	WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR 
	PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH 
	REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS 
	THEREOF) AND ANY ACCOMPANYING WRITTEN MATERIALS. 

	To the maximum extent permitted by applicable law, IN NO EVENT SHALL 
	MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER 
	(INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF 
	BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS 
	INFORMATION, OR OTHER PECUNIARY LOSS) ARISING OF THE USE OR 
	INABILITY TO USE THE SOFTWARE.   Motorola assumes no responsibility 
	for the maintenance and support of the SOFTWARE.  

*/


/*
** Only define for BigBend platforms  -  default is no BigBend
*/

/* define BB_BE */


/*  process_type values */

#define PPC601     '1'
#define PPC603     '3'
#define PPC604     '4'
#define PPCART     '5'
#define PPCMAX     '6'
#define PPC755     '7'

/*  ensure this is big so if not defined it will cause an error */
#define MAX_PROCESS_TYPE     'z'  


#define INT_32_BITS


#define D_ACCESS   8			/* 8 bytes */
#define W_ACCESS   4			/* 4 bytes */
#define H_ACCESS   2			/* 2 bytes */
#define B_ACCESS   1			/* 1 bytes */


//---------------------------------------------------------------------------
// Board identifiers.  Used during initialization and later to
// identify board capabilities.

#define YK_X2      0			// Yellowknife X2: EDO, local ROM
#define YK_X4      1			// Yellowknife X4: SDRAM, PCI ROM
#define EXCIMER    2			// Excimer: PBSRAM
#define PMC8240    3		  	// PPMC8240 all alone
#define SP_8240    4			// Sandpoint w/PPMC8240
#define SP_107     5			// Sandpoint w/Altimus or Talos
#define UNIX	   6			// Unix


// MAP B (aka CHRP) -- preferred address map.

#define CHRP_REG_ADDR   0xfec0    // upper half of config_addr in CHRP
#define CHRP_REG_DATA   0xfee0    // upper half of config_data in CHRP
#define CHRP_IO_BASE    0xfe00    // upper 16 bits addr. of IO_BASE in CHRP
#define CHRP_ADDR_MAP   0x0	  	  // set bit 16 of PICR1 to 0 for CHRP mode

// MAP A (aka PREP) -- deprecated, may not be supported on future devs.

#define PREP_REG_ADDR   0x0cf8	  // lower half of config_addr in PREP
#define PREP_REG_DATA   0x0cfc	  // lower half of config_data in PREP
#define PREP_REG_BASE   0x8000    // upper half of data & addr
#define PREP_IO_BASE    0x8000	  // upper 16 bits addr. of IO_BASE in PREP
#define PREP_ADDR_MAP   0x1	  	  // set bit 16 of PICR1 to 1 for PREP mode


#define VENDOR_ID_HI    0x1057    // Vendor ID - Motorola
#define DEVICE_ID_LO    0x0002    // Device ID - Default (MPC106)
#define MPC106_ID_LO    0x0002    // Device ID - MPC106  (Grackle)
#define KAHLUA_ID_LO    0x0003    // Device ID - MPC8240 (Kahlua)
#define MPC107_ID_LO    0x0004    // Device ID - MPC107  (Chaparral)


#define BE_BASE         0x0080    // upper half of MPC106 register addr.

// added defines for autodetect x2/x4 TJD 	using big-endian values

#define BMC_BASE        0x8000    // upper half of Bridge Mem Cont register
								  // addr.
#define BMC_BASE_HIGH   0x800F    // upper half of Bridge Mem Cont register
								  // addr. for high registers


//---------------------------------------------------------------------------
// For an MPC106-controlled L2 cache version of DINK, 
// change 'undef' to 'define'.  See changes in board.h

#undef L2CACHE


//---------------------------------------------------------------------------
// Define DCACHEON to enable L1 Data cache.

#define DCACHEON


//---------------------------------------------------------------------------
// Define ICACHEON to enable L1 Instruction cache.

#define ICACHEON


//---------------------------------------------------------------------------
// Define L2_BACKSIDE_ON to enable L2 backside cache, as on
// an MPC750/755/7400, etc.

#define L2_BACKSIDE_ON


//---------------------------------------------------------------------------
// To build a version of DINK which runs under UNIX (mostly), undefine
// "ON_BOARD" and UNIXDINK will be built.

#define ON_BOARD

#ifndef ON_BOARD
#define UNIXDINK
#endif


//---------------------------------------------------------------------------
/*  RESET_BASE is a define which is used to determine where this 'build'
    of DINK will try to copy itself FROM to RAM.  If this is a bootable
    version of DINK (or MDINK) which is designed to be placed in ROM
    at a given location (generally the reset vector @ 0xfff00100) then
    the value used here should be 0xfff0.  If, however, this version is
    designed to be downloaded and run from a different location (as happens 
    to be the case on Excimer) then the location that it will be downloaded
    to needs to be used in this definition.  In that manner when 'executing'
    this new version the copy routine which is embedded in it will 'know'
    where it is.  On Excimer the MDINK monitor is designed to check for
    the exisitence of a non - 0xffffffff value at location 0xffc00100.  If
    it finds this is the case then it will try to transfer control to that 
    location in a 'blind' jump.  Therefore,  a downloaded and flashed version
    of DINK is designed to be placed in that location.  To build that version 
    of DINK the value of 0xffc0 should be used for RESET_BASE. */

// GM: Note that since YK&SP don't have a large ROM, you can leave this
// at RESET_BASE_EXCIMER and it will work (due to the small ROM
// being replicated throughout the FFCx_xxxx space).


#define RESET_BASE_OTHERS	0xFFF0
#define RESET_BASE_EXCIMER	0xFFC0

#define RESET_BASE 			RESET_BASE_EXCIMER



//---------------------------------------------------------------------------
// Define "RTC_SUPPORT" to enable the the RTC clock functions.

#define RTC_SUPPORT


//---------------------------------------------------------------------------
// Define "BUS_SPEED_DETECT" to enable the reporting of the processor
// core and bus/memory speed.

#define BUS_SPEED_DETECT


//---------------------------------------------------------------------------
// Define "ENV_SUPPORT" to include support for environment variables.
// If defined, automatic startup configuration is enabled.

#define ENV_SUPPORT

// The ENV can be used to tailor L2 settings.  This allows a
// DINK to be built that runs on 750 or 740 since L2 enabling is
// optional and varies based on CPU speed and components used.
// If ENV is not defined, DINK used fixed values for different
// boards.

#define ENV_ENABLES_CACHE


//---------------------------------------------------------------------------
// Define "TAU_SUPPORT" to include support for working with the thermal
// assist unit (TAU).

#define TAU_SUPPORT


//---------------------------------------------------------------------------
// Define "XIO_SUPPORT" to include support for working with the AT keyboard
// for input and VGA for output.

#define XIO_SUPPORT


//---------------------------------------------------------------------------
// Define "HISTORY_SUPPORT" to include support for command-line history.

#define HISTORY_SUPPORT