/*----------- ASM Functions --------*/

/******************************************************
 * agentBoot: agent boot code to be copied to Host Ram.
 *
 *
 *****************************************************/

	.text
	.align 2
	.global agentBoot
agentBoot:
	lis	r9,0xfff0     //setup an address in the
	ori	r9,r9,0x4c00  //outbound translation window
	addi	r0,0,777      //load a value
	stw	r0,4(r9)      //store value
	ori	0,0,0         //no-op
	ori	0,0,0         //no-op
	b	agentBoot
/******************** end agentBoot ******************/


/******************************************************
 * cacheDisable: disable cache
 *  	  input: HID0 mask value in r3
 *   	 output: none
 *****************************************************/

	.text
	.align 2
	.global cacheDisable
cacheDisable:
	mfspr	r4,1008     //load HID0
	and	r4,r4,r3    //and w/ input mask
	mtspr	1008,r4     //store HID0
	blr

/***************** end cacheDisable *****************/


/******************************************************
 * memcpy: copy agentBoot code to memory
 *  input: r3 contains address to copy to
 *         r4 contains address to copy from
 *         r5 contains copy length
 * output: none
 *****************************************************/

	.text
	.align 2
	.global memcpy
memcpy:
	addi	r3,r3,-4    //start load/store address
	addi	r4,r4,-4    //one word back to use stwu, lwzu
loop1:
	lwzu	r6,4(r4)    //load word
	stwu	r6,4(r3)    //store word
	addic.	r5,r5,-1    //decrement counter
	bne	loop1
	blr

/******************* end memcpy *********************/


/******************************************************
 * pciConfigOutHalfWord: write given data half word to 
 *                       given config register.
 *                input: r3 contains config address offset
 *                       r4 contains config data
 *               output: none
 *****************************************************/

	.text
	.align 2
	.global pciConfigOutHalfWord
pciConfigOutHalfWord:
	lis	r5,0x8000    //load config_addr for PCI Slot 4
	ori	r5,r5,0x8000 //on Sandpoint
	or	r3,r3,r5     //attach config register offset
	lis	r5,0xfec0    //load config_addr_reg location
	ori	r5,r5,0x0cf8
	lis	r6,0xfee0    //load config_data_reg location
	ori	r6,r6,0x0cfc
	stwbrx	r3,0,r5      //store config_addr
	sync
	sthbrx	r4,0,r6      //store config_data
	sync
	blr

/**************** end pciConfigOutHalfWord *****************/

/******************************************************
 * pciConfigOutLong: write given data word to given
 *                   config register.
 *            input: r3 contains config address offset
 *                   r4 contains config data
 *           output: none
 *****************************************************/

	.text
	.align 2
	.global pciConfigOutWord
pciConfigOutWord:
	lis	r5,0x8000    //load config_addr for PCI Slot 4
	ori	r5,r5,0x8000 //on Sandpoint
	or	r3,r3,r5     //attach config register offset
	lis	r5,0xfec0    //load config_addr_reg location
	ori	r5,r5,0x0cf8
	lis	r6,0xfee0    //load config_data_reg location
	ori	r6,r6,0x0cfc
	stwbrx	r3,0,r5      //store config_addr
	sync
	stwbrx	r4,0,r6      //store config_data
	sync
	blr

/**************** end pciConfigOutWord *****************/



/******************************************************
 * pgmreturn: program return via DINK exception handler.
 *            Take an illegal opcode exception.
 *     input: none
 *    output: none
 *****************************************************/

	.text
	.align 2
	.global pgmreturn
pgmreturn:
	b	illegal_op   // branch to illegal opcode

/**************** end pgmrtn *****************/


/******************************************************
 * mmuSetup: set up DBAT3 for PCI memory space
 *            
 *    input: none
 *   output: none
 *****************************************************/

	.text
	.align 2
	.global mmuSetup
mmuSetup:
	mfmsr	r3		//turn off tranlations
	lis	r4,0xffff	//disable IR and DR in MSR
	ori	r4,r4,0xffcf
	and	r3,r3,r4
	mtmsr	r3
	isync

	xor	r3,r3,r3
	mtspr	542,r3		//Clear upper DBAT3
	lis	r3,0xFC00	//PCI space lower DBAT3
	ori	r3,r3,0x001A	//R/W, Cachable
	lis	r4,0xFC00	//PCI space upper DBAT3
	ori	r4,r4,0x1fff	//map 1MB 
	mtspr	543,r3		//DBAT3L
	mtspr	542,r4		//DBAT3U
	isync

	mfmsr	r3		//turn on translations
	ori	r3,r3,0x0030
	mtmsr	r3
	isync

	blr

/**************** end mmuSetup *****************/

	.data
	.align 2
illegal_op:
	.long 0x00000000