/* File name: cmdtests.h */
#ifndef CMDTEST_H
#define CMDTEST_H   
/*
 *    cmdtests.h
 *  9/10/99 - 10/20/99  mo
 *  L2CR register definitions for the c program l2backtest.c
 *  these values are used in cmdtests.c and cmdtestutils.s
 */


/* L2 cache parameters */
#define L2CR_L2E          0x80000000 /* bit 0 - enable */
#define L2CR_L2PE         0x40000000 /* bit 1 - data parity */
                    /*  NOTE: motorola interposers do not have L2 parity 
                     *        therefore always set parity off          
                     */
#define L2CR_L2SIZ_1M     0x30000000 /* bits 2-3 1MB */
#define L2CR_L2SIZ_HM     0x20000000 /* bits 2-3 512K */
#define L2CR_L2SIZ_QM     0x10000000 /* bits 2-3 256K */
#define L2CR_L2CLK_1      0x02000000 /* bits 4-6 Clock Ratio div 1 */
#define L2CR_L2CLK_1_5    0x04000000 /* bits 4-6 Clock Ratio div 1.5 */
#define L2CR_L2CLK_2      0x08000000 /* bits 4-6 Clock Ratio div 2 */
#define L2CR_L2CLK_2_5    0x0a000000 /* bits 4-6 Clock Ratio div 2.5 */
#define L2CR_L2CLK_3      0x0c000000 /* bits 4-6 Clock Ratio div 3 */
#define L2CR_L2RAM_BURST  0x01000000 /* bits 7-8 burst SRAM */
#define L2CR_DO           0x00400000 /* bit 9 Enable caching of instr. in L2 */
#define L2CR_L2I          0x00200000 /* bit 10 Global invalidate bit */
#define L2CR_TS           0x00040000 /* bit 13 Test support on  */
#define L2CR_TS_OFF       ~L2CR_TS   /* bit 13 Test support off */
#define L2CR_L2OH_5       0x00000000 /* bits 14-15 Output Hold time = 0.5ns*/
#define L2CR_L2OH_1       0x00010000 /* bits 14-15 Output Hold time = 1.0ns*/
#define L2CR_L2OH_INV     0x00020000 /* bits 14-15 Output Hold time = 1.0ns*/

#define  MPC750_L2_DISABLE    L2CR_L2SIZ_HM + L2CR_L2CLK_2 + \
               L2CR_L2RAM_BURST + L2CR_DO + L2CR_TS + L2CR_L2OH_5 /*0x69440000*/
#define  MPC750_L2_ENABLE    MPC750_L2_DISABLE + L2CR_L2E         /*0xe9440000*/
#define  MPC750_L2_DISABLE_G_INV MPC750_L2_DISABLE + L2CR_L2I     /*0x69640000*/
#define  MPC750_L2_ENABLE_G_INV  MPC750_L2_ENABLE + L2CR_L2I      /*0xe9640000*/

#define  MPC7400_L2_DISABLE    L2CR_L2SIZ_HM + L2CR_L2CLK_2 + \
               L2CR_L2RAM_BURST + L2CR_DO + L2CR_TS + L2CR_L2OH_5 /*0x79440000*/
#define  MPC7400_L2_ENABLE   MPC7400_L2_DISABLE + L2CR_L2E        /*0xf9440000*/
#define  MPC7400_L2_DISABLE_G_INV MPC7400_L2_DISABLE + L2CR_L2I   /*0x79640000*/
#define  MPC7400_L2_ENABLE_G_INV  MPC7400_L2_ENABLE + L2CR_L2I    /*0xf9640000*/

/*  non L2 values  */
#define MPC755  755
#define MPC750  750
#define MPC7400 7400
#define HID0_CACHE_ON    0x0000cc00  /* turn instruction and data cache on */
#define MPC750_CACHE_SIZE   0x080000  /* half meg L2 cache */
#define MPC7400_CACHE_SIZE  0x080000  /* half meg L2 cache */
#define MPC750_MAX_ENCODE   18       /* pmc3 has 17 encodings for Perf Monitor*/
#define MPC7400_MAX_ENCODE  49       /* pmc1 has 48 encodings for Perf Monitor*/
#define L2TESTOUTRANGE_LOOP 5  /* number of times to write/read out of
                                * previously set L2 Cache range
                                */

/*========================================================
 * Variables defined for cmdtestutils.s
 *
 *========================================================*/
/*
 *  6/10/99  MT original definitions
 *  9/10/99  MO
 *  L2CR register definitions for the s program l2backtest.s
 */
/*  register names and numbers */
#define MSR_REG     1027 /* MSR register number */
#define L2CR_REG    1017 /* L2CR register number */
#define HID0_REG    1008 /* HID0 register number */

#define DBAT0U_REG  536 /* Dbat 0 lower register */
#define DBAT0L_REG  537 /* Dbat 0 lower register */
#define DBAT1U_REG  538 /* Dbat 1 lower register */
#define DBAT1L_REG  539 /* Dbat 1 lower register */
#define DBAT2U_REG  540 /* Dbat 2 lower register */
#define DBAT2L_REG  541 /* Dbat 2 lower register */
#define DBAT3U_REG  542 /* Dbat 3 lower register */
#define DBAT3L_REG  543 /* Dbat 3 lower register */

#define IBAT0U_REG  528 /* Dbat 0 lower register */
#define IBAT0L_REG  529 /* Dbat 0 lower register */
#define IBAT1U_REG  530 /* Dbat 1 lower register */
#define IBAT1L_REG  531 /* Dbat 1 lower register */
#define IBAT2U_REG  532 /* Dbat 2 lower register */
#define IBAT2L_REG  533 /* Dbat 2 lower register */
#define IBAT3U_REG  534 /* Dbat 3 lower register */
#define IBAT3L_REG  535 /* Dbat 3 lower register */

#define L2CR_REG    1017
#define MMCR0_REG   952
#define MMCR1_REG   956
#define PMC1_REG    953
#define PMC2_REG    954
#define PMC3_REG    957
#define PMC4_REG    958
#define HID0_REG   1008
#define LR_REG    8




#endif  /*  CMDTEST_H */