/* File name: mytestutils.s */ /***************************************************************** * defines routines used by cmdtest.c * -------------------- * October241999 Jason Villanueva */ /* includes */ #ifdef GCC_REGISTERS #include "gcc_registers.h" #endif /*GCC_REGISTERS */ #define _ASM_LANGUAGE #include "cmdtest.h" /* globals routines */ .global MemInit .global TraceInit .global TraceCheck .global BpInit .global BpCheck .global DbatCheck .global Dbatrestore .global SetupSpin .global Stopspin .global CheckReg .global Breakout .global IBATWrite .global DBATWrite .global MemRead .global WriteMem .global VRWrite .global GPRInit .global GPRCheck .global FPRWrite .global GPRWrite .global MSRRead .global MSRWrite .global HID0Read .global HID0Write .global HID0Init .global BATInit .global DBATURead .global DBATLRead .global IBATURead .global IBATLRead .global cacheFlush .text .align 2 /********************************************************************* * MSRRead - Read the content of the MSR register from the processor. * Input - None * Return - Value of the MSR register in r3. */ MSRRead: mfmsr r3 blr /********************************************************************* * MSRWrite - Write the content of r3 to MSR register * Input - r3 contains new value * Return - None */ MSRWrite: mtmsr r3 isync blr /********************************************************************* * cacheFlush - Flush the L1 and L2 cache by reading 2Mb * Input - None * Return - address of last word flushed from cache */ /********************************************************* **************L1 + L2 CACHE FLUSH OPERATION************ cache flush reads 2megs of data from dink rom-ram space 0x0 to 0x200000. these reads force the cache to dump whatever it has, and since we aren't going to modify anything after the read, it is safe to read this data into the cache This function assumes that there is 0x200000 (= 2Mb dec) bytes of memory either defined in virtual space or in real physical memory.*/ cacheFlush: sync isync flushfunction: lis r3,0x0000 lis r4,0x0020 /* ending value = 0x200000 */ flushhead: cmpw r3,r4 /* done yet? */ bge flushdone /* go to done */ lwz r5,0(r3) /* flush this address by reading it*/ addi r3,r3,0x20 /* increment by cache line size (20 bytes)*/ b flushhead /* repeat */ flushdone: blr /********************************************************************* * HID0Write - Write value to the HID0 register from the processor. * Input - value in r3 * Return - Value in r3. */ HID0Write: sync mtspr HID0_REG,r3 sync blr /********************************************************************* * HID0Read - Read the content of the HID0 register from the processor. * Input - None * Return - Value of the HID0 register in r3. */ HID0Read: mfspr r3, HID0_REG blr /********************************************************************* * HID0Init - Initialize the content of the HID0 register from the processor. * Input - None * Return - Value of the HID0 register in r3. */ HID0Init: mflr r6 /* temporary save of lr value*/ bl cacheFlush /* flush the caches */ mtlr r6 /* restore of lr value */ mfspr r3, HID0_REG ori r3,r3,0xcc00 /* set the i&d cache on and invalidate */ mtspr HID0_REG,r3 isync sync lis r4,0xffff ori r4,r4,0xf3ff /* turn off invalidate bits */ and r3,r3,r4 mtspr HID0_REG,r3 isync sync blr /********************************************************************* * BATInit - Initialize the content of the BAT registers * - Set the bat registers correctly based on the * usual default from dink32 for starting a user program * Input - None * Return - None */ BATInit: isync /* dbat0 for rom, even though I do not use it in this test DINK can use it */ lis r3,0xff00 /* start at low ROM address */ ori r3,r3,0x01ff /* 16mb Vs and Vp set */ lis r4,0xff00 /* start at low ROM address */ ori r4,r4,0x12 /* Write-thru, Cache on, Memory coherence, * no Guard, PP = 10 read/write */ mtspr DBAT0U_REG,r3 mtspr DBAT0L_REG,r4 isync /* dbat1 for ram */ lis r3,0x0000 /* start at low RAM address */ ori r3,r3,0xfff /* 128 Vs and Vp set */ lis r4,0x0000 /* start at low RAM address */ ori r4,r4,0x12 /* Write-thru, Cache on, Memory coherence, * no Guard, PP = 10 read/write */ mtspr DBAT1U_REG,r3 mtspr DBAT1L_REG,r4 isync /* dbat2 ram for yellow knife IO space must be cache off */ lis r3,0xfe00 /* start at RAM 4040 address */ ori r3,r3,0x1ff /* 16 Vs and Vp set */ mtspr DBAT2U_REG,r3 lis r4,0xfe00 /* start at low RAM address */ ori r4,r4,0x32 /* Write-thru, Cache off, Memory coherence, * no Guard, PP = 10 read/write */ mtspr DBAT2L_REG,r4 isync /*=====================================================================*/ .if 0 /* dbat2 ram I/O space for excimer must be cache off*/ lis r3,0x4040 /* start at RAM 4040 address */ ori r3,r3,0x1ff /* 16 Vs and Vp set */ mtspr DBAT2U_REG,r3 lis r4,0x4040 /* start at low RAM address */ ori r4,r4,0x32 /* Write-thru, Cache on, Memory coherence, * no Guard, PP = 10 read/write */ mtspr DBAT2L_REG,r4 isync .endif /*========================================================================*/ /* dbat3 diabled */ lis r3,0 mtspr DBAT3U_REG,r3 mtspr DBAT3L_REG,r3 isync /* always isync after changing bat registers */ /* ibat0 for rom, even though I do not use it in this test DINK can use it */ lis r3,0xff00 /* start at low ROM address */ ori r3,r3,0x01ff /* 16mb Vs and Vp set */ mtspr IBAT0U_REG,r3 lis r3,0xff00 /* start at low ROM address */ ori r3,r3,0x12 /* Write-thru, Cache on, Memory coherence, * no Guard, PP = 10 read/write */ mtspr IBAT0L_REG,r3 isync /* always isync after changing bat registers */ /* ibat1 for ram */ lis r3,0x0000 /* start at low RAM address */ ori r3,r3,0xfff /* 128 Vs and Vp set */ mtspr IBAT1U_REG,r3 lis r3,0x0000 /* start at low RAM address */ ori r3,r3,0x12 /* Write-thru, Cache on, Memory coherence, * no Guard, PP = 10 read/write */ mtspr IBAT1L_REG,r3 isync /* always isync after changing bat registers */ /* ibat2 rom yellow knife IO space must be cache off*/ lis r3,0xfe00 /* start at low RAM address */ ori r3,r3,0x1ff /* 16 Vs and Vp set */ mtspr IBAT2U_REG,r3 lis r3,0xfe00 /* start at low RAM address */ ori r3,r3,0x32 /* Write-thru, Cache off, Memory coherence, * no Guard, PP = 10 read/write */ mtspr IBAT2L_REG,r3 isync /* always isync after changing bat registers */ /*=====================================================================*/ .if 0 /* ibat2 rom IO space for excimer must be cache off*/ lis r3,0x4040 /* start at low RAM address */ ori r3,r3,0x1ff /* 16 Vs and Vp set */ mtspr IBAT2U_REG,r3 lis r3,0x4040 /* start at low RAM address */ ori r3,r3,0x32 /* Write-thru, Cache off, Memory coherence, * no Guard, PP = 10 read/write */ mtspr IBAT2L_REG,r3 isync /* always isync after changing bat registers */ .endif /*=====================================================================*/ /* ibat3 diabled */ lis r3,0 mtspr IBAT3U_REG,r3 mtspr IBAT3L_REG,r3 isync /* always isync after changing bat registers */ blr /********************************************************************* * DBATURead - Read the content of DBATU register * Input - which DBAT 0,1,2, or 3 * Return - r3 contains DBATU register value */ DBATURead: cmpwi cr0,r3,0x0 bne DBATU_next1 mfspr r3,DBAT0U_REG blr DBATU_next1: cmpwi cr0,r3,0x1 bne DBATU_next2 mfspr r3,DBAT1U_REG blr DBATU_next2: cmpwi cr0,r3,0x2 bne DBATU_next3 mfspr r3,DBAT2U_REG blr DBATU_next3: cmpwi cr0,r3,0x3 bne DBATU_next4 mfspr r3,DBAT3U_REG blr DBATU_next4: /* invalid DBAT register request */ lis r3,0xdead ori r3,r3,0xbeef blr /********************************************************************* * DBATLRead - Read the content of DBATL register * Input - which DBAT 0,1,2, or 3 * Return - r3 contains DBATL register value */ DBATLRead: cmpwi cr0,r3,0x0 bne DBATL_next1 mfspr r3,DBAT0L_REG blr DBATL_next1: cmpwi cr0,r3,0x1 bne DBATL_next2 mfspr r3,DBAT1L_REG blr DBATL_next2: cmpwi cr0,r3,0x2 bne DBATL_next3 mfspr r3,DBAT2L_REG blr DBATL_next3: cmpwi cr0,r3,0x3 bne DBATL_next4 mfspr r3,DBAT3L_REG blr DBATL_next4: /* invalid DBAT register request */ lis r3,0xdead ori r3,r3,0xbeef blr /********************************************************************* * IBATURead - Read the content of IBATU register * Input - which IBAT 0,1,2, or 3 * Return - r3 contains IBATU register value */ IBATURead: cmpwi cr0,r3,0x0 bne IBATU_next1 mfspr r3,IBAT0U_REG blr IBATU_next1: cmpwi cr0,r3,0x1 bne IBATU_next2 mfspr r3,IBAT1U_REG blr IBATU_next2: cmpwi cr0,r3,0x2 bne IBATU_next3 mfspr r3,IBAT2U_REG blr IBATU_next3: cmpwi cr0,r3,0x3 bne IBATU_next4 mfspr r3,IBAT3U_REG blr IBATU_next4: /* invalid IBAT register request */ lis r3,0xdead ori r3,r3,0xbeef blr /********************************************************************* * IBATLRead - Read the content of IBATL register * Input - which IBAT 0,1,2, or 3 * Return - r3 contains IBATL register value */ IBATLRead: cmpwi cr0,r3,0x0 bne IBATL_next1 mfspr r3,IBAT0L_REG blr IBATL_next1: cmpwi cr0,r3,0x1 bne IBATL_next2 mfspr r3,IBAT1L_REG blr IBATL_next2: cmpwi cr0,r3,0x2 bne IBATL_next3 mfspr r3,IBAT2L_REG blr IBATL_next3: cmpwi cr0,r3,0x3 bne IBATL_next4 mfspr r3,IBAT3L_REG blr IBATL_next4: /* invalid IBAT register request */ lis r3,0xdead ori r3,r3,0xbeef blr /******************************************************************** * SetupSpin - Used to initialize GPR 22 to known value. This will * be used to break out of spin loop. * Input - None * Ouput - None */ SetupSpin: li r22,0x1234 isync blr /******************************************************************* * CheckReg - Used to determine if r22 has been modified. Returns * 1 if r22 has changed, 0 if not. * Input - None * Output - 1 if r22 changed, 0 if not */ CheckReg: cmpwi cr0,r22,0x1234 bne Stopspin li r3,0x0 blr Stopspin: li r3,0x1 blr /******************************************************************** * GPRInit - used to set r13-r16 with value of zero. * Input - None * Ouput - None */ GPRInit: li r13,0x0 li r14,0x0 li r15,0x0 li r16,0x0 blr /************************************************************************* * GPRWrite - Used to update r13-r16 with corresponding value. * Input - None * Ouput - None */ GPRWrite: li r13,0x13 li r14,0x14 li r15,0x15 li r16,0x16 blr /*********************************************************************** * GPRCheck - Used to constantly compare r13-r16 and returns when one * of the registers has been modified. * Input - None * Ouput - None */ GPRCheck: cmpwi cr0,r13,0x13 bne Breakout cmpwi cr0,r14,0x14 bne Breakout cmpwi cr0,r15,0x15 bne Breakout cmpwi cr0,r16,0x16 bne Breakout b GPRCheck Breakout: blr /******************************************************************** * FPRWrite - NOT COMPLETE. */ FPRWrite: lis r22,0x9 ori r22,r22,0x412c sync lfd f10,0(r22) blr /******************************************************************** * VRWrite - NOT COMPLETE */ VRWrite: #ifdef GCC_REGISTERS loopforever: b loopforever #else stvx v5,r0,r23 blr #endif /******************************************************************* * MemInit - Used to initialize locations in memory to zero. * Locations in memory are from MYSPACE array defined in * main function. * Input - None * Ouput - None */ MemInit: li r14,0x0 li r15,0x10 lis r16,0x9 ori r16,r16,0x403c sync stw r14,0(r16) stw r14,4(r16) stw r14,8(r16) stw r14,12(r16) dcbf r14,r16 dcbf r15,r16 sync blr /************************************************************************ * WriteMem - Used to modify locations in memory. * Input - None * Ouput - None */ WriteMem: li r17,0x1111 li r18,0x2222 li r19,0x3333 li r20,0x4444 sync stw r17,0(r16) stw r18,4(r16) stw r19,8(r16) stw r20,12(r16) dcbf r14,r16 dcbf r15,r16 sync blr /*********************************************************************** * IBATWrite - NOT COMPLETE */ IBATWrite: lis r3,0xff00 ori r3,r3,0x7ff mtspr IBAT0U_REG,r3 sync lis r3,0xff00 ori r3,r3,0x32 mtspr IBAT0L_REG,r3 sync blr /************************************************************************ * DBATWrite - Loads GPRs with initial values of DBATs in order to * restore them to their original values. Alters DBATs and * used for comparison in black box. * Input - None * Ouput - None */ DBATWrite: mfspr r14,DBAT0U_REG mfspr r15,DBAT1U_REG mfspr r16,DBAT2U_REG mfspr r17,DBAT3U_REG lis r3,0xff00 ori r3,r3,0x7ff mtspr DBAT0U_REG,r3 sync lis r3,0x0 ori r3,r3,0x7ff mtspr DBAT1U_REG,r3 sync lis r3,0xfe00 ori r3,r3,0x7ff mtspr DBAT2U_REG,r3 sync lis r3,0x0 ori r3,r3,0x7ff mtspr DBAT3U_REG,r3 sync mfspr r22,DBAT0L_REG mfspr r23,DBAT1L_REG mfspr r24,DBAT2L_REG mfspr r25,DBAT3L_REG lis r3,0xff00 ori r3,r3,0x32 mtspr DBAT0L_REG,r3 sync lis r3,0x0 ori r3,r3,0x32 mtspr DBAT1L_REG,r3 sync lis r3,0xfe00 ori r3,r3,0x12 mtspr DBAT2L_REG,r3 sync lis r3,0x0 ori r3,r3,0x32 mtspr DBAT3L_REG,r3 sync blr /******************************************************************** * DbatCheck - Used to check write function of DBATs. Breaks out of * loop when a modification on DBAT3U occurs. * Input - None * Ouput - None */ DbatCheck: mfspr r14,DBAT0U_REG mfspr r15,DBAT1U_REG mfspr r16,DBAT2U_REG mfspr r17,DBAT3U_REG mfspr r22,DBAT0L_REG mfspr r23,DBAT1L_REG mfspr r24,DBAT2L_REG mfspr r25,DBAT3L_REG sync cmpwi cr0,r15,0xfff bne Dbatrestore cmpwi cr0,r17,0x0 bne Dbatrestore b DbatCheck /********************************************************************** * Dbatrestore - restores DBATs to initial values before modifications * Input - None * Ouput - None */ Dbatrestore: mtspr DBAT0U_REG,r14 mtspr DBAT1U_REG,r15 mtspr DBAT2U_REG,r16 mtspr DBAT3U_REG,r17 mtspr DBAT0L_REG,r22 mtspr DBAT1L_REG,r23 mtspr DBAT2L_REG,r24 mtspr DBAT3L_REG,r25 sync blr /******************************************************************** * BpInit - Used to initialize r14-r17 to zero. * Input - None * Ouput - None */ BpInit: li r14,0x0 li r15,0x0 li r16,0x0 li r17,0x0 sync blr /******************************************************************* * BpCheck - Used to write to registers line by line. Breakpoint * will be setup right after lis command. dead beef * should not be written to the registers is bp work * Input - None * Ouput - None */ BpCheck: li r14,0x14 li r15,0x15 lis r16,0x0 ori r16,r16,0xdead lis r17,0x0 ori r17,r17,0xbeef sync blr /********************************************************************* * TraceInit - Used to initialize r14-r19 to zero * Input - None * Ouput - None */ TraceInit: li r14,0x0 li r15,0x0 li r16,0x0 li r17,0x0 li r18,0x0 li r19,0x0 sync blr /********************************************************************** * TraceCheck - Trace will be setup at beginning of routine and allow * user to step through each line. * Input - None * Ouput - None */ TraceCheck: b TraceCheck li r14,0x14 li r15,0x15 li r16,0x16 li r17,0x17 li r18,0x18 li r19,0x19 blr /************************************************************ * MemRead - Returns the contents of the requested memory * location. * Input - value in r3 * Ouput - value in r3 */ MemRead: sync li r14,0x0 dcbf r14,r3 sync lwz r15,0(r3) sync or r3,r14,r15 sync blr