l1test.readme
3/14/00   mo

	This is an L1 cache test.  It can be compiled to run in dink32 as a 
downloadable srecord file or as a standalone elf executable.

	There are three makefiles, makefile for unix and makefile_pc for 
the pc. Both use the Metaware tool chain. makefile_gcc for unix using the 
GNU GCC tool chain.


	The test can be made in two versions:

1.  Run under dink32.  make target is l1testdink
    make l1testdink
    This make requires the two files, dinkusr.s and dinkusr.h, which
    can be obtained from any dink32 release of R12.0 or later.
    This make will only work with dink32 R12.0 or later.
    dl -k    (download l1test.src)
    go       (runs the test and prints the pass/fail results.
   

2.  Run standalone.    make target is l1teststdalone
    make l1teststdalone
    use an ICE like AMC powertap to download the l1teststd.out file.
    Using the xrefstd.txt file find the address of loopforever
    set a breakpoint at loopforever
    Run the test
    stop the processor
    display memory addresses 9a000-9a008 and 9a010-9a018
    The pass pattern is 0x0101010101
    The failing pattern is 0x11111111

	Synopsys of the test.
	
/***********************************************************************
Updated: 3/14/00  mo

    Purpose:
       To initialize the MPC60x/MPC750 and perform rudimentary memory/cache 
       test.
       These tests are not meant to be exhaustive.  They are a simple check
       that can be used to determine if things are getting written into
       memory and cache as expected.  They do not test all the different
       possible combinations of BAT-mapped cache-inhibited regions, write-
       through and write back modes, cache sizes, etc.

   NOTE: This code will only test L1 cache.  The sizes of the data
         accesses needs to be increased if testing L2.

         Also, this code only tests data cache - instruction cache is
         a different beast since it's not allowed to contain
         modified data.


    Register and Memory usage:
        registers r13, r3, and r4 have special uses - don't use them
        for anything else.

        R13 - holds address of location for current test result
        R3  - holds lr value for the entire cache test routine
        R4  - holds lr value for individual routines that call bl to
              branch elsewhere

        This test uses memory regions from 0x0009a000 - 0x0009a020
        and 0x000a0000 to 0x000b0000.  

    This code is meant to be run shortly after a hard reset when the caches
        are marked invalid and address translation is enabled.  The caches
        are also marked invalid on power-on or hard reset. Modifications 
        are necessary to put the caches and MMU into the correct state if this 
        code is not run from hard reset.

    Results:
	Result values are:
	   0x10101010 indicates passed the test
	   0x11111111 indicates failed the test
	The location of the result values are as follows:
           Write Through Test 1 0x0009a000
           Write Through Test 2 0x0009a004
           Write Through Test 3 0x0009a008
           Write Back    Test 1 0x0009a010
           Write Back    Test 2 0x0009a014
           Write Back    Test 4 0x0009a018
	Patterns are:
	   zero: all zeros
	   neg:  the negative value of the address of the data

    Algorithm:
	1.  
          system_reset:
	    Save the lr and dbat1, which is the IO area address.
	    initialize the bats, the msr, and the hid0 register.
	    call the cache_test_routine
	    IF $(DINK) under control of dink then 
               return to caller with r3=answer vector
	    else
	       loop in loopforever so the user and stop it and look at the 
               results
	2.  
          cache_test_routine
	    invalidate and enable the L2 cache
	    put ram in write through mode
	    Call the cache_test_1, 2, and 3 routines.
	          Note: test 3 is for write through mode only.
	    put ram in write back mode
	    Call the cache_test_1, 2, and 4 routines.
	          Note: test 4 is for write back mode only.
	3.
	  cache_test_1
	    Turn on and invalidate the cache
	    fill the cache with the neg pattern.
	    read the data
	    verify that it is the neg pattern.
	    
	4.
	  cache_test_2
	    Turn on and invalidate the cache
	    fill the cache with the zero pattern.
	    Turn off the cache
	    fill the cache with the neg pattern.
	    turn on the cache
	    read the data
	    verify that it is the neg pattern.
	       because writing to memory with a disabled cache
	       will invalidate the cache entries for those addresses.
	       so expect the neg pattern which was written to overwrite
	       the first pattern of zeros.
	5.
	  cache_test_3
	    Write through mode only
	    Turn on and invalidate the cache
	    fill the cache with the zero pattern.
	    read the zero pattern and verify it
	    fill the cache with the neg pattern.
	    invalidate the cache
	    read the data
	    verify that it is the neg pattern.
	         because write through mode will write the data to memory
	         and the cache simultaneously
	    
	6.
	  cache_test_4
	    Write back mode only
	    Turn on and invalidate the cache
	    (store) fill the cache with the zero pattern.
	    flush the cache to memory
	    read the zero pattern and verify it
	    (store) fill the cache with the neg pattern.
	    invalidate the cache
	    read the data
	    verify that it is the zero pattern.
	         because write back mode will not write the data to memory
	         and the cache simultaneously hence the data in the cache
	         is lost when it is invalidated.