Configuration Register Decoder Version 0.8 July 10, 2000 Enter a description of this data, 60 characters or less >>Data set: MPC106 registers from Maurie Little Endian order Please chose one of the following by number 1,2,3, or 4: 1. MPC106 Rev 4.0 2. MPC107 3. MPC8240 Host 4. MPC8240 Agent >>Choose printing order: 1. Big endian order 2. Little endian order You chose Little endian order for printing MPC106 Decoder Enter all values in hex, DO NOT preceed them with 0x Only use word boundry addresses, e.g. 0,4,8,etc Values are in little endian orientation and will be padded with zeros on the left Enter address : value Example: 04 : a00106 Enter "^D" i.e. EOF to exit >> Reg00 Device ID and Vendor ID = 0x00021057 0x02:Device ID = 0x0002 0x00:Vendor ID = 0x1057 >> Reg04 PCI Status/Command = 0xFFFFFFFF 0x06:PCI Status = 0Xffff Detected Parity Error = 0x1 Parity Error is detected Signaled System abort = 0x1 SEER is asserted Received Master-abort = 0x1 PCI master issued PCI abort Received Target-abort = 0x1 Target terminated PCI abort Signaled Target-abort = 0x1 Target issued abort to PCi master DEVSEL Use fast device Timing = 0x6 ERROR => should be zero Data Parity Detected = 0x1 Data Partity detected Fast Back To Back = 0x1 unnamed bit 6 = 0x1 ERROR => should be zero 66-MHz capable = 0x1 66-MHz capable unnamed bits 0-4 = 0x1f ERROR => should be zero 0x04:PCI Command = 0xffff unnamed bit 15 = 0x1 ERROR => should be zero Read_Lock = 0x1 MPC106 V4.0 mode unnamed bits 13-10 = 0xf ERROR => should be zero Fast Back to back = 0x1 ERROR => should be zero SERR = 0x1 SERR driver enabled unnamed bit 7 = 0x1 ERROR => should be zero Parity Error Response = 0x1 Parity errors take action unnamed bit 5 = 0x1 ERROR => should be zero Memory Write and Invalidate = 0x1 Use Memory Write and Invalidate Special Cycles = 0x1 ERROR => should be zero Bus Master = 0x1 Enabled Memory Space = 0x1 Respond to PCI memory accesses I/O Space = 0x1 ERROR => should be zero >> Reg04 PCI Status/Command = 0x00000000 0x06:PCI Status = 0X0000 Detected Parity Error = 0x0 Parity Error not detected Signaled System abort = 0x0 SEER not asserted Received Master-abort = 0x0 No PCI master abort Received Target-abort = 0x0 No PCI target abort received Signaled Target-abort = 0x0 No PCI target abort issued DEVSEL Use fast device Timing = 0x0 Data Parity Detected = 0x0 No Data Partity detected Fast Back To Back = 0x0 ERROR => should be one unnamed bit 6 = 0x0 66-MHz capable = 0x0 Not 66-MHz capable unnamed bits 0-4 = 0x0 0x04:PCI Command = 0x0000 unnamed bit 15 = 0x0 Read_Lock = 0x0 MPC106 V3.0 mode unnamed bits 13-10 = 0x0 Fast Back to back = 0x0 SERR = 0x0 SERR driver disabled unnamed bit 7 = 0x0 Parity Error Response = 0x0 Parity errors are ignored unnamed bit 5 = 0x0 Memory Write and Invalidate = 0x0 Use Memory Write Special Cycles = 0x0 Bus Master = 0x0 Disabled Memory Space = 0x0 Do not respond to PCI memory accesses I/O Space = 0x0 >> Reg08 Class Code, Subclass Code, Standard Programming, Revision ID = 0x12345678 0x0b:Base Class Code = 0x12 0x0a:Subclass Code = 0x34 0x09:Standard Programing Interface = 0x56 0x08:Revision ID = 0x78 >> Reg48 CMDR Perfrm Mon Cmd Reg = 0x00000000 THRESHOLD_L lower = 0x0 THRESHOLD_U upper = 0x0 EVENT_L lower = 0x0 Unnamed bits 12-8 = 0x0 COUNTER which counter = 0x0 PMC0 CMD_TYPE which table = 0x0 Use Table 12 EVENT_U upper = 0x0 >> Reg48 CMDR Perfrm Mon Cmd Reg = 0xffffffff THRESHOLD_L lower = 0xff THRESHOLD_U upper = 0xff EVENT_L lower = 0x7 Unnamed bits 12-8 = 0x1f ERROR => should be zero COUNTER which counter = 0x3 PMC3 CMD_TYPE which table = 0x1 Use Table 13 EVENT_U upper = 0x1f >> Reg4c MMCR Perfrm Mon Mode Reg= 0x00000000 OVERFLOW 0-1 PMC0 into PMC1 = 0x0 Disabled OVERFLOW 2-3 PMC2 into PMC3 = 0x0 Disabled Unnamed bits 13-8 = 0x0 ENABLE counters = 0x0 Disabled DISCOUNT PMCx msb from 0 to 1 = 0x0 counters continue to increment Unnamed bits 5-1 = 0x0 PMCTRG PMC0 msb from 0 to 1 = 0x0 enable counters ignore msb >> Reg4c MMCR Perfrm Mon Mode Reg= 0xffffffff OVERFLOW 0-1 PMC0 into PMC1 = 0x1 Enabled OVERFLOW 2-3 PMC2 into PMC3 = 0x1 Enabled Unnamed bits 13-8 = 0x1f ERROR => should be zero ENABLE counters = 0x1 Enabled DISCOUNT PMCx msb from 0 to 1 = 0x1 PMC0 stops Unnamed bits 5-1 = 0x1f ERROR => should be zero PMCTRG PMC0 msb from 0 to 1 = 0x1 disable counters until msb >> Reg50 PMC0 Perfrm Mon Counter = 0x00000021 >> Reg54 PMC1 Perfrm Mon Counter = 0x00000030 >> Reg58 PMC2 Perfrm Mon Counter = 0x12345678 >> Reg5c PMC3 Perfrm Mon Counter = 0x00abcdef >> Reg70 Power Management & Output Driver = 0xffffffff 0x73:Output Driver Config Reg = 0xFF PCI_AD address/data signal driver = 0x1 20 ohm control PCI_CTRL control signal driver = 0x1 20 ohm control PROC_A address bus singal driver = 0x1 20 ohm control Combined MEM_CTRL2 & MEM_CTRL1 = 0x3 8 ohm control MEM_CTRL2 mem signal driver = 0x1 PROC_A address bus signal driver = 0x1 20 ohm control PROC_CTRL1 proc/L2 signal 1 = 0x1 20 ohm control PROC_CTRL2 proc/L2 signal 2 = 0x1 20 ohm control MEM_CTRL1 mem signal driver = 0x1 0x72:Power Management Register 2 = 0xFF Shared MPC = 0x1 High Impedence except on error unnammed bit 7 - 1 = 0x7F ERROR => should be zero 0x70:Power Management Register 1 = 0xFFFF No Nap Msg Halt command Broadcast = 0x1 Does not broadcast HALT No Sleep Message Broadcast = 0x1 Does not broadcast SLEEP Sleep Message Type = 0x1 Broadcast SHUTDOWN Low Power Refresh = 0x1 Perform mem refresh in SLEEP NO_604_RUN assert QUAK on wake = 0x1 Yes 601_NEED_QREQ use the QREQ nap = 0x1 Required Suspend Mode QACK* = 0x1 QACK* is asserted in suspend mode unnammed bits 9 - 8 = 0x1 ERROR => should be zero Power Management Enable = 0x1 Enabled unnammed bit 6 = 0x1 ERROR => should be zero Doze Mode = 0x1 Enables Doze mode Nap Mode = 0x1 Disables Nap mode Sleep Mode = 0x1 Enables Sleep mode Selects Clock Source = 0x30 BR1_WAKE awareness of other CPUs = 0x1 Ignored during nap and sleep >> Reg70 Power Management & Output Driver = 0x00000000 0x73:Output Driver Config Reg = 0x00 PCI_AD address/data signal driver = 0x0 40 ohm control PCI_CTRL control signal driver = 0x0 40 ohm control PROC_A address bus singal driver = 0x0 40 ohm control Combined MEM_CTRL2 & MEM_CTRL1 = 0x0 Reserved do not use MEM_CTRL2 mem signal driver = 0x0 PROC_A address bus signal driver = 0x0 40 ohm control PROC_CTRL1 proc/L2 signal 1 = 0x0 40 ohm control PROC_CTRL2 proc/L2 signal 2 = 0x0 40 ohm control MEM_CTRL1 mem signal driver = 0x0 0x72:Power Management Register 2 = 0x00 Shared MPC = 0x0 Always drive MPC* unnammed bit 7 - 1 = 0x0 0x70:Power Management Register 1 = 0x0000 No Nap Msg Halt command Broadcast = 0x0 Broadcast HALT No Sleep Message Broadcast = 0x0 Broadcast SLEEP Sleep Message Type = 0x0 Broadcast HALT Low Power Refresh = 0x0 Don't perform mem refresh in SLEEP NO_604_RUN assert QUAK on wake = 0x0 No 601_NEED_QREQ use the QREQ nap = 0x0 Not Required Suspend Mode QACK* = 0x0 QACK* not asserted in suspend mode unnammed bits 9 - 8 = 0x0 Power Management Enable = 0x0 Disabled unnammed bit 6 = 0x0 Doze Mode = 0x0 Disables Doze mode Nap Mode = 0x0 Disables Nap mode Sleep Mode = 0x0 Disables Sleep mode Selects Clock Source = 0x0 Disable the test clock driver BR1_WAKE awareness of other CPUs = 0x0 Ignored during nap and sleep >> Reg70 Power Management & Output Driver = 0x12345678 0x73:Output Driver Config Reg = 0x12 PCI_AD address/data signal driver = 0x0 40 ohm control PCI_CTRL control signal driver = 0x0 40 ohm control PROC_A address bus singal driver = 0x0 40 ohm control Combined MEM_CTRL2 & MEM_CTRL1 = 0x2 13 ohm control MEM_CTRL2 mem signal driver = 0x1 PROC_A address bus signal driver = 0x0 40 ohm control PROC_CTRL1 proc/L2 signal 1 = 0x0 40 ohm control PROC_CTRL2 proc/L2 signal 2 = 0x1 20 ohm control MEM_CTRL1 mem signal driver = 0x0 0x72:Power Management Register 2 = 0x34 Shared MPC = 0x0 Always drive MPC* unnammed bit 7 - 1 = 0x1A ERROR => should be zero 0x70:Power Management Register 1 = 0x5678 No Nap Msg Halt command Broadcast = 0x0 Broadcast HALT No Sleep Message Broadcast = 0x1 Does not broadcast SLEEP Sleep Message Type = 0x0 Broadcast HALT Low Power Refresh = 0x1 Perform mem refresh in SLEEP NO_604_RUN assert QUAK on wake = 0x0 No 601_NEED_QREQ use the QREQ nap = 0x1 Required Suspend Mode QACK* = 0x1 QACK* is asserted in suspend mode unnammed bits 9 - 8 = 0x0 Power Management Enable = 0x0 Disabled unnammed bit 6 = 0x1 ERROR => should be zero Doze Mode = 0x1 Enables Doze mode Nap Mode = 0x1 Disables Nap mode Sleep Mode = 0x1 Enables Sleep mode Selects Clock Source = 0x30 BR1_WAKE awareness of other CPUs = 0x0 Ignored during nap and sleep >> Rega8 PICR1 Processor Interface Config 1= 0x12345678 CF_CBA_MASK L2 copy back addr mask = 0x12 CF_BREAD_WS Burst Read Wait States = 0x0 0 wait state (2:1 clock) CF_CACHE_1G L2 cache addresses = 0x1 0 to 1 Gbyte addresses RCS0 ROM Location = 0x1 Processor/memory data Bus XIO_MODE Map A mode = 0x0 Contiguous PROC_TYPE Processor Type = 0x2 603x, 7xx, and 74xx ADDRESS_MAP = 0x0 Map B CF_MP_ID Multiprocessor ID = 0x1 Reserved do not use CF_LBA_EN Local Bus Slave enable = 0x0 Disabled FLASH_WR_EN Flash Write enable = 0x1 Enabled MPC_EN Machine Check enable = 0x0 Disabled TEA_EN TEA enable = 0x1 Enabled CF_DPARK data bus park = 0x1 Enabled CF_EXTERNAL_L2 enable = 0x0 Disabled NO_PORT_REGS Map A ext config regs = 0x0 Implemented ST_GATH_EN Store gathering = 0x1 Enabled LE_MODE Little Endian MODE = 0x1 Big-Endian Mode CF_LOOP_SNOOP Repeat Snoops = 0x1 Enabled CF_APARK Processor Parked on 60x = 0x1 Last processor Speculative PCI Reads = 0x0 Disabled CF_MP Multiprocessor configuration = 0x0 Uniprocessor >> Regac PICR2 Processor Interface Config 2= 0x12345678 L2_UPDATE_EN L2 update enable = 0x0 Enabled L2_EN L2 cache enable = 0x0 Disabled NO_SERIAL_CFG serialize wr to PCI = 0x0 Yes NO_SNOOP_EN snoop transactions = 0x0 Enabled CF_FF0_LOCAL remapping enable = 0x0 Disabled FLASH_WR_LOCKOUT write lockout = 0x1 Disabled CF_FAST_L2_MODE fast mode disable = 0x0 Disabled CF_DATA_RAM_TYPE L2 RAM type = 0x0 Synchronous burst SRAM CF_WMODE SRAM write timing = 0x3 Early with partial update CF_SNOOP_WS Snoop wait states = 0x1 1 wait state CF_MOD_HIGH Cache modified sig = 0x0 Active low CF_HIT_HIGH L2 HIT* signal = 0x0 Active low unnamed bit 15 = 0x0 CF_ADDR_ONLY_DISABLE clean,flush,kill = 0x1 Ignore CF_HOLD L2 tag address hold = 0x0 Synchronous tag RAM CF_INV_MODE L2 Invalidate Mode = 0x1 Enabled CF_RWITM_FILL line fill disable = 0x0 Enabled CF_L2_HIT_DELAY = 0x3 3 clock cycles CF_TWO_BANKS L2 cache banks = 0x00 1 SRAM Bank CF_FAST_CACTOUT timing = 0x0 Normal CF_TOE_WIDTH TOE active pulse width= 0x00 2 clock cycles L2 cache size = 0x3 Reserved do not use CF_APHASE_WS address phase wait sts= 0x0 0 wait states CF_DOE L2 first data read timing = 0x0 1 or 2 clock cycle CF_WDATA = 0x0 >> Regac PICR2 Processor Interface Config 2= 0xffffffff L2_UPDATE_EN L2 update enable = 0x1 Disabled L2_EN L2 cache enable = 0x1 Enabled NO_SERIAL_CFG serialize wr to PCI = 0x1 No NO_SNOOP_EN snoop transactions = 0x1 Disabled CF_FF0_LOCAL remapping enable = 0x1 Enabled FLASH_WR_LOCKOUT write lockout = 0x1 Disabled CF_FAST_L2_MODE fast mode disable = 0x1 Enabled CF_DATA_RAM_TYPE L2 RAM type = 0x3 Reserved do not use CF_WMODE SRAM write timing = 0x3 Early with partial update CF_SNOOP_WS Snoop wait states = 0x3 3 wait states CF_MOD_HIGH Cache modified sig = 0x1 Active high CF_HIT_HIGH L2 HIT* signal = 0x1 Active high unnamed bit 15 = 0x1 ERROR => should be zero CF_ADDR_ONLY_DISABLE clean,flush,kill = 0x1 Ignore CF_HOLD L2 tag address hold = 0x1 Asynchronous tag RAM CF_INV_MODE L2 Invalidate Mode = 0x1 Enabled CF_RWITM_FILL line fill disable = 0x1 Disabled CF_L2_HIT_DELAY = 0x3 3 clock cycles CF_TWO_BANKS L2 cache banks = 0x01 2 SRAM Bank CF_FAST_CACTOUT timing = 0x1 Fast CF_TOE_WIDTH TOE active pulse width= 0x01 3 clock cycles L2 cache size = 0x3 Reserved do not use CF_APHASE_WS address phase wait sts= 0x3 3 wait states CF_DOE L2 first data read timing = 0x1 2 or 3 clock cycle CF_WDATA = 0x1 >> Regb8 ECC Single Bit Error = 0x12345678 unnamed bits 7 - 1 = 0x9 ERROR => should be zero FLASH_WR_EN flash write = 0x0 Disabled 0xbb:Alternate OS-Visible Reg2= 0x12 unnamed bits 7 - 6 = 0x0 RX_SERR_EN SEER* assertion = 0x0 Ignore unnamed bits 4 - 3 = 0x2 ERROR => should be zero XIO_MODE Map A mode = 0x1 Contiguous TEA_EN Transfer Error Ack = 0x0 Disabled MCP_EN Machine check enable = 0x0 Disabled 0xba:Alternate OS-Visible Reg1= 0x34 0xB9:ECC single bit Trigger = 0x56 single bit error threshold 0xb8:ECC single bit counter = 0x78 >> Regc0 Error Enabling and detection 1 = 0x12345678 0xc3:60x Bus Error Status = 0x12 Copy of TT on processor bus error = 0x02 Copy TSIZ on processor bus error = 0x2 0xc2:unnamed bits 23 - 17 = 0x34 ERROR => should be zero 0xc1:Error Detection 1 = 0x56 PCI SERR* two clks after address = 0x0 No error detected PCI target PERR* parity error = 0x1 error detected Memory Select Error = 0x0 No error detected Memory refresh overflow error = 0x1 error detected 60x/PCI cycle error occurred = 0x0 on processor-init cycle Memory Read Parity ECC trigger = 0x1 Parity or ECC trigger Unsupported 60x Transaction = 0x02 XATS* detected 0xc0:Error Enabling 1 = 0x78 PCI received error = 0x0 Disabled PCI target PERR* = 0x1 Enabled Memory select = 0x1 Enabled Memory refresh overflow = 0x1 Enabled PCI master PERR* = 0x1 Enabled Memory parity/ECC = 0x0 Disabled PCI master abort = 0x0 Disabled 60x Bus Error enable = 0x0 Disabled >> Regc4 Error Enabling and detection 2 = 0x12345678 0xc7:PCI Bus Error Status = 0x12 unnamed bits 31 - 29 (7 - 5) = 0x0 MPC107 master/target status = 0x1 PCI target Copy of C/BE* on PCI bus error = 0x2 0xc6:unnamed bits 23 - 17 = 0x34 ERROR => should be zero 0xc5:Error Detection 2 = 0x56 Invalid error address Register val = 0x0 valid Unnamed bit 6 = 0x1 ERROR => should be zero L2 Copy Back Error = 0x0 No error detected L2 Parity Error = 0x1 error detected ECC mutli-bit error = 0x0 No error detected Unnamed bit 2 = 0x1 ERROR => should be zero Unnamed bit 1 = 0x1 ERROR => should be zero Flash ROM write Error = 0x0 No error detected 0xc4:Error Enabling 2 = 0x78 PCI address parity = 0x0 Disabled Unnamed bit 6 = 0x1 ERROR => should be zero Illegal L2 copy back er = 0x1 Enabled L2 parity error = 0x1 Enabled ECC multi-bit error = 0x1 Enabled Unnamed bit 2 = 0x0 Unnamed bit 1 = 0x0 Flash ROM Write Enable = 0x0 Disabled >> Regc8 60x/PCI Error Address Reg = 0x12345678 0xcb:A[24:32] or AD[7:0] = 0x12 0xca:A[16:23] or AD[15:8] = 0x34 0xc9:A[8:15] or AD[23:16] = 0x56 0xc8:A[0:7] or AD[31:24] = 0x78 >> Rege0 Emulation Support Config 1 = 0xffffffff unnamed bits 31 - 28 = 0xF ERROR => should be zero INT_VECTOR_RELOCATE = 0xFFF TOP_OF_MEM upper boundry = 0xFF unnamed bit 7 = 0x1 ERROR => should be zero PCI FD Alias En = 0x1 respond PIRQ_EN PIRQ* emulation = 0x1 Enabled PIRQ_ACTIVE_HIGH PIRQ*polarity= 0x1 Active high PCI Compatibility Hole = 0x1 don't respond Proc Compatibility Hole = 0x1 forward to PCI memory EMULATION_MODE_HW address map = 0x1 EMULATION_MODE_EN address map = 0x1 Enabled >> Rege0 Emulation Support Config 1 = 0x12345678 unnamed bits 31 - 28 = 0x1 ERROR => should be zero INT_VECTOR_RELOCATE = 0x234 TOP_OF_MEM upper boundry = 0x56 unnamed bit 7 = 0x0 PCI FD Alias En = 0x1 respond PIRQ_EN PIRQ* emulation = 0x1 Enabled PIRQ_ACTIVE_HIGH PIRQ*polarity= 0x1 Active high PCI Compatibility Hole = 0x1 don't respond Proc Compatibility Hole = 0x0 forward to system memory EMULATION_MODE_HW address map = 0x0 ERROR => should be one EMULATION_MODE_EN address map = 0x0 Disabled >> Rege4 Modified memory Status (no clear)= 0xffffffff HWM value = 0xEFFF LWM value = 0x7FFF MOD_MEM_STATUS HWM, LWM status = 0x3 Valid define block address >> Regec Modified memory Status (clear) = 0x12345678 HWM value = 0x091A LWM value = 0x159E MOD_MEM_STATUS HWM, LWM status = 0x0 Invalid >> Rege4 Modified memory Status (no clear)= 0x00000001 HWM value = 0x0000 LWM value = 0x0000 MOD_MEM_STATUS HWM, LWM status = 0x1 Valid same address >> Regec Modified memory Status (clear) = 0x00000002 HWM value = 0x0000 LWM value = 0x0000 MOD_MEM_STATUS HWM, LWM status = 0x2 Valid different addresses >> Regec Modified memory Status (clear) = 0x00000000 HWM value = 0x0000 LWM value = 0x0000 MOD_MEM_STATUS HWM, LWM status = 0x0 Invalid >> Rege8 ESCR2 Emulation Support Config 2 = 0xffffffff Unnamed bits 31 - 8 = 0xFFFFFF ERROR => should be zero MOD_MEM_SIZE Modified mem reg = 0xFF Invalid value >> Rege8 ESCR2 Emulation Support Config 2 = 0x00000001 Unnamed bits 31 - 8 = 0x000000 MOD_MEM_SIZE Modified mem reg = 0x1 128 bytes (Not supported) >> Rege8 ESCR2 Emulation Support Config 2 = 0x00000002 Unnamed bits 31 - 8 = 0x000000 MOD_MEM_SIZE Modified mem reg = 0x2 256 bytes (Not supported) >> Rege8 ESCR2 Emulation Support Config 2 = 0x00000003 Unnamed bits 31 - 8 = 0x000000 MOD_MEM_SIZE Modified mem reg = 0x3 Invalid value >> Rege8 ESCR2 Emulation Support Config 2 = 0x00000004 Unnamed bits 31 - 8 = 0x000000 MOD_MEM_SIZE Modified mem reg = 0x4 512 bytes (Not supported) >> Rege8 ESCR2 Emulation Support Config 2 = 0x00000008 Unnamed bits 31 - 8 = 0x000000 MOD_MEM_SIZE Modified mem reg = 0x8 1 Kbytes (Not supported) >> Rege8 ESCR2 Emulation Support Config 2 = 0x00000010 Unnamed bits 31 - 8 = 0x000000 MOD_MEM_SIZE Modified mem reg = 0x10 2 Kbytes (Not supported) >> Rege8 ESCR2 Emulation Support Config 2 = 0x00000020 Unnamed bits 31 - 8 = 0x000000 MOD_MEM_SIZE Modified mem reg = 0x20 4 Kbytes >> Rege8 ESCR2 Emulation Support Config 2 = 0x00000040 Unnamed bits 31 - 8 = 0x000000 MOD_MEM_SIZE Modified mem reg = 0x40 8 Kbytes >> Rege8 ESCR2 Emulation Support Config 2 = 0x00000080 Unnamed bits 31 - 8 = 0x000000 MOD_MEM_SIZE Modified mem reg = 0x80 16 Kbytes (Not supported) >> Rege8 ESCR2 Emulation Support Config 2 = 0x00000123 Unnamed bits 31 - 8 = 0x000001 ERROR => should be zero MOD_MEM_SIZE Modified mem reg = 0x23 Invalid value >> Regf0 MCCR1 Memory Control Config Reg = 0xffffffff ROMNAL next access time = 0xF ROMFAL access time = 0x1F 501 _MODE = 0x1 backward compatibility 8N64 ROM bank0 data path width= 0x1 8 bit BURST Burst mode ROM timing = 0x1 burst-mode MEMGO RAM interface logic = 0x1 Enabled SREN Self refresh = 0x1 Enabled RAM_TYPE = 0x1 DRAM or EDO RAM PCKEN Memory interface parity checking = 0x1 Enabled Bank 7 Row = 0x3 12,13 or (11 x n x 2) Bank 6 Row = 0x3 12,13 or (11 x n x 2) Bank 5 Row = 0x3 12,13 or (11 x n x 2) Bank 4 Row = 0x3 12,13 or (11 x n x 2) Bank 3 Row = 0x3 12,13 or (11 x n x 2) Bank 2 Row = 0x3 12,13 or (11 x n x 2) Bank 1 Row = 0x3 12,13 or (11 x n x 2) Bank 0 Row = 0x3 12,13 or (11 x n x 2) >> Regf0 MCCR1 Memory Control Config Reg = 0x12345678 ROMNAL next access time = 0x1 ROMFAL access time = 0x04 501 _MODE = 0x0 16501 type buffers 8N64 ROM bank0 data path width= 0x1 8 bit BURST Burst mode ROM timing = 0x1 burst-mode MEMGO RAM interface logic = 0x0 Disabled SREN Self refresh = 0x1 Enabled RAM_TYPE = 0x0 SDRAM PCKEN Memory interface parity checking = 0x0 Disabled Bank 7 Row = 0x1 10 or (13 x n x 2) Bank 6 Row = 0x1 10 or (13 x n x 2) Bank 5 Row = 0x1 10 or (13 x n x 2) Bank 4 Row = 0x2 11 or (13 x n x 4) Bank 3 Row = 0x1 10 or (13 x n x 2) Bank 2 Row = 0x3 12,13 or (11 x n x 2) Bank 1 Row = 0x2 11 or (13 x n x 4) Bank 0 Row = 0x0 9 or (12 x n x 4) >> Regf0 MCCR1 Memory Control Config Reg = 0x00000000 ROMNAL next access time = 0x0 ROMFAL access time = 0x00 501 _MODE = 0x0 16501 type buffers 8N64 ROM bank0 data path width= 0x0 64 bit BURST Burst mode ROM timing = 0x0 standard (non burst-mode) MEMGO RAM interface logic = 0x0 Disabled SREN Self refresh = 0x0 Disabled RAM_TYPE = 0x0 SDRAM PCKEN Memory interface parity checking = 0x0 Disabled Bank 7 Row = 0x0 9 or (12 x n x 4) Bank 6 Row = 0x0 9 or (12 x n x 4) Bank 5 Row = 0x0 9 or (12 x n x 4) Bank 4 Row = 0x0 9 or (12 x n x 4) Bank 3 Row = 0x0 9 or (12 x n x 4) Bank 2 Row = 0x0 9 or (12 x n x 4) Bank 1 Row = 0x0 9 or (12 x n x 4) Bank 0 Row = 0x0 9 or (12 x n x 4) >> Regf4 MCCR2 Memory Control Config Reg = 0xffffffff EXT_ECM_ECC_EN external parity= 0x1 Enabled EXT_ECM_PAR_EN external parity= 0x1 Enabled BSTOPRE[0-1] = 0x3 unnamed bits 28 - 22 = 0x7F ERROR => should be zero TS_WAIT_TIMER = 0x7 8 clocks 120ns @ 66MHz 96ns @83MHz ECC enable = 0x1 Enabled EDO Enable = 0x1 EDO DRAM Refresh Interval = 0x1FFF = 8191 decimal BUF_MODE BCTL0 & BCTL1 mode = 0x1 BCTL0 direction, BCTL1 buf enable Read Modify Write parity = 0x1 Enabled >> Regf4 MCCR2 Memory Control Config Reg = 0x12345678 EXT_ECM_ECC_EN external parity= 0x1 Enabled EXT_ECM_PAR_EN external parity= 0x0 Disabled BSTOPRE[0-1] = 0x3 unnamed bits 28 - 22 = 0x48 ERROR => should be zero TS_WAIT_TIMER = 0x0 2 clocks 30ns @ 66MHz 24ns @83MHz ECC enable = 0x0 Disabled EDO Enable = 0x0 standard DRAM Refresh Interval = 0x0ACF = 2767 decimal BUF_MODE BCTL0 & BCTL1 mode = 0x0 BCTL0 write, BCTL1 read enable Read Modify Write parity = 0x0 Disabled >> Regf4 MCCR2 Memory Control Config Reg = 0x00000000 EXT_ECM_ECC_EN external parity= 0x0 Disabled EXT_ECM_PAR_EN external parity= 0x0 Disabled BSTOPRE[0-1] = 0x0 unnamed bits 28 - 22 = 0x0 TS_WAIT_TIMER = 0x0 2 clocks 30ns @ 66MHz 24ns @83MHz ECC enable = 0x0 Disabled EDO Enable = 0x0 standard DRAM Refresh Interval = 0x0000 = 0 decimal BUF_MODE BCTL0 & BCTL1 mode = 0x0 BCTL0 write, BCTL1 read enable Read Modify Write parity = 0x0 Disabled >> Regf8 MCCR3 Memory Control Config Reg 3 = 0xffffffff Burst to precharge BSTOPRE[2-5] = 0xF Refresh to activate interval = 0xF 15 clocks Data Latency from read command = 0xF Reserved Do not use CAS write timing modifier DRAM = 0x1 Modified RAS assertion interval for CBR DRAM = 0xF 15 clocks CAS assertion interval CAS5 DRAM = 0x7 7 clocks CAS precharge interval CP4 DRAM = 0x7 7 clocks CAS assertion interval CAS3 DRAM = 0x7 7 clocks RAS CAS delay interval RCD2 DRAM = 0x7 7 clocks RAS precharge interval RP1 DRAM = 0x7 7 clocks >> Regf8 MCCR3 Memory Control Config Reg 3 = 0x00000000 Burst to precharge BSTOPRE[2-5] = 0x0 Refresh to activate interval = 0x0 16 clocks Data Latency from read command = 0x0 Reserved Do not use CAS write timing modifier DRAM = 0x0 Unmodified RAS assertion interval for CBR DRAM = 0x0 16 clocks CAS assertion interval CAS5 DRAM = 0x0 8 clocks CAS precharge interval CP4 DRAM = 0x0 8 clocks CAS assertion interval CAS3 DRAM = 0x0 8 clocks RAS CAS delay interval RCD2 DRAM = 0x0 8 clocks RAS precharge interval RP1 DRAM = 0x0 8 clocks >> Regf8 MCCR3 Memory Control Config Reg 3 = 0x12345678 Burst to precharge BSTOPRE[2-5] = 0x1 Refresh to activate interval = 0x2 2 clocks Data Latency from read command = 0x3 3 clocks CAS write timing modifier DRAM = 0x0 Unmodified RAS assertion interval for CBR DRAM = 0x8 8 clocks CAS assertion interval CAS5 DRAM = 0x5 5 clocks CAS precharge interval CP4 DRAM = 0x3 3 clocks CAS assertion interval CAS3 DRAM = 0x1 1 clocks RAS CAS delay interval RCD2 DRAM = 0x7 7 clocks RAS precharge interval RP1 DRAM = 0x0 8 clocks >> Regfc MCCR4 Memory Control Config Reg 4 = 0x00000000 Prechrg to act int PRETOACT = 0x0 16 clocks Act to precharge int ACTOPRE = 0x0 16 clocks EXT_ECM_EN external error mod = 0x0 Disabled WCBUF memory read buffer type = 0x0 Flow-through or transparent RCBUF memory write buffer type= 0x0 Flow-through OPCODE = 0x0 CAS Latency = 0x0 Reserved do not use Wrap Type = 0x0 Sequential Wrap Length = 0x0 Reserved do not use SDRAM mode Register SDMODE = 0x00 Activate to R/W int ACTORW = 0x0 16 clocks Burst to Prechrg BSTOPRE[6-9] = 0x0 >> Regfc MCCR4 Memory Control Config Reg 4 = 0xffffffff Prechrg to act int PRETOACT = 0xF 15 clocks Act to precharge int ACTOPRE = 0xF 15 clocks EXT_ECM_EN external error mod = 0x3 Enabled WCBUF memory read buffer type = 0x1 Registered RCBUF memory write buffer type= 0x1 Transparent or registered OPCODE = 0x1F CAS Latency = 0x7 Reserved do not use Wrap Type = 0x1 Interleaved Wrap Length = 0x7 Reserved do not use SDRAM mode Register SDMODE = 0xFFF Activate to R/W int ACTORW = 0xF 15 clocks Burst to Prechrg BSTOPRE[6-9] = 0xF >> Regfc MCCR4 Memory Control Config Reg 4 = 0x12345678 Prechrg to act int PRETOACT = 0x1 1 clocks Act to precharge int ACTOPRE = 0x2 2 clocks EXT_ECM_EN external error mod = 0x0 Disabled WCBUF memory read buffer type = 0x1 Registered RCBUF memory write buffer type= 0x1 Transparent or registered OPCODE = 0x8 CAS Latency = 0x5 Reserved do not use Wrap Type = 0x0 Sequential Wrap Length = 0x6 Reserved do not use SDRAM mode Register SDMODE = 0x456 Activate to R/W int ACTORW = 0x7 7 clocks Burst to Prechrg BSTOPRE[6-9] = 0x8 >> Regf0 MCCR1 Memory Control Config Reg = 0x53ec0000 ROMNAL next access time = 0x5 ROMFAL access time = 0x07 501 _MODE = 0x1 backward compatibility 8N64 ROM bank0 data path width= 0x1 8 bit BURST Burst mode ROM timing = 0x0 standard (non burst-mode) MEMGO RAM interface logic = 0x1 Enabled SREN Self refresh = 0x1 Enabled RAM_TYPE = 0x0 SDRAM PCKEN Memory interface parity checking = 0x0 Disabled Bank 7 Row = 0x0 9 or (12 x n x 4) Bank 6 Row = 0x0 9 or (12 x n x 4) Bank 5 Row = 0x0 9 or (12 x n x 4) Bank 4 Row = 0x0 9 or (12 x n x 4) Bank 3 Row = 0x0 9 or (12 x n x 4) Bank 2 Row = 0x0 9 or (12 x n x 4) Bank 1 Row = 0x0 9 or (12 x n x 4) Bank 0 Row = 0x0 9 or (12 x n x 4) >> Regf4 MCCR2 Memory Control Config Reg = 0x30000caa EXT_ECM_ECC_EN external parity= 0x0 Disabled EXT_ECM_PAR_EN external parity= 0x0 Disabled BSTOPRE[0-1] = 0x0 unnamed bits 28 - 22 = 0x40 ERROR => should be zero TS_WAIT_TIMER = 0x1 2 clocks 30ns @ 66MHz 24ns @83MHz ECC enable = 0x0 Disabled EDO Enable = 0x0 standard DRAM Refresh Interval = 0x0195 = 405 decimal BUF_MODE BCTL0 & BCTL1 mode = 0x1 BCTL0 direction, BCTL1 buf enable Read Modify Write parity = 0x0 Disabled >> Regf8 MCCR3 Memory Control Config Reg 3 = 0x03100000 Burst to precharge BSTOPRE[2-5] = 0x0 Refresh to activate interval = 0x3 3 clocks Data Latency from read command = 0x1 1 clocks CAS write timing modifier DRAM = 0x0 Unmodified RAS assertion interval for CBR DRAM = 0x0 16 clocks CAS assertion interval CAS5 DRAM = 0x0 8 clocks CAS precharge interval CP4 DRAM = 0x0 8 clocks CAS assertion interval CAS3 DRAM = 0x0 8 clocks RAS CAS delay interval RCD2 DRAM = 0x0 8 clocks RAS precharge interval RP1 DRAM = 0x0 8 clocks >> Regfc MCCR4 Memory Control Config Reg 4 = 0x22002220 Prechrg to act int PRETOACT = 0x2 2 clocks Act to precharge int ACTOPRE = 0x2 2 clocks EXT_ECM_EN external error mod = 0x0 Disabled WCBUF memory read buffer type = 0x0 Flow-through or transparent RCBUF memory write buffer type= 0x0 Flow-through OPCODE = 0x0 CAS Latency = 0x2 2 Wrap Type = 0x0 Sequential Wrap Length = 0x2 4 SDRAM mode Register SDMODE = 0x22 Activate to R/W int ACTORW = 0x2 2 clocks Burst to Prechrg BSTOPRE[6-9] = 0x0 >> Rega0 Memory Page and Bank Information = 0x3a000001 0xa3:Memory Page Mode Register = 0x3A = 3712 clocks 0xa1:unnamed bits 23 - 8 = 0x00 0xa0:Memory Bank Enable Register = 0x01 Bank7 = 0x0 Disabled Bank6 = 0x0 Disabled Bank5 = 0x0 Disabled Bank4 = 0x0 Disabled Bank3 = 0x0 Disabled Bank2 = 0x0 Disabled Bank1 = 0x0 Disabled Bank0 = 0x1 Enabled >> End of File, Program complete