Configuration Register Decoder Version 0.8 July 10, 2000 Enter a description of this data, 60 characters or less >>Data set: MPC106 registers from Maurie Big Endian Mode Please chose one of the following by number 1,2,3, or 4: 1. MPC106 Rev 4.0 2. MPC107 3. MPC8240 Host 4. MPC8240 Agent >>Choose printing order: 1. Big endian order 2. Little endian order You chose Big endian order for printing MPC106 Decoder Enter all values in hex, DO NOT preceed them with 0x Only use word boundry addresses, e.g. 0,4,8,etc Values are in little endian orientation and will be padded with zeros on the left Enter address : value Example: 04 : a00106 Enter "^D" i.e. EOF to exit >> Reg00 Device ID and Vendor ID = 0x00021057 0x00:Vendor ID = 0x1057 0x02:Device ID = 0x0002 >> Reg04 PCI Status/Command = 0xFFFFFFFF 0x04:PCI Command = 0xffff I/O Space = 0x1 ERROR => should be zero Memory Space = 0x1 Respond to PCI memory accesses Bus Master = 0x1 Enabled Special Cycles = 0x1 ERROR => should be zero Memory Write and Invalidate = 0x1 Use Memory Write and Invalidate unnamed bit 5 = 0x1 ERROR => should be zero Parity Error Response = 0x1 Parity errors take action unnamed bit 7 = 0x1 ERROR => should be zero SERR = 0x1 SERR driver enabled Fast Back to back = 0x1 ERROR => should be zero unnamed bits 13-10 = 0xf ERROR => should be zero Read_Lock = 0x1 MPC106 V4.0 mode unnamed bit 15 = 0x1 ERROR => should be zero 0x06:PCI Status = 0Xffff unnamed bits 0-4 = 0x1f ERROR => should be zero 66-MHz capable = 0x1 66-MHz capable unnamed bit 6 = 0x1 ERROR => should be zero Fast Back To Back = 0x1 Data Parity Detected = 0x1 Data Partity detected DEVSEL Use fast device Timing = 0x6 ERROR => should be zero Signaled Target-abort = 0x1 Target issued abort to PCi master Received Target-abort = 0x1 Target terminated PCI abort Received Master-abort = 0x1 PCI master issued PCI abort Signaled System abort = 0x1 SEER is asserted Detected Parity Error = 0x1 Parity Error is detected >> Reg04 PCI Status/Command = 0x00000000 0x04:PCI Command = 0x0000 I/O Space = 0x0 Memory Space = 0x0 Do not respond to PCI memory accesses Bus Master = 0x0 Disabled Special Cycles = 0x0 Memory Write and Invalidate = 0x0 Use Memory Write unnamed bit 5 = 0x0 Parity Error Response = 0x0 Parity errors are ignored unnamed bit 7 = 0x0 SERR = 0x0 SERR driver disabled Fast Back to back = 0x0 unnamed bits 13-10 = 0x0 Read_Lock = 0x0 MPC106 V3.0 mode unnamed bit 15 = 0x0 0x06:PCI Status = 0X0000 unnamed bits 0-4 = 0x0 66-MHz capable = 0x0 Not 66-MHz capable unnamed bit 6 = 0x0 Fast Back To Back = 0x0 ERROR => should be one Data Parity Detected = 0x0 No Data Partity detected DEVSEL Use fast device Timing = 0x0 Signaled Target-abort = 0x0 No PCI target abort issued Received Target-abort = 0x0 No PCI target abort received Received Master-abort = 0x0 No PCI master abort Signaled System abort = 0x0 SEER not asserted Detected Parity Error = 0x0 Parity Error not detected >> Reg08 Class Code, Subclass Code, Standard Programming, Revision ID = 0x12345678 0x08:Revision ID = 0x78 0x09:Standard Programing Interface = 0x56 0x0a:Subclass Code = 0x34 0x0b:Base Class Code = 0x12 >> Reg48 CMDR Perfrm Mon Cmd Reg = 0x00000000 EVENT_U upper = 0x0 CMD_TYPE which table = 0x0 Use Table 12 COUNTER which counter = 0x0 PMC0 Unnamed bits 12-8 = 0x0 EVENT_L lower = 0x0 THRESHOLD_U upper = 0x0 THRESHOLD_L lower = 0x0 >> Reg48 CMDR Perfrm Mon Cmd Reg = 0xffffffff EVENT_U upper = 0x1f CMD_TYPE which table = 0x1 Use Table 13 COUNTER which counter = 0x3 PMC3 Unnamed bits 12-8 = 0x1f ERROR => should be zero EVENT_L lower = 0x7 THRESHOLD_U upper = 0xff THRESHOLD_L lower = 0xff >> Reg4c MMCR Perfrm Mon Mode Reg= 0x00000000 PMCTRG PMC0 msb from 0 to 1 = 0x0 enable counters ignore msb Unnamed bits 5-1 = 0x0 DISCOUNT PMCx msb from 0 to 1 = 0x0 counters continue to increment ENABLE counters = 0x0 Disabled Unnamed bits 13-8 = 0x0 OVERFLOW 2-3 PMC2 into PMC3 = 0x0 Disabled OVERFLOW 0-1 PMC0 into PMC1 = 0x0 Disabled >> Reg4c MMCR Perfrm Mon Mode Reg= 0xffffffff PMCTRG PMC0 msb from 0 to 1 = 0x1 disable counters until msb Unnamed bits 5-1 = 0x1f ERROR => should be zero DISCOUNT PMCx msb from 0 to 1 = 0x1 PMC0 stops ENABLE counters = 0x1 Enabled Unnamed bits 13-8 = 0x1f ERROR => should be zero OVERFLOW 2-3 PMC2 into PMC3 = 0x1 Enabled OVERFLOW 0-1 PMC0 into PMC1 = 0x1 Enabled >> Reg50 PMC0 Perfrm Mon Counter = 0x00000021 >> Reg54 PMC1 Perfrm Mon Counter = 0x00000030 >> Reg58 PMC2 Perfrm Mon Counter = 0x12345678 >> Reg5c PMC3 Perfrm Mon Counter = 0x00abcdef >> Reg70 Power Management & Output Driver = 0xffffffff 0x70:Power Management Register 1 = 0xFFFF BR1_WAKE awareness of other CPUs = 0x1 Ignored during nap and sleep Selects Clock Source = 0x30 Sleep Mode = 0x1 Enables Sleep mode Nap Mode = 0x1 Disables Nap mode Doze Mode = 0x1 Enables Doze mode unnammed bit 6 = 0x1 ERROR => should be zero Power Management Enable = 0x1 Enabled unnammed bits 9 - 8 = 0x1 ERROR => should be zero Suspend Mode QACK* = 0x1 QACK* is asserted in suspend mode 601_NEED_QREQ use the QREQ nap = 0x1 Required NO_604_RUN assert QUAK on wake = 0x1 Yes Low Power Refresh = 0x1 Perform mem refresh in SLEEP Sleep Message Type = 0x1 Broadcast SHUTDOWN No Sleep Message Broadcast = 0x1 Does not broadcast SLEEP No Nap Msg Halt command Broadcast = 0x1 Does not broadcast HALT 0x72:Power Management Register 2 = 0xFF unnammed bit 7 - 1 = 0x7F ERROR => should be zero Shared MPC = 0x1 High Impedence except on error 0x73:Output Driver Config Reg = 0xFF MEM_CTRL1 mem signal driver = 0x1 PROC_CTRL2 proc/L2 signal 2 = 0x1 20 ohm control PROC_CTRL1 proc/L2 signal 1 = 0x1 20 ohm control PROC_A address bus signal driver = 0x1 20 ohm control MEM_CTRL2 mem signal driver = 0x1 Combined MEM_CTRL2 & MEM_CTRL1 = 0x3 8 ohm control PROC_A address bus singal driver = 0x1 20 ohm control PCI_CTRL control signal driver = 0x1 20 ohm control PCI_AD address/data signal driver = 0x1 20 ohm control >> Reg70 Power Management & Output Driver = 0x00000000 0x70:Power Management Register 1 = 0x0000 BR1_WAKE awareness of other CPUs = 0x0 Ignored during nap and sleep Selects Clock Source = 0x0 Disable the test clock driver Sleep Mode = 0x0 Disables Sleep mode Nap Mode = 0x0 Disables Nap mode Doze Mode = 0x0 Disables Doze mode unnammed bit 6 = 0x0 Power Management Enable = 0x0 Disabled unnammed bits 9 - 8 = 0x0 Suspend Mode QACK* = 0x0 QACK* not asserted in suspend mode 601_NEED_QREQ use the QREQ nap = 0x0 Not Required NO_604_RUN assert QUAK on wake = 0x0 No Low Power Refresh = 0x0 Don't perform mem refresh in SLEEP Sleep Message Type = 0x0 Broadcast HALT No Sleep Message Broadcast = 0x0 Broadcast SLEEP No Nap Msg Halt command Broadcast = 0x0 Broadcast HALT 0x72:Power Management Register 2 = 0x00 unnammed bit 7 - 1 = 0x0 Shared MPC = 0x0 Always drive MPC* 0x73:Output Driver Config Reg = 0x00 MEM_CTRL1 mem signal driver = 0x0 PROC_CTRL2 proc/L2 signal 2 = 0x0 40 ohm control PROC_CTRL1 proc/L2 signal 1 = 0x0 40 ohm control PROC_A address bus signal driver = 0x0 40 ohm control MEM_CTRL2 mem signal driver = 0x0 Combined MEM_CTRL2 & MEM_CTRL1 = 0x0 Reserved do not use PROC_A address bus singal driver = 0x0 40 ohm control PCI_CTRL control signal driver = 0x0 40 ohm control PCI_AD address/data signal driver = 0x0 40 ohm control >> Reg70 Power Management & Output Driver = 0x12345678 0x70:Power Management Register 1 = 0x5678 BR1_WAKE awareness of other CPUs = 0x0 Ignored during nap and sleep Selects Clock Source = 0x30 Sleep Mode = 0x1 Enables Sleep mode Nap Mode = 0x1 Disables Nap mode Doze Mode = 0x1 Enables Doze mode unnammed bit 6 = 0x1 ERROR => should be zero Power Management Enable = 0x0 Disabled unnammed bits 9 - 8 = 0x0 Suspend Mode QACK* = 0x1 QACK* is asserted in suspend mode 601_NEED_QREQ use the QREQ nap = 0x1 Required NO_604_RUN assert QUAK on wake = 0x0 No Low Power Refresh = 0x1 Perform mem refresh in SLEEP Sleep Message Type = 0x0 Broadcast HALT No Sleep Message Broadcast = 0x1 Does not broadcast SLEEP No Nap Msg Halt command Broadcast = 0x0 Broadcast HALT 0x72:Power Management Register 2 = 0x34 unnammed bit 7 - 1 = 0x1A ERROR => should be zero Shared MPC = 0x0 Always drive MPC* 0x73:Output Driver Config Reg = 0x12 MEM_CTRL1 mem signal driver = 0x0 PROC_CTRL2 proc/L2 signal 2 = 0x1 20 ohm control PROC_CTRL1 proc/L2 signal 1 = 0x0 40 ohm control PROC_A address bus signal driver = 0x0 40 ohm control MEM_CTRL2 mem signal driver = 0x1 Combined MEM_CTRL2 & MEM_CTRL1 = 0x2 13 ohm control PROC_A address bus singal driver = 0x0 40 ohm control PCI_CTRL control signal driver = 0x0 40 ohm control PCI_AD address/data signal driver = 0x0 40 ohm control >> Rega8 PICR1 Processor Interface Config 1= 0x12345678 CF_MP Multiprocessor configuration = 0x0 Uniprocessor Speculative PCI Reads = 0x0 Disabled CF_APARK Processor Parked on 60x = 0x1 Last processor CF_LOOP_SNOOP Repeat Snoops = 0x1 Enabled LE_MODE Little Endian MODE = 0x1 Big-Endian Mode ST_GATH_EN Store gathering = 0x1 Enabled NO_PORT_REGS Map A ext config regs = 0x0 Implemented CF_EXTERNAL_L2 enable = 0x0 Disabled CF_DPARK data bus park = 0x1 Enabled TEA_EN TEA enable = 0x1 Enabled MPC_EN Machine Check enable = 0x0 Disabled FLASH_WR_EN Flash Write enable = 0x1 Enabled CF_LBA_EN Local Bus Slave enable = 0x0 Disabled CF_MP_ID Multiprocessor ID = 0x1 Reserved do not use ADDRESS_MAP = 0x0 Map B PROC_TYPE Processor Type = 0x2 603x, 7xx, and 74xx XIO_MODE Map A mode = 0x0 Contiguous RCS0 ROM Location = 0x1 Processor/memory data Bus CF_CACHE_1G L2 cache addresses = 0x1 0 to 1 Gbyte addresses CF_BREAD_WS Burst Read Wait States = 0x0 0 wait state (2:1 clock) CF_CBA_MASK L2 copy back addr mask = 0x12 >> Regac PICR2 Processor Interface Config 2= 0x12345678 CF_WDATA = 0x0 CF_DOE L2 first data read timing = 0x0 1 or 2 clock cycle CF_APHASE_WS address phase wait sts= 0x0 0 wait states L2 cache size = 0x3 Reserved do not use CF_TOE_WIDTH TOE active pulse width= 0x00 2 clock cycles CF_FAST_CACTOUT timing = 0x0 Normal CF_TWO_BANKS L2 cache banks = 0x00 1 SRAM Bank CF_L2_HIT_DELAY = 0x3 3 clock cycles CF_RWITM_FILL line fill disable = 0x0 Enabled CF_INV_MODE L2 Invalidate Mode = 0x1 Enabled CF_HOLD L2 tag address hold = 0x0 Synchronous tag RAM CF_ADDR_ONLY_DISABLE clean,flush,kill = 0x1 Ignore unnamed bit 15 = 0x0 CF_HIT_HIGH L2 HIT* signal = 0x0 Active low CF_MOD_HIGH Cache modified sig = 0x0 Active low CF_SNOOP_WS Snoop wait states = 0x1 1 wait state CF_WMODE SRAM write timing = 0x3 Early with partial update CF_DATA_RAM_TYPE L2 RAM type = 0x0 Synchronous burst SRAM CF_FAST_L2_MODE fast mode disable = 0x0 Disabled FLASH_WR_LOCKOUT write lockout = 0x1 Disabled CF_FF0_LOCAL remapping enable = 0x0 Disabled NO_SNOOP_EN snoop transactions = 0x0 Enabled NO_SERIAL_CFG serialize wr to PCI = 0x0 Yes L2_EN L2 cache enable = 0x0 Disabled L2_UPDATE_EN L2 update enable = 0x0 Enabled >> Regac PICR2 Processor Interface Config 2= 0xffffffff CF_WDATA = 0x1 CF_DOE L2 first data read timing = 0x1 2 or 3 clock cycle CF_APHASE_WS address phase wait sts= 0x3 3 wait states L2 cache size = 0x3 Reserved do not use CF_TOE_WIDTH TOE active pulse width= 0x01 3 clock cycles CF_FAST_CACTOUT timing = 0x1 Fast CF_TWO_BANKS L2 cache banks = 0x01 2 SRAM Bank CF_L2_HIT_DELAY = 0x3 3 clock cycles CF_RWITM_FILL line fill disable = 0x1 Disabled CF_INV_MODE L2 Invalidate Mode = 0x1 Enabled CF_HOLD L2 tag address hold = 0x1 Asynchronous tag RAM CF_ADDR_ONLY_DISABLE clean,flush,kill = 0x1 Ignore unnamed bit 15 = 0x1 ERROR => should be zero CF_HIT_HIGH L2 HIT* signal = 0x1 Active high CF_MOD_HIGH Cache modified sig = 0x1 Active high CF_SNOOP_WS Snoop wait states = 0x3 3 wait states CF_WMODE SRAM write timing = 0x3 Early with partial update CF_DATA_RAM_TYPE L2 RAM type = 0x3 Reserved do not use CF_FAST_L2_MODE fast mode disable = 0x1 Enabled FLASH_WR_LOCKOUT write lockout = 0x1 Disabled CF_FF0_LOCAL remapping enable = 0x1 Enabled NO_SNOOP_EN snoop transactions = 0x1 Disabled NO_SERIAL_CFG serialize wr to PCI = 0x1 No L2_EN L2 cache enable = 0x1 Enabled L2_UPDATE_EN L2 update enable = 0x1 Disabled >> Regb8 ECC Single Bit Error = 0x12345678 0xb8:ECC single bit counter = 0x78 0xB9:ECC single bit Trigger = 0x56 single bit error threshold 0xba:Alternate OS-Visible Reg1= 0x34 MCP_EN Machine check enable = 0x0 Disabled TEA_EN Transfer Error Ack = 0x0 Disabled XIO_MODE Map A mode = 0x1 Contiguous unnamed bits 4 - 3 = 0x2 ERROR => should be zero RX_SERR_EN SEER* assertion = 0x0 Ignore unnamed bits 7 - 6 = 0x0 0xbb:Alternate OS-Visible Reg2= 0x12 FLASH_WR_EN flash write = 0x0 Disabled unnamed bits 7 - 1 = 0x9 ERROR => should be zero >> Regc0 Error Enabling and detection 1 = 0x12345678 0xc0:Error Enabling 1 = 0x78 60x Bus Error enable = 0x0 Disabled PCI master abort = 0x0 Disabled Memory parity/ECC = 0x0 Disabled PCI master PERR* = 0x1 Enabled Memory refresh overflow = 0x1 Enabled Memory select = 0x1 Enabled PCI target PERR* = 0x1 Enabled PCI received error = 0x0 Disabled 0xc1:Error Detection 1 = 0x56 Unsupported 60x Transaction = 0x02 XATS* detected Memory Read Parity ECC trigger = 0x1 Parity or ECC trigger 60x/PCI cycle error occurred = 0x0 on processor-init cycle Memory refresh overflow error = 0x1 error detected Memory Select Error = 0x0 No error detected PCI target PERR* parity error = 0x1 error detected PCI SERR* two clks after address = 0x0 No error detected 0xc2:unnamed bits 23 - 17 = 0x34 ERROR => should be zero 0xc3:60x Bus Error Status = 0x12 Copy TSIZ on processor bus error = 0x2 Copy of TT on processor bus error = 0x02 >> Regc4 Error Enabling and detection 2 = 0x12345678 0xc4:Error Enabling 2 = 0x78 Flash ROM Write Enable = 0x0 Disabled Unnamed bit 1 = 0x0 Unnamed bit 2 = 0x0 ECC multi-bit error = 0x1 Enabled L2 parity error = 0x1 Enabled Illegal L2 copy back er = 0x1 Enabled Unnamed bit 6 = 0x1 ERROR => should be zero PCI address parity = 0x0 Disabled 0xc5:Error Detection 2 = 0x56 Flash ROM write Error = 0x0 No error detected Unnamed bit 1 = 0x1 ERROR => should be zero Unnamed bit 2 = 0x1 ERROR => should be zero ECC mutli-bit error = 0x0 No error detected L2 Parity Error = 0x1 error detected L2 Copy Back Error = 0x0 No error detected Unnamed bit 6 = 0x1 ERROR => should be zero Invalid error address Register val = 0x0 valid 0xc6:unnamed bits 23 - 17 = 0x34 ERROR => should be zero 0xc7:PCI Bus Error Status = 0x12 Copy of C/BE* on PCI bus error = 0x2 MPC107 master/target status = 0x1 PCI target unnamed bits 31 - 29 (7 - 5) = 0x0 >> Regc8 60x/PCI Error Address Reg = 0x12345678 0xc8:A[0:7] or AD[31:24] = 0x78 0xc9:A[8:15] or AD[23:16] = 0x56 0xca:A[16:23] or AD[15:8] = 0x34 0xcb:A[24:32] or AD[7:0] = 0x12 >> Rege0 Emulation Support Config 1 = 0xffffffff EMULATION_MODE_EN address map = 0x1 Enabled EMULATION_MODE_HW address map = 0x1 Proc Compatibility Hole = 0x1 forward to PCI memory PCI Compatibility Hole = 0x1 don't respond PIRQ_ACTIVE_HIGH PIRQ*polarity= 0x1 Active high PIRQ_EN PIRQ* emulation = 0x1 Enabled PCI FD Alias En = 0x1 respond unnamed bit 7 = 0x1 ERROR => should be zero TOP_OF_MEM upper boundry = 0xFF INT_VECTOR_RELOCATE = 0xFFF unnamed bits 31 - 28 = 0xF ERROR => should be zero >> Rege0 Emulation Support Config 1 = 0x12345678 EMULATION_MODE_EN address map = 0x0 Disabled EMULATION_MODE_HW address map = 0x0 ERROR => should be one Proc Compatibility Hole = 0x0 forward to system memory PCI Compatibility Hole = 0x1 don't respond PIRQ_ACTIVE_HIGH PIRQ*polarity= 0x1 Active high PIRQ_EN PIRQ* emulation = 0x1 Enabled PCI FD Alias En = 0x1 respond unnamed bit 7 = 0x0 TOP_OF_MEM upper boundry = 0x56 INT_VECTOR_RELOCATE = 0x234 unnamed bits 31 - 28 = 0x1 ERROR => should be zero >> Rege4 Modified memory Status (no clear)= 0xffffffff MOD_MEM_STATUS HWM, LWM status = 0x3 Valid define block address LWM value = 0x7FFF HWM value = 0xEFFF >> Regec Modified memory Status (clear) = 0x12345678 MOD_MEM_STATUS HWM, LWM status = 0x0 Invalid LWM value = 0x159E HWM value = 0x091A >> Rege4 Modified memory Status (no clear)= 0x00000001 MOD_MEM_STATUS HWM, LWM status = 0x1 Valid same address LWM value = 0x0000 HWM value = 0x0000 >> Regec Modified memory Status (clear) = 0x00000002 MOD_MEM_STATUS HWM, LWM status = 0x2 Valid different addresses LWM value = 0x0000 HWM value = 0x0000 >> Regec Modified memory Status (clear) = 0x00000000 MOD_MEM_STATUS HWM, LWM status = 0x0 Invalid LWM value = 0x0000 HWM value = 0x0000 >> Rege8 ESCR2 Emulation Support Config 2 = 0xffffffff MOD_MEM_SIZE Modified mem reg = 0xFF Invalid value Unnamed bits 31 - 8 = 0xFFFFFF ERROR => should be zero >> Rege8 ESCR2 Emulation Support Config 2 = 0x00000001 MOD_MEM_SIZE Modified mem reg = 0x1 128 bytes (Not supported) Unnamed bits 31 - 8 = 0x000000 >> Rege8 ESCR2 Emulation Support Config 2 = 0x00000002 MOD_MEM_SIZE Modified mem reg = 0x2 256 bytes (Not supported) Unnamed bits 31 - 8 = 0x000000 >> Rege8 ESCR2 Emulation Support Config 2 = 0x00000003 MOD_MEM_SIZE Modified mem reg = 0x3 Invalid value Unnamed bits 31 - 8 = 0x000000 >> Rege8 ESCR2 Emulation Support Config 2 = 0x00000004 MOD_MEM_SIZE Modified mem reg = 0x4 512 bytes (Not supported) Unnamed bits 31 - 8 = 0x000000 >> Rege8 ESCR2 Emulation Support Config 2 = 0x00000008 MOD_MEM_SIZE Modified mem reg = 0x8 1 Kbytes (Not supported) Unnamed bits 31 - 8 = 0x000000 >> Rege8 ESCR2 Emulation Support Config 2 = 0x00000010 MOD_MEM_SIZE Modified mem reg = 0x10 2 Kbytes (Not supported) Unnamed bits 31 - 8 = 0x000000 >> Rege8 ESCR2 Emulation Support Config 2 = 0x00000020 MOD_MEM_SIZE Modified mem reg = 0x20 4 Kbytes Unnamed bits 31 - 8 = 0x000000 >> Rege8 ESCR2 Emulation Support Config 2 = 0x00000040 MOD_MEM_SIZE Modified mem reg = 0x40 8 Kbytes Unnamed bits 31 - 8 = 0x000000 >> Rege8 ESCR2 Emulation Support Config 2 = 0x00000080 MOD_MEM_SIZE Modified mem reg = 0x80 16 Kbytes (Not supported) Unnamed bits 31 - 8 = 0x000000 >> Rege8 ESCR2 Emulation Support Config 2 = 0x00000123 MOD_MEM_SIZE Modified mem reg = 0x23 Invalid value Unnamed bits 31 - 8 = 0x000001 ERROR => should be zero >> Regf0 MCCR1 Memory Control Config Reg = 0xffffffff Bank 0 Row = 0x3 12,13 or (11 x n x 2) Bank 1 Row = 0x3 12,13 or (11 x n x 2) Bank 2 Row = 0x3 12,13 or (11 x n x 2) Bank 3 Row = 0x3 12,13 or (11 x n x 2) Bank 4 Row = 0x3 12,13 or (11 x n x 2) Bank 5 Row = 0x3 12,13 or (11 x n x 2) Bank 6 Row = 0x3 12,13 or (11 x n x 2) Bank 7 Row = 0x3 12,13 or (11 x n x 2) PCKEN Memory interface parity checking = 0x1 Enabled RAM_TYPE = 0x1 DRAM or EDO RAM SREN Self refresh = 0x1 Enabled MEMGO RAM interface logic = 0x1 Enabled BURST Burst mode ROM timing = 0x1 burst-mode 8N64 ROM bank0 data path width= 0x1 8 bit 501 _MODE = 0x1 backward compatibility ROMFAL access time = 0x1F ROMNAL next access time = 0xF >> Regf0 MCCR1 Memory Control Config Reg = 0x12345678 Bank 0 Row = 0x0 9 or (12 x n x 4) Bank 1 Row = 0x2 11 or (13 x n x 4) Bank 2 Row = 0x3 12,13 or (11 x n x 2) Bank 3 Row = 0x1 10 or (13 x n x 2) Bank 4 Row = 0x2 11 or (13 x n x 4) Bank 5 Row = 0x1 10 or (13 x n x 2) Bank 6 Row = 0x1 10 or (13 x n x 2) Bank 7 Row = 0x1 10 or (13 x n x 2) PCKEN Memory interface parity checking = 0x0 Disabled RAM_TYPE = 0x0 SDRAM SREN Self refresh = 0x1 Enabled MEMGO RAM interface logic = 0x0 Disabled BURST Burst mode ROM timing = 0x1 burst-mode 8N64 ROM bank0 data path width= 0x1 8 bit 501 _MODE = 0x0 16501 type buffers ROMFAL access time = 0x04 ROMNAL next access time = 0x1 >> Regf0 MCCR1 Memory Control Config Reg = 0x00000000 Bank 0 Row = 0x0 9 or (12 x n x 4) Bank 1 Row = 0x0 9 or (12 x n x 4) Bank 2 Row = 0x0 9 or (12 x n x 4) Bank 3 Row = 0x0 9 or (12 x n x 4) Bank 4 Row = 0x0 9 or (12 x n x 4) Bank 5 Row = 0x0 9 or (12 x n x 4) Bank 6 Row = 0x0 9 or (12 x n x 4) Bank 7 Row = 0x0 9 or (12 x n x 4) PCKEN Memory interface parity checking = 0x0 Disabled RAM_TYPE = 0x0 SDRAM SREN Self refresh = 0x0 Disabled MEMGO RAM interface logic = 0x0 Disabled BURST Burst mode ROM timing = 0x0 standard (non burst-mode) 8N64 ROM bank0 data path width= 0x0 64 bit 501 _MODE = 0x0 16501 type buffers ROMFAL access time = 0x00 ROMNAL next access time = 0x0 >> Regf4 MCCR2 Memory Control Config Reg = 0xffffffff Read Modify Write parity = 0x1 Enabled BUF_MODE BCTL0 & BCTL1 mode = 0x1 BCTL0 direction, BCTL1 buf enable Refresh Interval = 0x1FFF = 8191 decimal EDO Enable = 0x1 EDO DRAM ECC enable = 0x1 Enabled TS_WAIT_TIMER = 0x7 8 clocks 120ns @ 66MHz 96ns @83MHz unnamed bits 28 - 22 = 0x7F ERROR => should be zero BSTOPRE[0-1] = 0x3 EXT_ECM_PAR_EN external parity= 0x1 Enabled EXT_ECM_ECC_EN external parity= 0x1 Enabled >> Regf4 MCCR2 Memory Control Config Reg = 0x12345678 Read Modify Write parity = 0x0 Disabled BUF_MODE BCTL0 & BCTL1 mode = 0x0 BCTL0 write, BCTL1 read enable Refresh Interval = 0x0ACF = 2767 decimal EDO Enable = 0x0 standard DRAM ECC enable = 0x0 Disabled TS_WAIT_TIMER = 0x0 2 clocks 30ns @ 66MHz 24ns @83MHz unnamed bits 28 - 22 = 0x48 ERROR => should be zero BSTOPRE[0-1] = 0x3 EXT_ECM_PAR_EN external parity= 0x0 Disabled EXT_ECM_ECC_EN external parity= 0x1 Enabled >> Regf4 MCCR2 Memory Control Config Reg = 0x00000000 Read Modify Write parity = 0x0 Disabled BUF_MODE BCTL0 & BCTL1 mode = 0x0 BCTL0 write, BCTL1 read enable Refresh Interval = 0x0000 = 0 decimal EDO Enable = 0x0 standard DRAM ECC enable = 0x0 Disabled TS_WAIT_TIMER = 0x0 2 clocks 30ns @ 66MHz 24ns @83MHz unnamed bits 28 - 22 = 0x0 BSTOPRE[0-1] = 0x0 EXT_ECM_PAR_EN external parity= 0x0 Disabled EXT_ECM_ECC_EN external parity= 0x0 Disabled >> Regf8 MCCR3 Memory Control Config Reg 3 = 0xffffffff RAS precharge interval RP1 DRAM = 0x7 7 clocks RAS CAS delay interval RCD2 DRAM = 0x7 7 clocks CAS assertion interval CAS3 DRAM = 0x7 7 clocks CAS precharge interval CP4 DRAM = 0x7 7 clocks CAS assertion interval CAS5 DRAM = 0x7 7 clocks RAS assertion interval for CBR DRAM = 0xF 15 clocks CAS write timing modifier DRAM = 0x1 Modified Data Latency from read command = 0xF Reserved Do not use Refresh to activate interval = 0xF 15 clocks Burst to precharge BSTOPRE[2-5] = 0xF >> Regf8 MCCR3 Memory Control Config Reg 3 = 0x00000000 RAS precharge interval RP1 DRAM = 0x0 8 clocks RAS CAS delay interval RCD2 DRAM = 0x0 8 clocks CAS assertion interval CAS3 DRAM = 0x0 8 clocks CAS precharge interval CP4 DRAM = 0x0 8 clocks CAS assertion interval CAS5 DRAM = 0x0 8 clocks RAS assertion interval for CBR DRAM = 0x0 16 clocks CAS write timing modifier DRAM = 0x0 Unmodified Data Latency from read command = 0x0 Reserved Do not use Refresh to activate interval = 0x0 16 clocks Burst to precharge BSTOPRE[2-5] = 0x0 >> Regf8 MCCR3 Memory Control Config Reg 3 = 0x12345678 RAS precharge interval RP1 DRAM = 0x0 8 clocks RAS CAS delay interval RCD2 DRAM = 0x7 7 clocks CAS assertion interval CAS3 DRAM = 0x1 1 clocks CAS precharge interval CP4 DRAM = 0x3 3 clocks CAS assertion interval CAS5 DRAM = 0x5 5 clocks RAS assertion interval for CBR DRAM = 0x8 8 clocks CAS write timing modifier DRAM = 0x0 Unmodified Data Latency from read command = 0x3 3 clocks Refresh to activate interval = 0x2 2 clocks Burst to precharge BSTOPRE[2-5] = 0x1 >> Regfc MCCR4 Memory Control Config Reg 4 = 0x00000000 Burst to Prechrg BSTOPRE[6-9] = 0x0 Activate to R/W int ACTORW = 0x0 16 clocks SDRAM mode Register SDMODE = 0x00 Wrap Length = 0x0 Reserved do not use Wrap Type = 0x0 Sequential CAS Latency = 0x0 Reserved do not use OPCODE = 0x0 RCBUF memory write buffer type= 0x0 Flow-through WCBUF memory read buffer type = 0x0 Flow-through or transparent EXT_ECM_EN external error mod = 0x0 Disabled Act to precharge int ACTOPRE = 0x0 16 clocks Prechrg to act int PRETOACT = 0x0 16 clocks >> Regfc MCCR4 Memory Control Config Reg 4 = 0xffffffff Burst to Prechrg BSTOPRE[6-9] = 0xF Activate to R/W int ACTORW = 0xF 15 clocks SDRAM mode Register SDMODE = 0xFFF Wrap Length = 0x7 Reserved do not use Wrap Type = 0x1 Interleaved CAS Latency = 0x7 Reserved do not use OPCODE = 0x1F RCBUF memory write buffer type= 0x1 Transparent or registered WCBUF memory read buffer type = 0x1 Registered EXT_ECM_EN external error mod = 0x3 Enabled Act to precharge int ACTOPRE = 0xF 15 clocks Prechrg to act int PRETOACT = 0xF 15 clocks >> Regfc MCCR4 Memory Control Config Reg 4 = 0x12345678 Burst to Prechrg BSTOPRE[6-9] = 0x8 Activate to R/W int ACTORW = 0x7 7 clocks SDRAM mode Register SDMODE = 0x456 Wrap Length = 0x6 Reserved do not use Wrap Type = 0x0 Sequential CAS Latency = 0x5 Reserved do not use OPCODE = 0x8 RCBUF memory write buffer type= 0x1 Transparent or registered WCBUF memory read buffer type = 0x1 Registered EXT_ECM_EN external error mod = 0x0 Disabled Act to precharge int ACTOPRE = 0x2 2 clocks Prechrg to act int PRETOACT = 0x1 1 clocks >> Regf0 MCCR1 Memory Control Config Reg = 0x53ec0000 Bank 0 Row = 0x0 9 or (12 x n x 4) Bank 1 Row = 0x0 9 or (12 x n x 4) Bank 2 Row = 0x0 9 or (12 x n x 4) Bank 3 Row = 0x0 9 or (12 x n x 4) Bank 4 Row = 0x0 9 or (12 x n x 4) Bank 5 Row = 0x0 9 or (12 x n x 4) Bank 6 Row = 0x0 9 or (12 x n x 4) Bank 7 Row = 0x0 9 or (12 x n x 4) PCKEN Memory interface parity checking = 0x0 Disabled RAM_TYPE = 0x0 SDRAM SREN Self refresh = 0x1 Enabled MEMGO RAM interface logic = 0x1 Enabled BURST Burst mode ROM timing = 0x0 standard (non burst-mode) 8N64 ROM bank0 data path width= 0x1 8 bit 501 _MODE = 0x1 backward compatibility ROMFAL access time = 0x07 ROMNAL next access time = 0x5 >> Regf4 MCCR2 Memory Control Config Reg = 0x30000caa Read Modify Write parity = 0x0 Disabled BUF_MODE BCTL0 & BCTL1 mode = 0x1 BCTL0 direction, BCTL1 buf enable Refresh Interval = 0x0195 = 405 decimal EDO Enable = 0x0 standard DRAM ECC enable = 0x0 Disabled TS_WAIT_TIMER = 0x1 2 clocks 30ns @ 66MHz 24ns @83MHz unnamed bits 28 - 22 = 0x40 ERROR => should be zero BSTOPRE[0-1] = 0x0 EXT_ECM_PAR_EN external parity= 0x0 Disabled EXT_ECM_ECC_EN external parity= 0x0 Disabled >> Regf8 MCCR3 Memory Control Config Reg 3 = 0x03100000 RAS precharge interval RP1 DRAM = 0x0 8 clocks RAS CAS delay interval RCD2 DRAM = 0x0 8 clocks CAS assertion interval CAS3 DRAM = 0x0 8 clocks CAS precharge interval CP4 DRAM = 0x0 8 clocks CAS assertion interval CAS5 DRAM = 0x0 8 clocks RAS assertion interval for CBR DRAM = 0x0 16 clocks CAS write timing modifier DRAM = 0x0 Unmodified Data Latency from read command = 0x1 1 clocks Refresh to activate interval = 0x3 3 clocks Burst to precharge BSTOPRE[2-5] = 0x0 >> Regfc MCCR4 Memory Control Config Reg 4 = 0x22002220 Burst to Prechrg BSTOPRE[6-9] = 0x0 Activate to R/W int ACTORW = 0x2 2 clocks SDRAM mode Register SDMODE = 0x22 Wrap Length = 0x2 4 Wrap Type = 0x0 Sequential CAS Latency = 0x2 2 OPCODE = 0x0 RCBUF memory write buffer type= 0x0 Flow-through WCBUF memory read buffer type = 0x0 Flow-through or transparent EXT_ECM_EN external error mod = 0x0 Disabled Act to precharge int ACTOPRE = 0x2 2 clocks Prechrg to act int PRETOACT = 0x2 2 clocks >> Rega0 Memory Page and Bank Information = 0x3a000001 0xa0:Memory Bank Enable Register = 0x01 Bank0 = 0x1 Enabled Bank1 = 0x0 Disabled Bank2 = 0x0 Disabled Bank3 = 0x0 Disabled Bank4 = 0x0 Disabled Bank5 = 0x0 Disabled Bank6 = 0x0 Disabled Bank7 = 0x0 Disabled 0xa1:unnamed bits 23 - 8 = 0x00 0xa3:Memory Page Mode Register = 0x3A = 3712 clocks >> End of File, Program complete