Configuration Register Decoder Version 0.8 July 10, 2000 Enter a description of this data, 60 characters or less >>Data set: MPC107 registers from Doug Big Endian Mode Please chose one of the following by number 1,2,3, or 4: 1. MPC106 Rev 4.0 2. MPC107 3. MPC8240 Host 4. MPC8240 Agent >>Choose printing order: 1. Big endian order 2. Little endian order You chose Big endian order for printing MPC107 Decoder Enter all values in hex, DO NOT preceed them with 0x Only use word boundry addresses, e.g. 0,4,8,etc Values are in little endian orientation and will be padded with zeros on the left Enter address : value Example: 04 : a00106 Enter "^D" i.e. EOF to exit >> Reg00 Device ID and Vendor ID = 0x00041057 0x00:Vendor ID = 0x1057 0x02:Device ID = 0x0004 >> Reg04 PCI Status/Command = 0x00A00106 0x04:PCI Command = 0x00a0 I/O Space = 0x0 Memory Space = 0x0 Do not respond to PCI memory accesses Bus Master = 0x0 Host mode Special Cycles = 0x0 Memory Write and Invalidate = 0x0 Use Memory Write unnamed bit 5 = 0x1 ERROR => should be zero Parity Error Response = 0x0 Parity errors are ignored unnamed bit 7 = 0x1 ERROR => should be zero SERR = 0x0 SERR driver disabled Fast Back to back = 0x0 unnamed bits 15-10 = 0x0 0x06:PCI Status = 0X0106 unnamed bits 0-4 = 0x6 ERROR => should be zero 66-MHz capable = 0x0 Not 66-MHz capable unnamed bit 6 = 0x0 Fast Back To Back = 0x0 ERROR => should be one Data Parity Detected = 0x1 Data Partity detected DEVSEL Use fast device Timing = 0x0 Signaled Target-abort = 0x0 No PCI target abort issued Received Target-abort = 0x0 No PCI target abort received Received Master-abort = 0x0 No PCI master abort Signaled System abort = 0x0 SEER not asserted Detected Parity Error = 0x0 Parity Error not detected >> Reg08 Class Code, Subclass Code, Standard Programming, Revision ID = 0x0e000110 0x08:Revision ID = 0x10 0x09:Standard Programing Interface = 0x01 Agent device with the I2O 0x0a:Subclass Code = 0x00 0x0b:Base Class Code = 0x0E Target device with I2O >> Reg0c BIST Control, Header Type, Latency Timer, Cache Line Size = 0x0000f808 0x0C:Cache Line Size = 0x08 Only valid values are 0 or 8 0x0D:Latency Timer = 0xF8 0x0E:Header Type = 0x00 0x0F:BIST Control = 0x00 >> Reg10 LMBAR Local Memory Base Register = 0x00000008 Memory Space Indicator = 0x0 Type = 0x0 Prefetchable = 0x1 Prefetchable unnamed bits 11 - 4 = 0x00 Inbound Memory Base Address = 0x0000 >> Reg14 PCSR Peripheral Control and Status Register Base Address = 0x00000000 PCI Base Address = 0x00000 unnamed bits 11 - 0 = 0x00 >> ERROR: Invalid Register 0x18, try again >> ERROR: Invalid Register 0x1C, try again >> ERROR: Invalid Register 0x20, try again >> ERROR: Invalid Register 0x24, try again >> ERROR: Invalid Register 0x28, try again >> ERROR: Invalid Register 0x2C, try again >> ERROR: Invalid Register 0x30, try again >> ERROR: Invalid Register 0x34, try again >> ERROR: Invalid Register 0x38, try again >> Reg3c Max Lat, Min GNT, Interrupt Pin, Interrupt Line = 0x00000100 0x3C:Interrupt Line = 0x00 0x3D:Interrupt Pin = 0x01 0x3E:MIN GNT = 0x00 0x0F:MAX LAT = 0x00 >> Reg40 Subrodinate Bus # and Bus Number = 0x00000000 0x40:Bus Number = 0x00 0x41:Subordinate Bus # = 0x00 0x42:unnammed bits 31 - 17 = 0x0000 >> Reg44 PCI Arbiter Control = 0x00000000 0x44:unnammed bits 16 - 0 = 0x0000 0x46:PCI Arbiter Control = 0x0000 External Device Priority levels = 0x0 unnammed bits 6 - 5 = 0x0 MPC107 Priority Level = 0x0 Low unnammed bits 9 - 8 = 0x0 Retry PCI Configuration Cycle = 0x0 PCI target responds to external PCI unnammed bits 12 - 11 = 0x0 Parking Mode Bus parked with = 0x0 the last device Enable Internal PCI arbitration = 0x0 Internal Arbiter disabled. >> ERROR: Invalid Register 0x48, try again >> ERROR: Invalid Register 0x4C, try again >> ERROR: Invalid Register 0x50, try again >> ERROR: Invalid Register 0x54, try again >> ERROR: Invalid Register 0x58, try again >> ERROR: Invalid Register 0x60, try again >> ERROR: Invalid Register 0x68, try again >> ERROR: Invalid Register 0x6C, try again >> Reg70 Power Management & Output Driver = 0xbf000000 0x70:Power Management Register 1 = 0x0000 unnammed bit 0 = 0x0 Selects Clock Source = 0x0 Disable the test clock driver Sleep Mode = 0x0 Disables Sleep mode Nap Mode = 0x0 Disables Nap mode Doze Mode = 0x0 Disables Doze mode BR1* Wake = 0x0 Ignored during nap and sleep Power Management Enable = 0x0 Disabled unnammed bits 9 - 8 = 0x0 Suspend Mode QACK* = 0x0 QACK* not asserted in suspend mode unnammed bits 11 = 0x0 Low Power Refresh = 0x0 Don't perform mem refresh in SLEEP unnammed bit 13 = 0x0 No Sleep Message Broadcast = 0x0 Not supported Must be 1 No Nap Msg Halt command Broadcast = 0x0 Not supported Must be 1 0x72:Power Management Register 2 = 0x00 unnammed bit 0 = 0x0 Sampling When Waking from Sleep = 0x0 Does not sample PLL Sampling When Waking from Suspend = 0x0 Does not sample PLL unnammed bit 3 = 0x0 PCI Hold Delay = 0x0 Recommened for 66Mhz DLL Extend = 0x0 DLL extended range 0x73:Output Driver Config Reg = 0xBF Driver Memory Clock SDRAM_CLK = 0x3 8 ohm drive capability Driver PCI Clock PCI_CLK = 0x3 8 ohm drive capability Driver Memory Control MDH,MDL = 0x3 8 ohm drive capability Driver Capability CPU signals = 0x0 High drive capability Driver Capability PCI signals = 0x1 Medium drive capability >> Reg74 Power Management & Output Driver = 0x8d000300 0x74:Clock Driver Control Register = 0x0300 CPU_CLK2_DIS output = 0x0 Enabled CPU_CLK1_DIS output = 0x0 Enabled CPU_CLK0_DIS output = 0x0 Enabled SDRAM_CLK3_DIS output = 0x0 Enabled SDRAM_CLK2_DIS output = 0x0 Enabled SDRAM_CLK1_DIS output = 0x0 Enabled SDRAM_CLK0_DIS output = 0x0 Enabled SDRAM_SYNC_OUT output = 0x0 Enabled Driver capability for CPU_CLK = 0x3 8 ohm drive capability PCI_CL4_DIS output = 0x0 Enabled PCI_CL3_DIS output = 0x0 Enabled PCI_CL2_DIS output = 0x0 Enabled PCI_CL1_DIS output = 0x0 Enabled PCI_CL0_DIS output = 0x0 Enabled PCI_SYNC_OUT output = 0x0 Enabled 0x76:Misc. Driver Control Register = 0x00 unnamed bits 4 - 0 = 0x0 HI-Z_Qack = 0x0 is always driven SRESET_OD_MODE = 0x0 is always driven MCP_OD_MODE = 0x0 is always driven 0x77:unnamed bits 25 - 31 = 0x8D ERROR => should be zero >> Reg78 EUMBAR Embedded Util Mem Base A Reg = 0x00000000 unnamed bits 19 - 20 = 0x0000 Base Address = 0x000 >> ERROR: Invalid Register 0x7C, try again >> Reg80 Memory Starting Address Register 1 = 0x00000000 Starting Address Bank 0 = 0x00 Starting Address Bank 1 = 0x00 Starting Address Bank 2 = 0x00 Starting Address Bank 3 = 0x00 >> Reg84 Memory Starting Address Register 2 = 0x00000000 Starting Address Bank 4 = 0x00 Starting Address Bank 5 = 0x00 Starting Address Bank 6 = 0x00 Starting Address Bank 7 = 0x00 >> Reg88 Extended Memory Ending Address 1 = 0x00000000 Extended Starting Address 3 = 0x0 unnammed bits 7 - 2 = 0x00 Extended Starting Address 2 = 0x0 unnammed bits 15 - 10 = 0x00 Extended Starting Address 1 = 0x0 unnammed bits 23 - 18 = 0x00 Extended Starting Address 0 = 0x0 unnammed bits 31 - 26 = 0x00 >> Reg8c Extended Memory Ending Address 2 = 0x00000000 Extended Starting Address 7 = 0x0 unnammed bits 7 - 2 = 0x00 Extended Starting Address 6 = 0x0 unnammed bits 15 - 10 = 0x00 Extended Starting Address 5 = 0x0 unnammed bits 23 - 18 = 0x00 Extended Starting Address 4 = 0x0 unnammed bits 31 - 26 = 0x00 >> Reg90 Memory Ending Address Register 1 = 0x0000003f Ending Address Bank 0 = 0x3F Ending Address Bank 1 = 0x00 Ending Address Bank 2 = 0x00 Ending Address Bank 3 = 0x00 >> Reg94 Memory Ending Address Register 2 = 0x00000000 Ending Address Bank 4 = 0x00 Ending Address Bank 5 = 0x00 Ending Address Bank 6 = 0x00 Ending Address Bank 7 = 0x00 >> Reg98 Extended Memory Ending Address 1 = 0x00000000 Extended Ending Address 3 = 0x0 unnammed bits 7 - 2 = 0x00 Extended Ending Address 2 = 0x0 unnammed bits 15 - 10 = 0x00 Extended Ending Address 1 = 0x0 unnammed bits 23 - 18 = 0x00 Extended Ending Address 0 = 0x0 unnammed bits 31 - 26 = 0x00 >> Reg9c Extended Memory Ending Address 2 = 0x00000000 Extended Ending Address 7 = 0x0 unnammed bits 7 - 2 = 0x00 Extended Ending Address 6 = 0x0 unnammed bits 15 - 10 = 0x00 Extended Ending Address 5 = 0x0 unnammed bits 23 - 18 = 0x00 Extended Ending Address 4 = 0x0 unnammed bits 31 - 26 = 0x00 >> Rega0 Memory Page and Bank Information = 0x78000001 0xa0:Memory Bank Enable Register = 0x01 Bank0 = 0x1 Enabled Bank1 = 0x0 Disabled Bank2 = 0x0 Disabled Bank3 = 0x0 Disabled Bank4 = 0x0 Disabled Bank5 = 0x0 Disabled Bank6 = 0x0 Disabled Bank7 = 0x0 Disabled 0xa1:unnamed bits 23 - 8 = 0x00 0xa3:Memory Page Mode Register = 0x78 = 7680 clocks >> ERROR: Invalid Register 0xA4, try again >> Rega8 PICR1 Processor Interface Config 1= 0xff141053 CF_MP Multiprocessor configuration = 0x3 Multiprocessor Speculative PCI Reads = 0x0 Disabled CF_APARK Processor Parked on 60x = 0x0 No processor CF_LOOP_SNOOP Repeat Snoops = 0x1 Enabled LE_MODE Little Endian MODE = 0x0 Big-Endian Mode ST_GATH_EN Store gathering = 0x1 Enabled NO_BUS_WIDTH_CHECK Flash width = 0x0 Restricted to bus Width unnamed bits 9 - 8 = 0x0 TEA_EN TEA enable = 0x0 Disabled MPC_EN Machine Check enable = 0x0 Disabled FLASH_WR_EN Flash Write enable = 0x1 Enabled CF_LBA_EN Local Bus Slave enable = 0x0 Disabled CF_MP_ID Multiprocessor ID = 0x0 Uniprocessor ADDRESS_MAP = 0x0 Map B PROC_TYPE Processor Type = 0x2 603x, 7xx, and 74xx unnamed bit 19 = 0x0 RCS0 ROM Location = 0x1 Processor/memory data Bus unnamed bit 21 = 0x0 CF_BREAD_WS Burst Read Wait States = 0x0 0 wait state (2:1 clock) unnamed bits 31 - 24 = 0xFF >> Regac PICR2 Processor Interface Config 2= 0x20080208 unnamed bits 1 - 0 = 0x0 CF_APHASE_WS Address phase wait = 0x2 2 wait states unnamed bits 8 - 4 = 0x8 ERROR => should be zero CF_LBCLAIM_WS LBCLAIM wait states = 0x1 1 clock cycle unnamed bits 17 - 11 = 0x08 ERROR => should be zero CF_SNOOP_WS SNOOP wait states = 0x2 2 wait states unnamed bits 24 - 20 = 0x08 ERROR => should be zero FLASH_WR_LOCKOUT = 0x0 Disabled CF_FF0_LOCAL ROM remap enable = 0x0 Enabled NO_SNOOP_EN Generate Snooping = 0x0 Disabled unnamed bit 28 = 0x0 SERIALIZE_ON_CFG Config writes = 0x1 Serialization & flush buffers unnamed bits 31 - 30 = 0x0 >> ERROR: Invalid Register 0xB0, try again >> ERROR: Invalid Register 0xB4, try again >> Regb8 ECC Single Bit Error = 0x00002000 0xb8:ECC single bit counter = 0x00 0xB9:ECC single bit Trigger = 0x20 single bit error threshold 0xba:unnamed bits 23 - 17 = 0x00 0xbb:unnamed bits 31 - 18 = 0x00 >> ERROR: Invalid Register 0xBC, try again >> Regc0 Error Enabling and detection 1 = 0x11000081 0xc0:Error Enabling 1 = 0x81 Processor Transaction = 0x1 Enabled PCI master abort = 0x0 Disabled Memory parity/ECC = 0x0 Disabled PCI master PERR* = 0x0 Disabled Memory refresh overflow = 0x0 Disabled Memory select = 0x0 Disabled PCI target PERR* = 0x0 Disabled RX_SERR_EN = 0x1 Enabled 0xc1:Error Detection 1 = 0x00 Unsupported Processor Transaction = 0x00 No error detected Memory Read Parity ECC trigger = 0x0 No error detected Processor/PCI cycle error occurred = 0x0 on processor-init cycle Memory refresh overflow error = 0x0 No error detected Memory Select Error = 0x0 No error detected PCI target PERR* parity error = 0x0 No error detected PCI SERR* two clks after address = 0x0 No error detected 0xc2:unnamed bits 23 - 17 = 0x00 0xc3:Proc. Bus Error Status = 0x11 Copy TSIZ on processor bus error = 0x1 Copy of TT on processor bus error = 0x02 >> Regc4 Error Enabling and detection 2 = 0x00000000 0xc4:Error Enabling 2 = 0x00 Flash ROM Write Enable = 0x0 Disabled PCI Received target = 0x0 Disabled Processor memory parity = 0x0 Disabled ECC multi-bit error = 0x0 Disabled Unnamed bit 4 = 0x0 Unnamed bit 5 = 0x0 PCI SERR = 0x0 Disabled PCI address parity = 0x0 Disabled 0xc5:Error Detection 2 = 0x00 Flash ROM write Error = 0x0 No error detected Unnamed bit 1 = 0x0 Processor/memory write parity = 0x0 No error detected ECC mutli-bit error = 0x0 No error detected Unnamed bits 5 - 4 = 0x0 PCI SERR error = 0x0 No error detected Invalid error address Register val = 0x0 valid 0xc6:unnamed bits 23 - 17 = 0x00 0xc7:PCI Bus Error Status = 0x00 Copy of C/BE* on PCI bus error = 0x0 MPC107 master/target status = 0x0 PCI master unnamed bits 31 - 29 (7 - 5) = 0x0 >> Regc8 Processor/PCI Error Address Reg = 0x00000000 0xc8:A[0:7] or AD[31:24] = 0x00 0xc9:A[8:15] or AD[23:16] = 0x00 0xca:A[16:23] or AD[15:8] = 0x00 0xcb:A[24:32] or AD[7:0] = 0x00 >> ERROR: Invalid Register 0xCC, try again >> ERROR: Invalid Register 0xD0, try again >> ERROR: Invalid Register 0xD4, try again >> ERROR: Invalid Register 0xD8, try again >> ERROR: Invalid Register 0xDC, try again >> Rege0 AMBOR Address Map B Options Reg = 0x00000000 unnamed bits 1 - 0 = 0x0 ERROR => should be all ones Proc Compatibility Hole = 0x0 forward to system memory PCI Compatibility Hole = 0x0 respond unnamed bits 5 - 4 = 0x0 PCI FD Alias En = 0x0 don't respond CPU FD Alias En = 0x0 route normally unnamed bits 31 - 8 = 0x0 >> ERROR: Invalid Register 0xE4, try again >> ERROR: Invalid Register 0xE8, try again >> ERROR: Invalid Register 0xEC, try again >> Regf0 MCCR1 Memory Control Config Reg = 0xf46d0000 Bank 0 Row = 0x0 9 or (12 x n x 4) Bank 1 Row = 0x0 9 or (12 x n x 4) Bank 2 Row = 0x0 9 or (12 x n x 4) Bank 3 Row = 0x0 9 or (12 x n x 4) Bank 4 Row = 0x0 9 or (12 x n x 4) Bank 5 Row = 0x0 9 or (12 x n x 4) Bank 6 Row = 0x0 9 or (12 x n x 4) Bank 7 Row = 0x0 9 or (12 x n x 4) PCKEN Memory interface parity checking = 0x1 Enabled RAM_TYPE = 0x0 SDRAM SREN Self refresh = 0x1 Enabled MEMGO RAM interface logic = 0x1 Enabled BURST Burst mode ROM timing = 0x0 standard (non burst-mode) DBUS_SIZ[0-1] = 0x3 ROMFAL access time = 0x08 ROMNAL next access time = 0xF >> Regf4 MCCR2 Memory Control Config Reg = 0x00001839 Read Modify Write parity = 0x1 Enabled RSV_PG Reserve one open page = 0x0 Four open page mode Refresh Interval = 0x0307 = 775 decimal EDO Enable = 0x0 standard DRAM ECC enable = 0x0 Disabled Inline Read Parity enable = 0x0 Disabled Inline Report Parity enable = 0x0 Disabled Inline Parity not ECC = 0x0 Disabled ASFALL timing = 0x0 clocks ASRISE timing for Port X = 0x0 clocks TS Wait Timer = 0x0 2 clocks min disable time >> Regf8 MCCR3 Memory Control Config Reg 3 = 0xf3300000 RAS precharge interval RP1 DRAM = 0x0 Reserved Do not use RAS CAS delay interval RCD2 DRAM = 0x0 8 clocks CAS assertion interval CAS3 DRAM = 0x0 8 clocks CAS precharge interval CP4 DRAM = 0x0 Reserved Do not use CAS assertion interval CAS5 DRAM = 0x0 8 clocks RAS assertion interval for CBR DRAM = 0x0 16 clocks CAS write timing modifier DRAM = 0x0 Unmodified Data Latency from read command = 0x3 3 clocks Refresh to activate interval = 0x3 3 clocks Burst to precharge BSTOPRE[2-5] = 0xF >> Regfc MCCR4 Memory Control Config Reg 4 = 0x251e222f Burst to Precharge BSTOPRE_L = 0xF Activate to R/W int ACTORW = 0x2 2 clocks SDRAM mode Register = 0x22 Burst Length = 0x2 4 Wrap Type = 0x0 Sequential CAS Latency = 0x2 2 REGDIMM = 0x0 Unnamed bit 16 = 0x0 DEBUS_SIZE = 0x1 Burst to precharge bits 0-1 = 0x3 Least sig bit of memory data = 0x1 Most sig bit of memory data = 0x0 Reserved do not use Length of burst = 0x0 Four beats per burst Activate to precharge interval= 0x5 5 clocks Precharge to activate interval= 0x2 2 clocks >> End of File, Program complete