#ifndef pciLib_h
#define pciLib_h

/*
modification history
--------------------
01a,30Apr98,My 		Created
*/

#include "errors.h"

#define  MAX_PCI_HEADER_REG 42
#define  NAME_LEN           50
#define  HI_PCIDEV_NO	    30		/* Highest Pci device Num. */
#define  LO_PCIDEV_NO 	    10		/* Lowest Pci device Num. */
#define  HI_BASEREG_NO	     5		/* Base registers start from */
#define  LO_BASEREG_NO       0		/* 0 to 5 */
/* #define  MAX_PCIREG_NO      32 */

#define  PCIREG_BASE_ADR    0x80000000	/* PCI reg. base address */
#define  PCIDEV_START_BIT   11		/* DeviceNo starts at bit 11 */
#define  PCIBUS_START_BIT   16		/* Bus number starts at bit 16 */
#define  PCIFUNC_START_BIT   9		/* Func.No starts at bit 8 */

#define  PCI_INTPIN	    0x3d	/* Start addr. of int. pin reg. */
#define  PCI_CLASS 	    0x0b
#define  PCI_SUBCLASS	    0x0a
#define  PCI_STDPROGRAM	    0x09
#define  PCI_BASE_ADDR0	    0x10
#define  PCI_BASE_ADDR1	    0x14
#define  PCI_COMMAND	    0x04

#define  PCI_BASE_IOSPACE   0x1		/* Base Addr. I/O space */
#define  PCI_BASE_MEMSPACE  0x0		/* Base Addr. Memory space */


/* PCI command bits - Taken from ...\h\drv\pci\pciIomapLib.h - My 5/98 */

#define PCI_CMD_IO_ENABLE	0x0001	/* IO access enable */
#define PCI_CMD_MEM_ENABLE	0x0002	/* memory access enable */
#define PCI_CMD_MASTER_ENABLE	0x0004	/* bus master enable */
#define PCI_CMD_MON_ENABLE	0x0008	/* monitor special cycles enable */
#define PCI_CMD_WI_ENABLE	0x0010	/* write and invalidate enable */
#define PCI_CMD_SNOOP_ENABLE	0x0020	/* palette snoop enable */
#define PCI_CMD_PERR_ENABLE	0x0040	/* parity error enable */
#define PCI_CMD_WC_ENABLE	0x0080	/* wait cycle enable */
#define PCI_CMD_SERR_ENABLE	0x0100	/* system error enable */
#define PCI_CMD_FBTB_ENABLE	0x0200	/* fast back to back enable */


struct PciHeaderStr {
        int  reg_address;
        int  reg_size;
        char access_mode;
        char reg_name[NAME_LEN];
  };


extern unsigned long config_addr;
extern unsigned long config_data;

#define PciConfAddr  config_addr
#define PciConfData  config_data
#define OK     0

// PCI Class Codes.

#define PCI_CLASS_UNKNOWN		0x00
#define PCI_CLASS_STORAGE		0x01
#define PCI_CLASS_NETWORK		0x02
#define PCI_CLASS_DISPLAY		0x03
#define PCI_CLASS_MMEDIA		0x04
#define PCI_CLASS_MEMORY		0x05
#define PCI_CLASS_BRIDGE		0x06


/* function prototypes */

ULONG  pSwap4Bytes(ULONG inVal);
ULONG  pciRegGet(ULONG pciAddr, ULONG Reg);
STATUS pciRegSet(ULONG pciAddr, ULONG Reg, ULONG Value);
ULONG  pReadAReg(int devNo, int pIndex);
STATUS pWriteAReg(int devNo, int pIndex, ULONG Val);
STATUS pciDevProbe (void);
ULONG  pciRegRead(int devNo, int regNo);
STATUS pciRegWrite(int devNo, int regNo, ULONG Val);
void   pciConfShow(int devNo);
STATUS pciFindDevice(int vendorId, int deviceId, int index, int *pBusNo, 
		     int *pDeviceNo, int *pFuncNo);
int FindPCIDeviceClass( int WantClass, unsigned long *cfa );

#endif