#ifndef REG_MEMMAP_H
#define REG_MEMMAP_H

#define  MAX_MPC106_REG	54
#define  MAX_MPC107_REG	57
#define  NAME_LEN       50

struct mpc106_tbl_str {
	unsigned long reg_address; 
	int  reg_size;
	int  access_size;
	char access_mode;
	char reg_name[NAME_LEN];
  };

#ifndef MEMMAP_DEF_ONLY
/*								 */
/* Some MPC106 registers allow byte access, half word access, or */
/* word access.  The accessible size of each register is defined */
/* in the access_size field.  The values are: 		         */
/*     1 - byte access						 */
/*     2 - half-word access					 */
/*     4 - word access						 */
/* In case a register allows byte, halfword and word accessible, */
/* the value of the access_size field is 7 (1+2+4).  If it is    */
/* byte and halfword accessible only, the value is 3 (1+2).      */
/*								 */

struct mpc106_tbl_str mpc106_tbl[MAX_MPC106_REG] = {
 /*  0 */ { 0x00, 2, 2, 'r', "Vendor ID" },
 /*  1 */ { 0x02, 2, 2, 'r', "Device ID" },
 /*  2 */ { 0x04, 2, 2, 'b', "PCI command" },
 /*  3 */ { 0x06, 2, 2, 'b', "PCI status"},
 /*  4 */ { 0x08, 1, 1, 'r', "Revision ID" },
 /*  5 */ { 0x09, 1, 1, 'r', "Standard programming interface"},
 /*  6 */ { 0x0a, 1, 1, 'r', "Subclass code" },
 /*  7 */ { 0x0b, 1, 1, 'r', "Class code" },
 /*  8 */ { 0x0c, 1, 1, 'r', "Cache line size" },
 /*  9 */ { 0x0d, 1, 1, 'r', "Latency timer" },
 /* 10 */ { 0x0e, 1, 1, 'r', "Header type" },
 /* 11 */ { 0x0f, 1, 1, 'r', "BIST control" },
 /* 12 */ { 0x3c, 1, 1, 'r', "Interrupt line" },
 /* 13 */ { 0x3d, 1, 1, 'r', "Interrupt pin" },
 /* 14 */ { 0x3e, 1, 1, 'r', "MIN GNT" },
 /* 15 */ { 0x3f, 1, 1, 'r', "MAX GNT" },
 /* 16 */ { 0x40, 1, 1, 'r', "Bus number" },
 /* 17 */ { 0x41, 1, 1, 'b', "Subordinate bus number" },
 /* 18 */ { 0x42, 1, 1, 'r', "Disconnect counter" },
 /* 19 */ { 0x44, 2, 2, 'r', "Special cycle address" },
 /* 20 */ { 0x70, 2, 3, 'b', "Power management config. 1" },
 /* 21 */ { 0x72, 1, 1, 'b', "Power management config. 2" },
 /* 22 */ { 0x73, 1, 1, 'b', "Reserved" },
 /* 23 */ { 0x80, 4, 7, 'b', "Memory starting address-upper" },
 /* 24 */ { 0x84, 4, 7, 'b', "Memory starting address-lower" },
 /* 25 */ { 0x88, 4, 7, 'b', "Extended mem. starting addr.-upper"},
 /* 26 */ { 0x8c, 4, 7, 'b', "Extended mem. starting addr.-lower"},
 /* 27 */ { 0x90, 4, 4, 'b', "Memory ending address-upper" },
 /* 28 */ { 0x94, 4, 4, 'b', "Memory ending address-lower" },
 /* 29 */ { 0x98, 4, 7, 'b', "Extended mem. ending address-upper"},
 /* 30 */ { 0x9c, 4, 7, 'b', "Extended mem. ending address-lower"},
 /* 31 */ { 0xa0, 1, 1, 'b', "Memory bank enable" },
 /* 32 */ { 0xa3, 1, 1, 'b', "Memory page mode" },
 /* 33 */ { 0xa8, 4, 7, 'b', "Processor interface config. 1"},
 /* 34 */ { 0xac, 4, 7, 'b', "Processor interface config. 2"},
 /* 35 */ { 0xb8, 1, 1, 'b', "ECC single-bit error counter"},
 /* 36 */ { 0xb9, 1, 1, 'b', "ECC single-bit error trigger"},
 /* 37 */ { 0xba, 1, 1, 'b', "Alternate OS visible parameters 1"},
 /* 38 */ { 0xbb, 1, 1, 'b', "Alternate OS visible parameters 2"},
 /* 39 */ { 0xc0, 1, 1, 'b', "Error enabling 1" },
 /* 40 */ { 0xc1, 1, 1, 'b', "Error detection 1" },
 /* 41 */ { 0xc3, 1, 1, 'b', "60x bus error status" },
 /* 42 */ { 0xc4, 1, 1, 'b', "Error enabling 2" },
 /* 43 */ { 0xc5, 1, 1, 'b', "Error detection 2" },
 /* 44 */ { 0xc7, 1, 1, 'b', "PCI bus error status - no clear"},
 /* 45 */ { 0xc8, 4, 4, 'r', "60x/PCI error address"},
 /* 46 */ { 0xe0, 4, 7, 'b', "Emulation support config. 1"},
 /* 47 */ { 0xe4, 4, 7, 'r', "Modified memory status" },
 /* 48 */ { 0xe8, 4, 7, 'b', "Emulation support config. 2"},
 /* 49 */ { 0xec, 4, 7, 'r', "Modified memory status - clear"},
 /* 50 */ { 0xf0, 4, 7, 'b', "Memory control config. 1"},
 /* 51 */ { 0xf4, 4, 7, 'b', "Memory control config. 2"},
 /* 52 */ { 0xf8, 4, 7, 'b', "Memory control config. 3"},
 /* 53 */ { 0xfc, 4, 7, 'b', "Memory control config. 4"},
 };

struct mpc106_tbl_str mpc107_tbl[MAX_MPC107_REG] = {
 /*  0 */ { 0x00, 2, 2, 'r', "Vendor ID" },
 /*  1 */ { 0x02, 2, 2, 'r', "Device ID" },
 /*  2 */ { 0x04, 2, 2, 'b', "PCI command" },
 /*  3 */ { 0x06, 2, 2, 'b', "PCI status"},
 /*  4 */ { 0x08, 1, 1, 'r', "Revision ID" },
 /*  5 */ { 0x09, 1, 1, 'r', "Standard programming interface"},
 /*  6 */ { 0x0a, 1, 1, 'r', "Subclass code" },
 /*  7 */ { 0x0b, 1, 1, 'r', "Class code" },
 /*  8 */ { 0x0c, 1, 1, 'r', "Cache line size" },
 /*  9 */ { 0x0d, 1, 1, 'r', "Latency timer" },
 /* 10 */ { 0x0e, 1, 1, 'r', "Header type" },
 /* 11 */ { 0x0f, 1, 1, 'r', "BIST control" },
 /* 12 */ { 0x10, 4, 4, 'b', "Local Memory Base Address" },
 /* 13 */ { 0x14, 4, 4, 'b', "Peripheral ctrl/stat reg base addr" },
 /* 14 */ { 0x3c, 1, 1, 'r', "Interrupt line" },
 /* 15 */ { 0x3d, 1, 1, 'r', "Interrupt pin" },
 /* 16 */ { 0x3e, 1, 1, 'r', "MIN GNT" },
 /* 17 */ { 0x3f, 1, 1, 'r', "MAX GNT" },
 /* 18 */ { 0x46, 2, 2, 'b', "PCI arbiter control" },
 /* 19 */ { 0x48, 4, 6, 'w', "Performance monitor command" },
 /* 20 */ { 0x4c, 2, 3, 'b', "Performance monitor mode ctrl" },
 /* 21 */ { 0x50, 4, 4, 'b', "Performance monitor counter 0" },
 /* 22 */ { 0x54, 4, 4, 'b', "Performance monitor counter 1" },
 /* 23 */ { 0x58, 4, 4, 'b', "Performance monitor counter 2" },
 /* 24 */ { 0x5c, 4, 4, 'b', "Performance monitor counter 3" },	  
 /* 25 */ { 0x70, 2, 3, 'b', "Power management config. 1" },
 /* 26 */ { 0x72, 1, 1, 'b', "Power management config. 2" },
 /* 27 */ { 0x73, 1, 1, 'b', "ODCR: Output driver control" },
 /* 28 */ { 0x74, 2, 3, 'b', "CDCR: CLK driver control" },
 /* 28a*/ { 0x76, 1, 1, 'b', "MDCR: Misc I/O control" },
 /* 29 */ { 0x78, 4, 4, 'b', "EUMBBAR: Embedded util mem blk base addr."},  
 /* 30 */ { 0x80, 4, 7, 'b', "MSAR1: Memory starting address 1" },
 /* 31 */ { 0x84, 4, 7, 'b', "MSAR2: Memory starting address 2" },
 /* 32 */ { 0x88, 4, 7, 'b', "EMSAR1: Extended mem. starting address 1"},
 /* 33 */ { 0x8c, 4, 7, 'b', "EMSAR2: Extended mem. starting address 2"},
 /* 34 */ { 0x90, 4, 4, 'b', "MEAR1: Memory ending address 1" },
 /* 35 */ { 0x94, 4, 4, 'b', "MEAR2: Memory ending address 2" },
 /* 36 */ { 0x98, 4, 7, 'b', "EMEAR1: Extended mem. ending address 1"},
 /* 37 */ { 0x9c, 4, 7, 'b', "EMEAR2: Extended mem. ending address 2"},
 /* 38 */ { 0xa0, 1, 1, 'b', "MBEN: Memory bank enable" },
 /* 39 */ { 0xa3, 1, 1, 'b', "MPM: Memory page mode" },
 /* 40 */ { 0xa8, 4, 7, 'b', "PICR1: Processor interface config. 1"},
 /* 41 */ { 0xac, 4, 7, 'b', "PICR2: Processor interface config. 2"},
 /* 42 */ { 0xb8, 1, 1, 'b', "ECC single-bit error counter"},
 /* 43 */ { 0xb9, 1, 1, 'b', "ECC single-bit error trigger"},
 /* 44 */ { 0xc0, 1, 1, 'b', "ERREN1: Error enabling 1" },
 /* 45 */ { 0xc1, 1, 1, 'b', "ERRDET1: Error detection 1" },
 /* 46 */ { 0xc3, 1, 1, 'b', "60x bus error status" },
 /* 47 */ { 0xc4, 1, 1, 'b', "ERREN2: Error enabling 2" },
 /* 48 */ { 0xc5, 1, 1, 'b', "ERRDET2: Error detection 2" },
 /* 49 */ { 0xc7, 1, 1, 'b', "PCI bus error status - no clear"},
 /* 50 */ { 0xc8, 4, 4, 'r', "60x/PCI error address"},
 /* 51 */ { 0xe0, 4, 7, 'b', "Emulation support config. 1"},
 /* 52 */ { 0xf0, 4, 7, 'b', "MCCR1: Memory control config. 1"},
 /* 53 */ { 0xf4, 4, 7, 'b', "MCCR2: Memory control config. 2"},
 /* 54 */ { 0xf8, 4, 7, 'b', "MCCR3: Memory control config. 3"},
 /* 55 */ { 0xfc, 4, 7, 'b', "MCCR4: Memory control config. 4"},

/* Plus one -- see 28a -- why are these being manually numbered anyway? 
   That's what compilers are for.  GM */

 };

#endif
#endif