#include "cpu.h" extern STATUS rd_MQ(); extern STATUS rd_XER(); extern STATUS rd_RTCU(); extern STATUS rd_RTCL(); extern STATUS rd_LR(); extern STATUS rd_CTR(); extern STATUS rd_DSISR(); extern STATUS rd_DAR(); extern STATUS rd_DEC(); extern STATUS rd_SDR1(); extern STATUS rd_SRR0(); extern STATUS rd_SRR1(); extern STATUS rd_SPRG(); extern STATUS rd_EAR(); extern STATUS rd_TBL(); extern STATUS rd_TBU(); extern STATUS rd_PVR(); extern STATUS rd_BATU(); extern STATUS rd_BATL(); extern STATUS rd_IBATU(); extern STATUS rd_IBATL(); extern STATUS rd_DBATU(); extern STATUS rd_DBATL(); extern STATUS rd_MMCR0(); extern STATUS rd_PMC1(); extern STATUS rd_PMC2(); extern STATUS rd_SIA(); extern STATUS rd_MMCR1(); extern STATUS rd_PMC3(); extern STATUS rd_PMC4(); extern STATUS rd_SDA(); extern STATUS rd_DMISS(); extern STATUS rd_DCMP(); extern STATUS rd_HASH1(); extern STATUS rd_HASH2(); extern STATUS rd_IMISS(); extern STATUS rd_ICMP(); extern STATUS rd_RPA(); extern STATUS rd_HID0(); extern STATUS rd_HID1(); extern STATUS rd_HID2(); extern STATUS rd_USIA(); extern STATUS rd_IABR(); extern STATUS rd_DABR(); extern STATUS rd_L2CR(); extern STATUS rd_L2DM(); extern STATUS rd_ICTC(); extern STATUS rd_THRM1(); extern STATUS rd_THRM2(); extern STATUS rd_THRM3(); extern STATUS rd_PID(); extern STATUS rd_SR(); extern STATUS rd_CR(); extern STATUS rd_UMMCR0(); extern STATUS rd_UPMC1(); extern STATUS rd_UPMC2(); extern STATUS rd_UMMCR1(); extern STATUS rd_UPMC3(); extern STATUS rd_UPMC4(); extern STATUS rd_MSSCR0(); extern STATUS rd_MSSCR1(); extern STATUS rd_PIR(); extern STATUS rd_VRSAVE(); extern STATUS rd_MMCR2(); extern STATUS rd_BAMR(); extern STATUS rd_UBAMR(); extern STATUS rd_UMMCR2(); extern STATUS rd_VSCR(); struct spr_tbl_str { char name[10]; /* Special register name */ char s_sprnum[6]; /* Register number with the form snnn */ char processors[6]; /* Processors being supported */ int reg; /* register number passed to (*func) */ STATUS (*func)(); /* function to read/write register */ char reg_des[50]; /* Register description */ }; /* The following table defines legal register names for all POWER */ /* PC processors. The second name is the register number with */ /* an "s" prefixed to it. If a register has two names (hid5, and */ /* dabr), it will have two entries, one for each name. */ /* The processors that support the register are defined in the */ /* processors field. For instance, mq is supported by PPC601, */ /* only and PPC601 is defined as '1' in the config.h file, thus */ /* the value of the "processors" field is initialized to '1'. */ /* The register field defined the register number being passed to */ /* the function defined in (*func)() field. The reg_des filed */ /* is a one-line description of the register. This field is used */ /* in the special register help commands "help spr_name" or "sx" */ /* */ /* To add a new register: */ /* 1. Increase the value of the MAX_SPECIAL_REG variable */ /* 2. Declare the existence of the register function i.e. */ /* "extern STATUS rd_MQ()" */ /* 3. Add an entry in the table below */ /* 4. Add the function that read/write the new register */ /* There is no need to modify any other code in DINK */ /* */ struct spr_tbl_str spr_tbl[MAX_SPECIAL_REG] = { /* 0 */ { "mq", "s0", "1", 0, rd_MQ, "Multiplication/Quotient Register"}, /* 1 */ { "xer", "s1", "134567", 0, rd_XER, "FXU Exception Register"}, /* 2 */ { "rtcu", "s4", "1", 0, rd_RTCU, "Multiplication/Quotient Register Upper"}, /* 3 */ { "rtcl", "s5", "1", 0, rd_RTCL, "Multiplication/Quotient Register Lower"}, /* 4 */ { "lr", "s8", "134567", 0, rd_LR, "Link Register"}, /* 5 */ { "ctr", "s9", "134567", 0, rd_CTR, "Counter Register" }, /* 6 */ { "dsisr", "s18", "134567", 0, rd_DSISR, "Data Storage Interrupt Status Register"}, /* 7 */ { "dar", "s19", "134567", 0, rd_DAR, "Data Address Register" }, /* 8 */ { "dec", "s22", "134567", 0, rd_DEC, "Decrementer" }, /* 9 */ { "sdr1", "s25", "134567", 0, rd_SDR1, "Storage Description Register 1" }, /* 10 */ { "srr0", "s26", "134567", 0, rd_SRR0, "Status Save/Restore Register 0" }, /* 11 */ { "srr1", "s27", "134567", 0, rd_SRR1, "Status Save/Restore Register 1" }, /* 12 */ { "sprg0", "s272", "134567", 0, rd_SPRG, "General Purpose SPR 0" }, /* 13 */ { "sprg1", "s273", "134567", 1, rd_SPRG, "General Purpose SPR 1" }, /* 14 */ { "sprg2", "s274", "134567", 2, rd_SPRG, "General Purpose SPR 2" }, /* 15 */ { "sprg3", "s275", "134567", 3, rd_SPRG, "General Purpose SPR 3" }, /* 16 */ { "asr", "s280", "134567", 0, rd_SPRG, "Address Space Register" }, /* 17 */ { "ear", "s282", "134567", 0, rd_EAR, "External Access Register" }, /* 18 */ { "tbl", "s284", "34567", 0, rd_TBL, "Time Base Lower Register"}, /* 19 */ { "tbu", "s285", "34567", 0, rd_TBU, "Time Base Upper Register" }, /* 20 */ { "pvr", "s287", "134567", 0, rd_PVR, "Processor Version Register" }, /* 21 */ { "bat0u", "s528", "1", 0, rd_BATU, "Block Addr. Translation Reg. 0 Upper"}, /* 22 */ { "bat0l", "s529", "1", 0, rd_BATL, "Block Addr. Translation Reg. 0 Lower"}, /* 23 */ { "ibat0u", "s528", "34567", 0, rd_IBATU, "IBlock Addr. Translation Reg. 0 Upper"}, /* 24 */ { "ibat0l", "s529", "34567", 0, rd_IBATL, "IBlock Addr. Translation Reg. 0 Lower"}, /* 25 */ { "bat1u", "s530", "1", 1, rd_BATU, "Block Addr. Translation Reg. 1 Upper"}, /* 26 */ { "bat1l", "s531", "1", 1, rd_BATL, "Block Addr. Translation Reg. 1 Lower"}, /* 27 */ { "ibat1u", "s530", "34567", 1, rd_IBATU, "IBlock Addr. Translation Reg. 1 Upper"}, /* 28 */ { "ibat1l", "s531", "34567", 1, rd_IBATL, "IBlock Addr. Translation Reg. 1 Lower"}, /* 29 */ { "bat2u", "s532", "1", 2, rd_BATU, "Block Addr. Translation Reg. 2 Upper"}, /* 30 */ { "bat2l", "s533", "1", 2, rd_BATL, "Block Addr. Translation Reg. 2 Lower"}, /* 31 */ { "ibat2u", "s532", "34567", 2, rd_IBATU, "IBlock Addr. Translation Reg. 2 Upper"}, /* 32 */ { "ibat2l", "s533", "34567", 2, rd_IBATL, "IBlock Addr. Translation Reg. 2 Lower"}, /* 33 */ { "bat3u", "s534", "1", 3, rd_BATU, "Block Addr. Translation Reg. 3 Upper"}, /* 34 */ { "bat3l", "s535", "1", 3, rd_BATL, "Block Addr. Translation Reg. 3 Lower"}, /* 35 */ { "ibat3u", "s534", "34567", 3, rd_IBATU, "Inst Addr. Translation Reg. 3 Upper"}, /* 36 */ { "ibat3l", "s535", "34567", 3, rd_IBATL, "Inst Addr. Translation Reg. 3 Lower"}, /* 37 */ { "dbat0u", "s536", "34567", 0, rd_DBATU, "Data Addr. Translation Reg. 0 Upper" }, /* 38 */ { "dbat0l", "s537", "34567", 0, rd_DBATL, "Data Addr. Translation Reg. 0 Lower" }, /* 39 */ { "dbat1u", "s538", "34567", 1, rd_DBATU, "Data Addr. Translation Reg. 1 Upper" }, /* 40 */ { "dbat1l", "s539", "34567", 1, rd_DBATL, "Data Addr. Translation Reg. 1 Lower" }, /* 41 */ { "dbat2u", "s540", "34567", 2, rd_DBATU, "Data Addr. Translation Reg. 2 Upper" }, /* 42 */ { "dbat2l", "s541", "34567", 2, rd_DBATL, "Data Addr. Translation Reg. 2 Lower" }, /* 43 */ { "dbat3u", "s542", "34567", 3, rd_DBATU, "Data Addr. Translation Reg. 3 Upper" }, /* 44 */ { "dbat3l", "s543", "34567", 3, rd_DBATL, "Data Addr. Translation Reg. 3 Lower" }, /* 45 */ { "ummcr0", "s936", "567", 0, rd_UMMCR0, "Monitor Control 0"}, /* 46 */ { "upmc1", "s937", "567", 0, rd_UPMC1, "Performance Monitor 1"}, /* 47 */ { "upmc2", "s938", "567", 0, rd_UPMC2, "Performance Monitor 2"}, /* 48 */ { "usia", "s939", "567", 0, rd_USIA, "Sampled Instruction Address"}, /* 49 */ { "ummcr1", "s940", "567", 0, rd_UMMCR1, "User Monitor Control 1"}, /* 50 */ { "upmc3", "s941", "567", 0, rd_UPMC3, "Performance Monitor 3"}, /* 51 */ { "upmc4", "s942", "567", 0, rd_UPMC4, "Performance Monitor 4"}, /* 52 */ { "mmcr0", "s952", "4567", 0, rd_MMCR0, "Monitor Mode Control Register 0" }, /* 53 */ { "pmc1", "s953", "4567", 0, rd_PMC1, "Performance Monitor Counter 1" }, /* 54 */ { "pmc2", "s954", "4567", 0, rd_PMC2, "Performance Monitor Counter 2" }, /* 55 */ { "sia", "s955", "4567", 0, rd_SIA, "Sampled Instruction Address" }, /* 56 */ { "mmcr1", "s956", "567", 0, rd_MMCR1, "Monitor Mode Control Register 1" }, /* 57 */ { "pmc3", "s957", "567", 0, rd_PMC3, "Performance Monitor Counter 3" }, /* 58 */ { "pmc4", "s958", "567", 0, rd_PMC4, "Performance Monitor Counter 4"}, /* 59 */ { "sda", "s959", "4", 0, rd_SDA, "Sampled Data Address" }, /* 60 */ { "dmiss", "s976", "3", 0, rd_DMISS, "D-TLB Miss Address" }, /* 61 */ { "dcmp", "s977", "3", 0, rd_DCMP, "D-TLB Miss Compare Value" }, /* 62 */ { "hash1", "s978", "3", 0, rd_HASH1, "1st PTEG Hashed Address" }, /* 63 */ { "hash2", "s979", "3", 2, rd_HASH2, "2nd PTEG Hashed Address" }, /* 64 */ { "imiss", "s980", "3", 0, rd_IMISS, "I-TLB Miss Address" }, /* 65 */ { "icmp", "s981", "3", 0, rd_ICMP, "I-TLB Miss Compare Value" }, /* 66 */ { "rpa", "s982", "3", 0, rd_RPA, "Real Page Address" }, /* 67 */ { "hid0", "s1008", "134567", 0, rd_HID0, "HW Implementation Dependent Reg. 0"}, /* 68 */ { "hid1", "s1009", "134567", 0, rd_HID1, "HW Implementation Dependent Reg. 1"}, /* 69 */ { "iabr", "s1010", "34567", 0, rd_IABR, "Instruction Address Breakpoint Reg."}, /* 70 */ { "dabr", "s1013", "4567", 0, rd_DABR, "Data Address Breakpoint Register"}, /* 71 */ { "l2cr", "s1017", "567", 0, rd_L2CR, "L2 Control"}, /* 72 */ { "ictc", "s1019", "567", 0, rd_ICTC, "Instruction Cache Throttle Control"}, /* 73 */ { "thrm1", "s1020", "567", 0, rd_THRM1, "Thermal Assist Unit 1"}, /* 74 */ { "thrm2", "s1021", "567", 0, rd_THRM2, "Thermal Assist Unit 2"}, /* 75 */ { "thrm3", "s1022", "567", 0, rd_THRM3, "Thermal Assist Unit 3"}, /* 76 */ { "pid", "s1023", "1467", 0, rd_PID, "Processor ID Register"}, /* 77 */ { "cr", "s1025", "134567", 0, rd_CR, "Condition Register"}, /* 78 */ { "fpscr", "s1026", "134567", 0, rd_FPSCR, "Floating-Point Status and Control Register"}, /* 79 */ { "msr", "s1027", "134567", 0, rd_MSR, "Machine State Register"}, /* 80 */ { "sr0", "sr0", "134567", 0, rd_SR, "Segment Register 0 Upper"}, /* 81 */ { "sr1", "sr1", "134567", 1, rd_SR, "Segment Register 1 Upper"}, /* 82 */ { "sr2", "sr2", "134567", 2, rd_SR, "Segment Register 2 Upper"}, /* 83 */ { "sr3", "sr3", "134567", 3, rd_SR, "Segment Register 3 Upper"}, /* 84 */ { "sr4", "sr4", "134567", 4, rd_SR, "Segment Register 4 Upper"}, /* 85 */ { "sr5", "sr5", "134567", 5, rd_SR, "Segment Register 5 Upper"}, /* 86 */ { "sr6", "sr6", "134567", 6, rd_SR, "Segment Register 6 Upper"}, /* 87 */ { "sr7", "sr7", "134567", 7, rd_SR, "Segment Register 7 Upper"}, /* 88 */ { "sr8", "sr8", "134567", 8, rd_SR, "Segment Register 8 Upper"}, /* 89 */ { "sr9", "sr9", "134567", 9, rd_SR, "Segment Register 9 Upper"}, /* 90 */ { "sr10", "sr10", "134567", 10, rd_SR, "Segment Register 10 Upper"}, /* 91 */ { "sr11", "sr11", "134567", 11, rd_SR, "Segment Register 11 Upper"}, /* 92 */ { "sr12", "sr12", "134567", 12, rd_SR, "Segment Register 12 Upper"}, /* 93 */ { "sr13", "sr13", "134567", 13, rd_SR, "Segment Register 13 Upper"}, /* 94 */ { "sr14", "sr14", "134567", 14, rd_SR, "Segment Register 14 Upper"}, /* 95 */ { "sr15", "sr15", "134567", 15, rd_SR, "Segment Register 15 Upper"}, /* 96 */ { "msscr0", "s1014", "67", 0, rd_MSSCR0, "MAX chip - Memory Subsystem Control Register"}, /* 97 */ { "msscr1", "s1015", "67", 0, rd_MSSCR1, "MAX chip - Memory Subsystem Control Register"}, /* 98 */ { "pir", "s1023", "67", 0, rd_PIR, "MAX chip - Processor ID Register"}, /* 99 */ { "vrsave", "s256", "67", 0, rd_VRSAVE, "MAX chip - VRsave Register"}, /* 100 */ { "mmcr2", "s944", "67", 0, rd_MMCR2, "MAX chip - Performance Monitor Control Register"}, /* 101 */ { "bamr", "s951", "67", 0, rd_BAMR, "MAX chip - Breakout Address Mask Register"}, /* 102 */ { "ubamr", "s935", "67", 0, rd_UBAMR, "MAX chip - Breakout Address Mask Register"}, /* 103 */ { "ummcr2", "s928", "67", 0, rd_UMMCR2, "MAX chip - Performance Monitor Control Register"}, /* 104 */ { "vscr", "s1028", "67", 0, rd_VSCR, "MAX chip - Vector Status and Control Register"}, /* 105*/ { "hid2", "s1011", "7", 0, rd_HID2, "HW Implementation Dependent Reg. 1"}, /* 106*/ { "l2dm", "s1016", "7", 0, rd_L2DM, "HW Implementation Dependent Reg. 1"}, /* 107*/ { "ibat4u", "s560", "7", 4, rd_IBATU, "Inst Addr. Translation Reg. 4 Upper"}, /* 108*/ { "ibat4l", "s561", "7", 4, rd_IBATL, "Inst Addr. Translation Reg. 4 Lower"}, /* 109*/ { "ibat5u", "s562", "7", 5, rd_IBATU, "Inst Addr. Translation Reg. 4 Upper"}, /* 110*/ { "ibat5l", "s563", "7", 5, rd_IBATL, "Inst Addr. Translation Reg. 4 Lower"}, /* 111*/ { "ibat6u", "s564", "7", 6, rd_IBATU, "Inst Addr. Translation Reg. 4 Upper"}, /* 112*/ { "ibat6l", "s565", "7", 6, rd_IBATL, "Inst Addr. Translation Reg. 4 Lower"}, /* 113*/ { "ibat7u", "s566", "7", 7, rd_IBATU, "Inst Addr. Translation Reg. 4 Upper"}, /* 114*/ { "ibat7l", "s567", "7", 7, rd_IBATL, "Inst Addr. Translation Reg. 4 Lower"}, /* 115*/ { "dbat4u", "s568", "7", 4, rd_DBATU, "Data Addr. Translation Reg. 4 Upper" }, /* 116*/ { "dbat4l", "s569", "7", 4, rd_DBATL, "Data Addr. Translation Reg. 4 Lower" }, /* 117*/ { "dbat5u", "s570", "7", 5, rd_DBATU, "Data Addr. Translation Reg. 4 Upper" }, /* 118*/ { "dbat5l", "s571", "7", 5, rd_DBATL, "Data Addr. Translation Reg. 4 Lower" }, /* 119*/ { "dbat6u", "s572", "7", 6, rd_DBATU, "Data Addr. Translation Reg. 4 Upper" }, /* 120*/ { "dbat6l", "s573", "7", 6, rd_DBATL, "Data Addr. Translation Reg. 4 Lower" }, /* 121*/ { "dbat7u", "s574", "7", 7, rd_DBATU, "Data Addr. Translation Reg. 4 Upper" }, /* 122*/ { "dbat7l", "s575", "7", 7, rd_DBATL, "Data Addr. Translation Reg. 4 Lower" }, };