#line 67 "except2.s"
.file "except2.s"
#line 27 "config.h" /* from dink_asm.h from except2.s */
 




 

 


 
#line 46
 
#line 100
 

 
#line 157
 
#line 27
 




 

 


 
#line 46
 
#line 100
 

 
#line 157
 
#line 2 "yellowknife.h" /* from dink_asm.h from except2.s */
 

 
#line 27 "config.h" /* from dink_asm.h from except2.s */
 




 

 


 
#line 46
 
#line 100
 

 
#line 157
 
#line 9 "yellowknife.h" /* from dink_asm.h from except2.s */
 

 

 
 
 
#line 48
 
#line 154
  

 
 
 
 

 
 
 
 
#line 176
 

 
#line 197
 
#line 234
 
#line 241
 
 
#line 258
       
       
 
#line 266
 
#line 280
 
#line 290
       
#line 297
 

 
#line 318
 
#line 34 "dink_asm.h" /* from except2.s */
.set dink_msr,0x3930 



.set rtoc,2; 

.set r0,0; .set r1,1; .set r2,2; .set r3,3; 
.set r4,4; .set r5,5; .set r6,6; .set r7,7; 
.set r8,8; .set r9,9; .set r10,10; .set r11,11;
.set r12,12; .set r13,13; .set r14,14; .set r15,15; 
.set r16,16; .set r17,17; .set r18,18; .set r19,19; 
.set r20,20; .set r21,21; .set r22,22; .set r23,23;
.set r24,24; .set r25,25; .set r26,26; .set r27,27; 
.set r28,28; .set r29,29; .set r30,30; .set r31,31;

.set f0,0; .set f1,1; .set f2,2; .set f3,3; 
.set f4,4; .set f5,5; .set f6,6; .set f7,7; 
.set f8,8; .set f9,9; .set f10,10; .set f11,11;
.set f12,12; .set f13,13; .set f14,14; .set f15,15; 
.set f16,16; .set f17,17; .set f18,18; .set f19,19; 
.set f20,20; .set f21,21; .set f22,22; .set f23,23;
.set f24,24; .set f25,25; .set f26,26; .set f27,27; 
.set f28,28; .set f29,29; .set f30,30; .set f31,31;

.set v0,0; .set v1,1; .set v2,2; .set v3,3; 
.set v4,4; .set v5,5; .set v6,6; .set v7,7; 
.set v8,8; .set v9,9; .set v10,10; .set v11,11;
.set v12,12; .set v13,13; .set v14,14; .set v15,15; 
.set v16,16; .set v17,17; .set v18,18; .set v19,19; 
.set v20,20; .set v21,21; .set v22,22; .set v23,23;
.set v24,24; .set v25,25; .set v26,26; .set v27,27; 
.set v28,28; .set v29,29; .set v30,30; .set v31,31;

.set xer,1;  .set lr,8;  .set ctr,9;  .set dsisr,18; 
.set dar,19;  .set dec_r,22;  .set sdr1,25; .set srr0,26;
.set srr1,27; .set ear,282; .set pvr,287; 

.set sprg0,272; .set sprg1,273; 
.set sprg2,274; .set sprg3,275; 

.set cr2,2;

.set sr0,0; .set sr1,1; .set sr2,2; .set sr3,3; 
.set sr4,4; .set sr5,5; .set sr6,6; .set sr7,7; 
.set sr8,8; .set sr9,9; .set sr10,10;.set sr11,11;
.set sr12,12;.set sr13,13;.set sr14,14;.set sr15,15;



 
#line 94
 

.set dmiss,976; .set dcmp,977;
.set hash1,978; .set hash2,979;
.set imiss,980; .set icmp,981;
.set rpa,982;


 

 

 
#line 122
 
.set  mmcr1,956;
.set  pmc3,957; .set pmc4,958;
.set thrm1,1020; .set  thrm2,1021;
.set thrm3,1022; .set ictc,1019;
.set  l2cr,1017; .set upmc1,937;
.set upmc2,938; .set upmc3,941;
.set upmc4,942; .set usia,939;
.set ummcr0,936; .set ummcr1,940;

                                 


                                                                 


.set  vrsave,256; .set  ubamr, 935;
.set  ummcr2,928; .set  bamr, 951;
.set mmcr2,944; .set msscr1, 1015;
.set  msscr0,1014; 
.set dL1HWf,0x0080 
.set C_dL1HWf,0xff7f 
                                                                 


 

.set tbl,284; .set tbu,285;

.set ibat0u,528;  .set ibat0l,529; 
.set ibat1u,530; .set ibat1l,531;
.set ibat2u,532; .set ibat2l,533; 
.set ibat3u,534; .set ibat3l,535; 
.set dbat0u,536;  .set dbat0l,537; 
.set dbat1u,538; .set dbat1l,539;
.set dbat2u,540; .set dbat2l,541; 
.set dbat3u,542; .set dbat3l,543; 

.set mmcr0,952;
.set pmc1,953; .set pmc2,954;
.set sia,955; .set sda,959;

.set hid0,1008; .set hid1,1009; 
.set dabr,1013; .set iabr,1010;
.set pir,1023;

 

 

.set ibat4u,560;  .set ibat4l,561; 
.set ibat5u,562; .set ibat5l,563;
.set ibat6u,564; .set ibat6l,565; 
.set ibat7u,566; .set ibat7l,567; 
.set dbat4u,568;  .set dbat4l,569; 
.set dbat5u,570; .set dbat5l,571;
.set dbat6u,572; .set dbat6l,573; 
.set dbat7u,574; .set dbat7l,575; 
#line 80 "except2.s"
 
.extern exception_return
.extern save_to_dink
.extern save_to_user
.extern deal_w_exception
.extern restore_to_dink
.extern restore_partial_dink
.extern main
.extern KahluaInit
.extern epic_exception

.equ     PCSRBARVAL, 0xfc10
.equ     PCSRBAR, 0x0014
.equ     PCICMD,  0x0004
.equ     OMBAR,   0x0300
.equ     OTWR,    0x0308
.equ     LMBAR,   0x0010
.equ     ITWR,    0x0310
#line 108
 
#line 118
 .text
 .align 2
 .space (0x100) 
 
 b system_reset 

 .space (0x100 - 0x4) 


 
EH200S:

 .set mcval,0x200




 mtspr sprg3,r3
 mtspr sprg2,r4

 addis r3,0,0 
 ori r3,r3,mcval 

 lis r4, ex_type@h 
 ori r4,r4, ex_type@l 

 stwx r3,0,r4 
 mfsrr0 r3 

 lis r4, ex_addr@h 
 ori r4,r4, ex_addr@l 
 stwx r3,0,r4 
 b handle_ex 

EH200E:

 .space (0x100 - (EH200E-EH200S)) 



 .set daval,0x300




EH300S:




 mtspr sprg3,r3
 mtspr sprg2,r4

 addis r3,0,0 
 ori r3,r3,daval 

 lis r4, ex_type@h 
 ori r4,r4, ex_type@l 

 stwx r3,0,r4 
 mfsrr0 r3 

 lis r4, ex_addr@h 
 ori r4,r4, ex_addr@l 
 stwx r3,0,r4 

 b handle_ex 

EH300E:

 .space EH300S-EH300E + 0x100 



 .set iaval,0x400




EH400S:




 mtspr sprg3,r3
 mtspr sprg2,r4

 addis r3,0,0 
 ori r3,r3,iaval 

 lis r4, ex_type@h 
 ori r4,r4, ex_type@l 

 stwx r3,0,r4 
 mfsrr0 r3 

 lis r4, ex_addr@h 
 ori r4,r4, ex_addr@l 
 stwx r3,0,r4 

 b handle_ex 

EH400E:

 .space EH400S-EH400E + 0x100 



 .set eival,0x500




EH500S:




 mtspr sprg3,r3
 mtspr sprg2,r4

 mfspr r3,22 

 lis r4, decrementer_value@h 
 ori r4,r4, decrementer_value@l 

 stwx r3,0,r4 

 addis r3,0,0 
 ori r3,r3,eival 

 lis r4, ex_type@h 
 ori r4,r4, ex_type@l 

 stwx r3,0,r4 
 mfsrr0 r3 

 lis r4, ex_addr@h 
 ori r4,r4, ex_addr@l 
 stwx r3,0,r4 

 b handle_ex 

EH500E:

 .space EH500S-EH500E + 0x100 

 .set amval, 0x600



EH600S:




 mtspr sprg3,r3
 mtspr sprg2,r4


 addis r3,0,0 
 ori r3,r3,amval 

 lis r4, ex_type@h 
 ori r4,r4, ex_type@l 

 stwx r3,0,r4 
 mfsrr0 r3 

 lis r4, ex_addr@h 
 ori r4,r4, ex_addr@l 
 stwx r3,0,r4 

 b handle_ex 

EH600E:

 .space EH600S-EH600E + 0x100 



 .set pgval,0x700




EH700S:




 mtspr sprg3,r3
 mtspr sprg2,r4


 addis r3,0,0 
 ori r3,r3,pgval 

 lis r4, ex_type@h 
 ori r4,r4, ex_type@l 

 stwx r3,0,r4 
 mfsrr0 r3 
 lis r4, ex_addr@h 
 ori r4,r4, ex_addr@l 
 stwx r3,0,r4 

 b handle_ex 

EH700E:

 .space EH700S-EH700E + 0x100 



 .set fpval,0x800




EH800S:




 mtspr sprg3,r3
 mtspr sprg2,r4


 addis r3,0,0 
 ori r3,r3,fpval 

 lis r4, ex_type@h 
 ori r4,r4, ex_type@l 

 stwx r3,0,r4 
 mfsrr0 r3 

 lis r4, ex_addr@h 
 ori r4,r4, ex_addr@l 
 stwx r3,0,r4 

 b handle_ex 

EH800E:

 .space EH800S-EH800E + 0x100 



 .set dmval,0x900




EH900S:




 mtspr sprg3,r3
 mtspr sprg2,r4


 addis r3,0,0 
 ori r3,r3,dmval 

 lis r4, ex_type@h 
 ori r4,r4, ex_type@l 

 stwx r3,0,r4 
 mfsrr0 r3 

 lis r4, ex_addr@h 
 ori r4,r4, ex_addr@l 
 stwx r3,0,r4 

 b handle_ex 

EH900E:

 .space EH900S-EH900E + 0x100 



 .set ioval,0xA00




EHA00S:




 mtspr sprg3,r3
 mtspr sprg2,r4


 addis r3,0,0 
 ori r3,r3,ioval 

 lis r4, ex_type@h 
 ori r4,r4, ex_type@l 

 stwx r3,0,r4 
 mfsrr0 r3 

 lis r4, ex_addr@h 
 ori r4,r4, ex_addr@l 
 stwx r3,0,r4 

 b handle_ex 

EHA00E:

 .space EHA00S-EHA00E + 0x100 

 .space 256 



 .set scval,0xC00




EHC00S:




 mtspr sprg3,r3
 mtspr sprg2,r4


 addis r3,0,0 
 ori r3,r3,scval 

 lis r4, ex_type@h 
 ori r4,r4, ex_type@l 

 stwx r3,0,r4 
 mfsrr0 r3 

 lis r4, ex_addr@h 
 ori r4,r4, ex_addr@l 
 stwx r3,0,r4 

 b handle_ex 

EHC00E:

 .space EHC00S - EHC00E + 0x100 



 .set trval,0xD00




EHD00S:




 mtspr sprg3,r3
 mtspr sprg2,r4


 addis r3,0,0 
 ori r3,r3,trval 

 lis r4, ex_type@h 
 ori r4,r4, ex_type@l 

 stwx r3,0,r4 
 mfsrr0 r3 

 lis r4, ex_addr@h 
 ori r4,r4, ex_addr@l 
 stwx r3,0,r4 

 b handle_ex 

EHD00E:

 .space EHD00S-EHD00E + 0x100 



 .set fpaval,0xE00




EHE00S:




 mtspr sprg3,r3
 mtspr sprg2,r4


 addis r3,0,0 
 ori r3,r3,fpaval 

 lis r4, ex_type@h 
 ori r4,r4, ex_type@l 

 stwx r3,0,r4 
 mfsrr0 r3 

 lis r4, ex_addr@h 
 ori r4,r4, ex_addr@l 
 stwx r3,0,r4 

 b handle_ex 

EHE00E:

 .space EHE00S-EHE00E + 0x100 
 


 .set pmval,0xF00




EHF00S:




 mtspr sprg3,r3
 mtspr sprg2,r4


 addis r3,0,0 
 ori r3,r3,pmval 


 b EH2SM 

EHF00E:

 .space EHF00S-EHF00E + 0x020 




 .set aival,0xF20




EHF20S:




 mtspr sprg3,r3
 mtspr sprg2,r4


 addis r3,0,0 
 ori r3,r3,aival 

EH2SM: 
 

 lis r4, ex_type@h 
 ori r4,r4, ex_type@l 

 stwx r3,0,r4 
 mfsrr0 r3 

 lis r4, ex_addr@h 
 ori r4,r4, ex_addr@l 
 stwx r3,0,r4 

 b handle_ex 

EHF20E:

 .space EHF00S-EHF20E + 0x100 



 .set itval,0x1000




EH1000S:




 mtspr sprg3,r3
 mtspr sprg2,r4


 addis r3,0,0 
 ori r3,r3,itval 

 lis r4, ex_type@h 
 ori r4,r4, ex_type@l 

 stwx r3,0,r4 
 mfsrr0 r3 

 lis r4, ex_addr@h 
 ori r4,r4, ex_addr@l 
 stwx r3,0,r4 

 b handle_ex 

EH1000E:

 .space EH1000S-EH1000E + 0x100 




 .set dlval,0x1100




EH1100S:




 mtspr sprg3,r3
 mtspr sprg2,r4


 addis r3,0,0 
 ori r3,r3,dlval 

 lis r4, ex_type@h 
 ori r4,r4, ex_type@l 

 stwx r3,0,r4 
 mfsrr0 r3 

 lis r4, ex_addr@h 
 ori r4,r4, ex_addr@l 
 stwx r3,0,r4 

 b handle_ex 

EH1100E:

 .space EH1100S-EH1100E + 0x100 



 .set dsval,0x1200




EH1200S:




 mtspr sprg3,r3
 mtspr sprg2,r4


 addis r3,0,0 
 ori r3,r3,dsval 

 lis r4, ex_type@h 
 ori r4,r4, ex_type@l 

 stwx r3,0,r4 
 mfsrr0 r3 

 lis r4, ex_addr@h 
 ori r4,r4, ex_addr@l 
 stwx r3,0,r4 

 b handle_ex 

EH1200E:

 .space EH1200S-EH1200E + 0x100 




 .set ibval,0x1300




EH1300S:




 mtspr sprg3,r3
 mtspr sprg2,r4


 addis r3,0,0 
 ori r3,r3,ibval 

 lis r4, ex_type@h 
 ori r4,r4, ex_type@l 

 stwx r3,0,r4 
 mfsrr0 r3 

 lis r4, ex_addr@h 
 ori r4,r4, ex_addr@l 
 stwx r3,0,r4 

 b handle_ex 

EH1300E:

 .space EH1300S-EH1300E + 0x100 



 .set smval,0x1400




EH1400S:




 mtspr sprg3,r3
 mtspr sprg2,r4


 addis r3,0,0 
 ori r3,r3,smval 

 lis r4, ex_type@h 
 ori r4,r4, ex_type@l 

 stwx r3,0,r4 
 mfsrr0 r3 

 lis r4, ex_addr@h 
 ori r4,r4, ex_addr@l 
 stwx r3,0,r4 

 b handle_ex 

EH1400E:

 .space EH1400S-EH1400E + 0x100 




.space 256


 


 .set jmddval,0x1600




EH1600S:




 mtspr sprg3,r3
 mtspr sprg2,r4


 addis r3,0,0 
 ori r3,r3,jmddval 

 lis r4, ex_type@h 
 ori r4,r4, ex_type@l 

 stwx r3,0,r4 
 mfsrr0 r3 

 lis r4, ex_addr@h 
 ori r4,r4, ex_addr@l 
 stwx r3,0,r4 

 b handle_ex 

EH1600E:

 .space EH1600S-EH1600E + 0x100 


.space 256



.space 256



.space 256


 
.space 256


 
.space 256


 
.space 256


 
.space 256


 
.space 256



.space 256



 .set rtval,8192




EH2000S:




 mtspr sprg3,r3
 mtspr sprg2,r4

 
 addis r3,0,0 
 ori r3,r3,rtval 

 lis r4, ex_type@h 
 ori r4,r4, ex_type@l 

 stwx r3,0,r4 
 mfsrr0 r3 

 lis r4, ex_addr@h 
 ori r4,r4, ex_addr@l 
 stwx r3,0,r4 

 b handle_ex 

EH2000E:

 .space EH2000S-EH2000E + 0x100 

 .space 0x1000 
 
#line 912
.text 
.align 2
.global handle_ex

handle_ex: 
 
 .set user_code_value,1 
 
 .set duart_buf_check,1 
 
#line 965
 mfspr r4,268
 lis r3,timebase_register_l@h
 ori r3,r3,timebase_register_l@l
 stwx r4,0,r3
 sync

 mfspr r4,269
 lis r3,timebase_register_u@h
 ori r3,r3,timebase_register_u@l
 stwx r4,0,r3
 sync
 



 mfspr r4,hid0
 lis r3,current_hid0@h
 ori r3,r3,current_hid0@l
 stwx r4,0,r3
 sync

 mfspr r4,srr1 
 lis r3,current_msr@h 
 ori r3,r3,current_msr@l
 stwx r4,0,r3
 sync

 mfspr r4,srr0 
 lis r3,current_srr0@h 
 ori r3,r3,current_srr0@l 
 stw r4,0(r3)
 sync

 mfspr r4,lr
 lis r3,current_lr@h
 ori r3,r3,current_lr@l
 stwx r4,0,r3
 sync

 mfcr r4
 lis r3,current_cr@h
 ori r3,r3,current_cr@l
 stwx r4,0,r3
 sync

 mfspr r4,sprg2 
 lis r3,current_r4@h
 ori r3,r3,current_r4@l
 stwx r4,0,r3
 sync

 mfspr r4,sprg3
 lis r3,current_r3@h
 ori r3,r3,current_r3@l
 stwx r4,0,r3
 sync
 
 lis r3,current_r5@h
 ori r3,r3,current_r5@l
 stwx r5,0,r3
 sync



 mfspr r4,sprg0
 lis r3,temp_sprg0@h
 ori r3,r3,temp_sprg0@l
 stw r4,0(r3)
 sync

 mfspr r4,sprg1
 lis r3,temp_sprg1@h
 ori r3,r3,temp_sprg1@l
 stw r4,0(r3)
 sync
 
#line 1051
 lis r3,0x0000 
 ori r3,r3,eival 
 

 lis r4, ex_type@h 
 ori r4,r4, ex_type@l 
     lwz r4,0(r4) 
 
     cmpw cr0,r3,r4 
     bne cr0,cont_handle_ex 


 lis r4,target_type@h 
 ori  r4,r4,target_type@l 
 lwz r3,0(r4)
 
 
 lis r4,0x0004       
 ori r4,r4,0x1057       
 cmpw  cr0, r3, r4
 beq cr0,epic_launch 

 lis r4,0x0003       
 ori r4,r4,0x1057       
 cmpw  cr0, r3, r4
 bne cr0,cont_handle_ex 


epic_launch:
 b epic_exception 
#line 1087
cont_handle_ex:
#line 1095
 lis r3,in_which_code@h
 ori r3,r3,in_which_code@l
 lwz r3,0(r3)
 cmpi 0,0,r3,0x0 
 beq cr0,dinkException 
#line 1108
setupflush:

 sync
 isync

flushfunction:
 lis r3,0x0000 
 lis r4,0x0020 
flushhead:
 cmpw r3,r4 
 bge flushdone 
 lwz r5,0(r3) 
 addi r3,r3,0x20 
 b flushhead
flushdone:
 
 sync
 isync

 lis   r4,0x8000
 ori   r4,r4,0xcc00 
 mtspr hid0,r4
 isync
 sync

 lis   r4,0x8000
 ori   r4,r4,0xc000 
 mtspr hid0,r4
 isync
 sync

 lis   r4,0x8000
 ori   r4,r4,0x0000 
 mtspr hid0,r4
 isync
 sync
#line 1160
 mfmsr r4
 ori r4,r4,0x2000 
 mtmsr r4
 
 bl save_to_user 
 
 
 
 
 



 lis r3,in_which_code@h 
 ori r3,r3,in_which_code@l
 xor r4,r4,r4 
 stw r4,0(r3) 

 bl restore_partial_dink
 ori 0,0,0
 
 
 
 
 
 

 
 bl deal_w_exception 
 ori 0,0,0 

 bl restore_to_dink 
 ori 0,0,0




 ori 0,0,0
 b exception_return 
#line 1209
dinkException:


 lis r3,0x0000 
 lis r4,0x0020 
flushhead2:
 cmpw r3,r4 
 bge flushdone2 
 lwz r5,0(r3) 
 addi r3,r3,0x20 
 b flushhead2
flushdone2:

 lis r3,0x0000 
 ori r3,r3,0x3930 
 mtmsr r3 
 
 bl save_to_dink 

 bl deal_w_exception 
 
 bl restore_to_dink 

 mfspr r1,sprg1 
 mfspr r2,sprg2 
 
 lis r3,current_hid0@h 
 ori r3,r3,current_hid0@l
 lwz r3,0(r3)
 mtspr hid0,r3

 lis r3,current_msr@h
 ori r3,r3,current_msr@l
 lwz r3,0(r3)
 mtspr srr1,r3

 lis r3,current_srr0@h
 ori r3,r3,current_srr0@l
 lwz r3,0(r3)
 mtspr srr0,r3

 lis r3,current_lr@h
 ori r3,r3,current_lr@l
 lwz r3,0(r3)
 mtlr r3

 lis r3,current_cr@h
 ori r3,r3,current_cr@l
 lwz r3,0(r3)
 mtcr r3

 lis r3,temp_sprg0@h
 ori r3,r3,temp_sprg0@l
 lwz r3,0(r3)
 mtspr sprg0,r3

 lis r3,temp_sprg1@h
 ori r3,r3,temp_sprg1@l
 lwz r3,0(r3)
 mtspr sprg1,r3

 lis r3,current_r5@h
 ori r3,r3,current_r5@l
 lwz r5,0(r3)
 
 lis r3,current_r3@h
 ori r3,r3,current_r3@l
 lwz r3,0(r3)

 lis r4,current_r4@h
 ori r4,r4,current_r4@l
 lwz r4,0(r4)

 rfi 
#line 1293
.text
.align 2
.global system_reset
system_reset:
 
 addis r0,0,0x0000 
 mfmsr r3 
 addis r4,0,0xffff
 ori r4,r4,0xffcf
 and r3,r3,r4
 mtmsr r3
 isync
 sync 
#line 1315
        addis   r5, r0, 0xfec0        
        addis   r6, r0, 0xfee0        

        addis   r8, r0, 0xfe00       
 addis   r9, r0, 0x0           

 mtspr sprg1, r8 
 mtspr sprg2, r5 
 mtspr sprg3, r6 

 addis r3, r0, 0x8000   
 stwbrx r3, 0, (r5)
 sync
 lwbrx r3, 0, (r6) 

 addis r4, r0, 0x0003       
 ori r4, r4, 0x1057       
 cmp 0, 0, r3, r4
 bne cr0, TestYKMapB
 bl KahluaInit
 b do_mmu_setup




TestYKMapB:

        addis   r4, r0, 0x0002       
        ori     r4, r4, 0x1057
        cmp     0,  0, r3, r4
        beq     cr0, start_init 

        addis   r4, r0, 0x0004       
        ori     r4, r4, 0x1057
        cmp     0,  0, r3, r4
 bne cr0, tryprep 
 bl Mpc107Init 
 b do_mmu_setup




tryprep:
        addis   r5, r0, 0x8000        
        ori     r5, r5, 0x0cf8        
        addis   r6, r0, 0x8000        
        ori     r6, r6, 0x0cfc
        addis   r8, r0, 0x8000       
 addis  r9, r0, 0x1           

 mtspr sprg1, r8
 mtspr sprg2, r5
 mtspr sprg3, r6

        addis   r3, r0, 0x8000   
        stwbrx  r3, 0, (r5) 
 sync
        lwbrx   r3, 0, (r6) 
#line 1378
        addis   r4, r0, 0x0003       
        ori     r4, r4, 0x1057       
        cmp     0,  0, r3, r4 
        bne     cr0, TestYKMapA 
 bl KahluaInit
 b do_mmu_setup

TestYKMapA:
        addis   r4, r0, 0x0002       
        ori     r4, r4, 0x1057
        cmp     0,  0, r3, r4
        beq     cr0, start_init 

        addis   r4, r0, 0x0004       
        ori     r4, r4, 0x1057
        cmp     0,  0, r3, r4
 bne cr0, tryexcimer 
 bl Mpc107Init 
 b do_mmu_setup
#line 1405
tryexcimer:
        addis   r5, r0, 0x4050
        addis   r4, r0, 0x0100
        lwz     r3, 0(r5) 
 andis. r3,r3,0xff00 
        cmp     0,  0, r3, r4 
        beq     cr0, excimer_init 




cant_identify:
 lis r0,0xDEAD 
 ori r0,r0,0x001D 
 b cant_identify
#line 1426
.global start_init
start_init:

 mtspr sprg1, r8 
        mtspr   sprg2, r5 
        mtspr   sprg3, r6 
 
 addis  r3, r0, 0x8000
 ori    r3, r3, 0x00a8       
  stwbrx r3, 0,r5 
 sync
 lwbrx  r4, 0,r6 
  sync
 addis  r3,r0,0x0010 
 and    r4,r3,r4
 cmp    0, 0, r3, r4 
 beq    cr0, X2_START 
 
 
 
#line 1453
 addis r3,r0,0x0
 addi r3,r0,0x1
 mtspr sprg0,r3
 addi   r10, r0, 1
 addis  r3,r0,0x8000   
 ori    r3,r3,0x00A8
 stwbrx r3,0,r5
 addis  r4,r0,0x3f04
 or     r4,r4,r9
 ori    r4,r4,0x1800 
 stwbrx r4,0,r6
 sync
 lwbrx  r4,0,r6
 sync

 addis  r3,r0,0x8000   
 ori    r3,r3,0x00AC
 stwbrx r3,0,r5
 addis  r4,r0,0x0047     
 oris   r4,r4,0x0400 
 ori    r4,r4,0x0215
 stwbrx r4,0,r6
 sync
 lwbrx  r4,0,r6
 sync

 addis  r3,r0,0x8000   
 ori    r3,r3,0x00F0
 stwbrx r3,0,r5
 addis  r4,r0,0xFFA4
 ori    r4,r4,0xFFFF
 stwbrx r4,0,r6
 sync
 lwbrx  r4,0,r6
 sync

 addis  r3,r0,0x8000   
 ori    r3,r3,0x00F4
 stwbrx r3,0,r5
 addis  r4,r0,0x0000
 ori    r4,r4,0x0C34
 stwbrx r4,0,r6
 sync
 lwbrx  r4,0,r6
 sync

 addis  r3,r0,0x8000   
 ori    r3,r3,0x00F8
 stwbrx r3,0,r5
 addis  r4,r0,0xF830
 ori    r4,r4,0x0000
 stwbrx r4,0,r6
 sync
 lwbrx  r4,0,r6
 sync

 addis  r3,r0,0x8000   
 ori    r3,r3,0x00FC
 stwbrx r3,0,r5
 addis  r4,r0,0x2530
 ori    r4,r4,0x2244
 stwbrx r4,0,r6
 sync
#line 1528
 addis  r3,r0,0x8000   
 ori    r3,r3,0x0080
 stwbrx r3,0,r5

 addis  r4,r0,0x3020
 ori    r4,r4,0x1000
 stwbrx r4,0,r6

 addis  r3,r0,0x8000   
 ori    r3,r3,0x0084
 stwbrx r3,0,r5

 addis  r4,r0,0x7060
 ori    r4,r4,0x5040
 stwbrx r4,0,r6

 addis  r3,r0,0x8000   
 ori    r3,r3,0x0088
 stwbrx r3,0,r5

 addis  r4,r0,0x0000
 ori    r4,r4,0x0000
 stwbrx r4,0,r6

 addis  r3,r0,0x8000   
 ori    r3,r3,0x008c
 stwbrx r3,0,r5

 addis  r4,r0,0x0000
 ori    r4,r4,0x0000
 stwbrx r4,0,r6
#line 1567
 addis  r3,r0,0x8000   
 ori    r3,r3,0x0090
 stwbrx r3,0,r5

 addis  r4,r0,0x3f2f
 ori    r4,r4,0x1f0f 
 
 stwbrx r4,0,r6

 addis  r3,r0,0x8000   
 ori    r3,r3,0x0094
 stwbrx r3,0,r5

 addis  r4,r0,0x7f6f
 ori    r4,r4,0x5f4f
 stwbrx r4,0,r6

 addis  r3,r0,0x8000   
 ori    r3,r3,0x0098
 stwbrx r3,0,r5

 addis  r4,r0,0x0000
 ori    r4,r4,0x0000
 stwbrx r4,0,r6

 addis  r3,r0,0x8000   
 ori    r3,r3,0x009c
 stwbrx r3,0,r5

 addis  r4,r0,0x0000
 ori    r4,r4,0x0000
 stwbrx r4,0,r6
#line 1606
 addis   r3,r0,0x8000   
 ori     r3,r3,0xa0
 stwbrx  r3,0,r5
 sync

 li r4,0x03 
     stb     r4, 0(r6)
#line 1620
 addis   r3,r0,0x8000   
 ori     r3,r3,0xa3
 stwbrx  r3,0,r5
 sync

 li      r4, 0x32 
 stb     r4, 3(r6) 


 lwbrx  r4,0,r6
 
 sync



 li r4,0x3800
 mtctr   r4
X4wait200us:
 bdnz X4wait200us




 addis  r3,r0,0x8000   
 ori    r3,r3,0x00f0
 stwbrx r3,0,r5
 sync
 lwbrx  r4,0,r6 
 addis  r3,r0,0x0008
 ori    r3,r3,0x0000
 or     r4,r4,r3 
 stwbrx  r4,0,r6
 sync
 lwbrx  r4,0,r6 




 li r4, 8000
 mtctr r4
X4wait8ref:
 bdnz X4wait8ref

 sync

 b do_mmu_setup 


 
X2_START:
 addis r3,r0,0x0
 mtspr sprg0,r3
 addi    r10, r0, 0
 addis r3,r0,0x8000
 ori r3,r3,0x0080
 addis r4,r0,0x0000
 ori r4,r4,0x0000
 stwbrx r3,0,(r5)
 stwbrx r4,0,(r6)
 
 addis r3,r0,0x8000
 ori r3,r3,0x0090
 addis r4,r0,0x0000
 ori r4,r4,0x0007
 stwbrx r3,0,(r5)
 stwbrx r4,0,(r6)
 
 addis r3,r0,0x8000
 ori r3,r3,0x00a0
 addi r4,r0,0x01
 stwbrx r3,0,(r5)
 stb r4,0(r6)

 sync
 

 addis r3,r0,0x8000
        ori     r3,r3,0x00a8
        addis   r4,r0,0x3f90
 or r4,r4,r9
        ori     r4,r4,0x0a18

        stwbrx  r3,0,(r5)
        stwbrx  r4,0,(r6)

        sync

 addis r3,r0,0x8000
        ori     r3,r3,0x00ac
        addis   r4,r0,0x000c
        ori     r4,r4,0x060c
        stwbrx  r3,0,(r5)
        stwbrx  r4,0,(r6)

        sync
 

 
 
 
 
 
 

 

 
 
 
 
 
 
 
 
 
 addis r3,r0,0x8000
 ori r3,r3,0x00F4
 addis r4,r0,0x0000
 ori r4,r4,0x07F7
 stwbrx r3,0,(r5)
 stwbrx r4,0,(r6)
 
 addis r3,r0,0x8000
 ori r3,r3,0x00F8

 addis r4,r0,0x0002 

 ori r4,r4,0x2293 
 stwbrx r3,0, (r5)
 stwbrx r4,0, (r6)
 
 addis r3,r0,0x8000
 ori r3,r3,0x00FC
 addis r4,r0,0x0000
 ori r4,r4,0x0000
 stwbrx r3,0,(r5)
 stwbrx r4,0,(r6)
 
 addis r3,r0,0x8000
 ori r3,r3,0x00F0
 addis r4,r0,0xFF8A
 ori r4,r4,0x0001
 stwbrx r3,0,(r5)
 stwbrx r4,0,(r6)
 
 sync

 b do_mmu_setup 
#line 1773
.global excimer_init
excimer_init:
        addis   r8, r0, 0x4040 
 mtspr sprg1,r8

 addis r3,0,0x0
 ori r3,r3,0x2
 mtspr sprg0,r3 

do_mmu_setup:
 bl mmu_setup 
 sync




 mfmsr r3
 ori r3,r3,0x0030
 mtmsr r3
 isync
 sync 
#line 1801
 bl  invalidate_and_enable_L1_icache


.global copy_flash_to_ram
copy_flash_to_ram: 
 addis r3,0,0 
 addis r4,0,0xFFC0     
 lis r6,0x8 

lp1: lwzx r5,0,r4 
 stwx r5,0,r3 
 sync
 lwzx r7,0,r3 
 cmp 0,0,r7,r5 
 bne error_dram_init

 addi r4,r4,4 
 addi r3,r3,4
 addic. r6,r6,-4 
 bgt lp1
 
 eieio
 sync



 
 addis r3,0,0 
 addis r4,0,0xFFC0     
 lis r6,0x8 

 add r8,r0,r4

verlp: lwzx r5,0,r4 
 lwzx r7,0,r3 

 lwzx r9,0,r8 

 cmp 0,0,r7,r5 
 bne error_dram_init

 addi r4,r4,4 
 addi r3,r3,4
 addic. r6,r6,-4 
 bgt verlp
 
 eieio
 sync

 
#line 1856
 bl global_L2backside_invalidate

 



 bl  invalidate_and_enable_L1_dcache
#line 1873
 
 
 
#line 1889
 
 mfmsr r3
 andi. r3,r3,0x2000 
 beq no_float 

 lis r3,float_0@h
 ori r3,r3,float_0@l

 lfd f0,0(r3) 
 lfd f1,0(r3)
 lfd f2,0(r3)
 lfd f3,0(r3)
 lfd f4,0(r3)
 lfd f5,0(r3)
 lfd f6,0(r3)
 lfd f7,0(r3)
 lfd f8,0(r3)
 lfd f9,0(r3)
 lfd f10,0(r3)
 lfd f11,0(r3)
 lfd f12,0(r3)
 lfd f13,0(r3)
 lfd f14,0(r3)
 lfd f15,0(r3)
 lfd f16,0(r3)
 lfd f17,0(r3)
 lfd f18,0(r3)
 lfd f19,0(r3)
 lfd f20,0(r3)
 lfd f21,0(r3)
 lfd f22,0(r3)
 lfd f23,0(r3)
 lfd f24,0(r3)
 lfd f25,0(r3)
 lfd f26,0(r3)
 lfd f27,0(r3)
 lfd f28,0(r3)
 lfd f29,0(r3)
 lfd f30,0(r3)
 lfd f31,0(r3)

no_float:
#line 1937
.global init_globals
init_globals: 
        mfspr   r8, sprg1 
 lis r3,io_base_addr@h 
 ori r3,r3,io_base_addr@l 
 stw r8,0(r3)

 lis r3,in_which_code@h 
 ori r3,r3,in_which_code@l

 addis r4,0,0 
 stwx r4,0,r3 

        lis     r3,config_addr@h 
        ori     r3,r3,config_addr@l
        mfspr   r5, sprg2 
        stwx    r5,0,r3 

        lis     r3,config_data@h 
        ori     r3,r3,config_data@l
        mfspr   r5, sprg3 
        stwx    r5,0,r3 
#line 1966
 mfspr r5, sprg0
        lis     r3,board_type@h 
        ori     r3,r3,board_type@l
        stwx    r5,0,r3 

        cmpi    0,0,r5,0x2 
        beq     init_global_cont 
#line 1979
        mfspr   r5, sprg2 
        mfspr   r6, sprg3 

        lis     r7, 0x8000
        stwbrx  r7, 0, (r5)
        sync
        lwbrx   r4, 0, (r6)

        lis     r3, 0x0003       
        ori     r3, r3, 0x1057       
        cmp 0, 0, r3, r4


        lis     r3,target_type@h
        ori     r3,r3,target_type@l
        stwx    r4,0,r3 

        lis     r7, 0x8000
        ori     r7, r7,0x0008 
        stwbrx  r7, 0, (r5)
        sync
        lwbrx   r4, 0, (r6)
        andi.   r4, r4, 0xff00

        lis     r3,target_mode@h
        ori     r3,r3,target_mode@l
        stwx    r4,0,r3




init_global_cont:
 addis r1,0,0x8 
 ori r1,r1,0x0000 
 

 lis r3,0x7fff 
 ori r3,r3,0xffff 
 mtspr 22,r3 
 
 
 
 


 lis r3,main@h 
 ori r3,r3,main@l

 mtspr srr0,r3 
 
 addis r4,0,0x0000
 ori r4,r4,dink_msr 
 mtspr srr1,r4 
 
 

 addis   r13,r0,_SDA_BASE_@h
        ori     r13,r13,_SDA_BASE_@l

 rfi 




error_dram_init:
 lis r0,0xDEAD 
 ori r0,r0,0x000D 
 b error_dram_init
#line 2055
 .text
 .align 2
 .global mmu_setup
mmu_setup: 



 mfspr r3, sprg0 

 cmpi 0,0,r3,0x2
 beq rom_bat_excimer

 cmpi 0,0,r3,0x3 
        beq     cr0,setup_kahlua
 cmpi 0,0,r3,0x4 
        beq     cr0,setup_kahlua
 cmpi 0,0,r3,0x5 
        beq     cr0,setup_kahlua



 addis r4,0,0xff00 
       addis r3,0,0xff00 
 ori r4,r4,0x0012 
 ori r3,r3,0x01ff 
 b rom_bat




setup_kahlua:

 addis r4,0,0xfe00 
 ori r4,r4,0x0012 
       addis r3,0,0xfe00 
 ori r3,r3,0x03ff 

 isync 
 mtspr ibat0l,r4 
 isync
 mtspr ibat0u,r3
 isync

 addis r4,0,0xfc00 
 ori r4,r4,0x002a 
       addis r3,0,0xfc00 
 ori r3,r3,0x07ff 

 mtspr dbat0l,r4
 isync
 mtspr dbat0u,r3
 isync
 sync

 addis r4,0,0x0000 
 ori r4,r4,0x0012 
 addis r3,0,0x0000 
 ori r3,r3,0x0fff 

 isync
 mtspr ibat1l,r4
 isync
 mtspr ibat1u,r3
 isync

        lis     r4, 0x0
 ori r4,r4,0x002a 
        b       cont_mmu

rom_bat_excimer:
 addis r4,0,0xffc0 
       addis r3,0,0xffc0 
 ori r4,r4,0x0032 
 
 
 ori r3,r3,0x007f 

rom_bat:
 isync
 mtspr ibat0l,r4
 isync
 mtspr ibat0u,r3
 isync

 mtspr dbat0l,r4
 isync
 mtspr dbat0u,r3
 isync
 sync
#line 2153
 addis r4,0,0x0000 
 ori r4,r4,0x0012 
 addis r3,0,0x0000 
 ori r3,r3,0x1fff 

 isync
 mtspr ibat1l,r4
 isync
 mtspr ibat1u,r3
 isync

cont_mmu:
 mtspr dbat1l,r4
 isync
 mtspr dbat1u,r3
 isync
 sync
#line 2179
        mfspr   r8, sprg1 
        add     r3, r8, 0x0
        add     r4, r8, 0x0
        ori     r3, r3, 0x01ff
        ori     r4, r4, 0x0022
 isync
 mtspr ibat2l,r4 
 isync
 mtspr ibat2u,r3
 isync
 mtspr dbat2l,r4 
 isync
 mtspr dbat2u,r3
 isync
 sync
#line 2199
 isync
 mtspr ibat3l,r0
 isync
 mtspr ibat3u,r0
 isync
 mtspr dbat3l,r0
 isync
 mtspr dbat3u,r0
 isync
#line 2217
        mfspr   r8, sprg1 
#line 2223
 cmpwi r3, 0xFE00 

 bne extra_bats
 
 lis r4,   0x7800
 ori r4,r4,0x003A 
       lis r3,   0x7800
 ori r3,r3,0x1FFF

 isync 
 mtspr dbat3l,r4
 isync
 mtspr dbat3u,r3
 isync
#line 2242
extra_bats:
 mfspr r4, pvr
 srawi r3,r4,16
 cmpi 0,0,r3,0x0008
 bne tlb_init 

 andi. r3,r4,0x3000 
 beq tlb_init 

 andi. r3,r4,0x0F00 
 cmpi 0,0,r3,0x0200
 blt tlb_init 
#line 2261
 isync
 mtspr ibat4l,r0
 isync
 mtspr ibat4u,r0
 isync

 mtspr ibat5l,r0
 isync
 mtspr ibat5u,r0
 isync

 mtspr ibat6l,r0
 isync
 mtspr ibat6u,r0
 isync

 mtspr ibat7l,r0
 isync
 mtspr ibat7u,r0
 isync

 mtspr dbat4l,r0
 isync
 mtspr dbat4u,r0
 isync

 mtspr dbat5l,r0
 isync
 mtspr dbat5u,r0
 isync

 mtspr dbat6l,r0
 isync
 mtspr dbat6u,r0
 isync

 mtspr dbat7l,r0
 isync
 mtspr dbat7u,r0
 isync



 mfspr r4,1011 
 oris r4,r4,0x0004 
 mtspr 1011,r4
 isync


tlb_init:
 addis r3,0,0 
 ori r3,r3,0 

 mfspr r4, pvr
 srawi r4,r4,16

 cmpi 0,0,r4, 0x3 
 beq set_mmu_for603
 cmpi 0,0,r4, 0x6 
 beq set_mmu_for603
 cmpi 0,0,r4, 0x7
 beq set_mmu_for603


 addis r5,0,0x4 
 b tlblp 

set_mmu_for603:
 addis r5,0,0x2 

tlblp: 
 tlbie r3
 sync
 addi r3,r3,0x1000
 cmp 0,0,r3,r5 
 
 blt tlblp

 blr
 
.text
.align 2
.global time_base_init

time_base_init:

 mflr r3
 nop
 nop
 nop
 andi. r4,r0,0
 mtspr 285,r4
 mtspr 284,r4
 mtlr r3 
 blr

.text
.align 2
.global time_base_read_lower

time_base_read_lower:

 mflr r4
 nop
 nop
 nop
 mfspr r3,268
 mtlr r4 
 blr

.text
.align 2
.global time_base_read_upper

time_base_read_upper:

 mflr r4
 nop
 nop
 nop
 mfspr r3,269
 mtlr r4 
 blr

.text
.align 2
.global decrementer_read

decrementer_read:
 mfspr r3,22
 blr

.text
.align 2 
.global hid1_read

hid1_read:
 mfspr r3,hid1
 blr


.text
.align 2
.global pvr_read

pvr_read:
 mfspr r3,pvr
 blr


.text
.align 2
.global l2cr_read

l2cr_read:
 mfspr r3,l2cr
 blr
#line 2425
 
.text
.align 2
.global user_return

user_return:
 mtspr sprg3,r3 
 mtspr sprg2,r4 
 lis r3,usr_code_rtn@h 
 ori r3,r3,usr_code_rtn@l 
 li r4,0x0001 
 stw r4,0(r3)
 addis r3,0,0 
 ori r3,r3,0xaaaa 
 
 
 lis r4, ex_type@h 
 ori r4,r4, ex_type@l 
 stwx r3,0,r4 
 b handle_ex 


.text
.align 2
.global therm1_read

therm1_read:
 mfspr r3,1020
 blr


.text
.align 2
.global therm2_read

therm2_read:
 mfspr r3,1021
 blr


.text
.align 2
.global therm3_read

therm3_read:
 mfspr r3,1022
 blr


.text
.align 2
.global therm1_write
therm1_write:
 mtspr 1020,r3
 blr


.text
.align 2
.global therm2_write

therm2_write:
 mtspr 1021,r3
 blr


.text
.align 2
.global therm3_write

therm3_write:
 mtspr 1022,r3
 blr

.text
.align 2
.global decrementer_write

decrementer_write:
 mtspr 22, r3
 blr


.text
.align 2
.global total_recall

total_recall:
 sync
 sync
 mtlr r3 
 sync
 sync
 blr


.text
.align 2
.global cache_inhibit

cache_inhibit:



 mfspr r3, hid0
 addis r4,0,0xffff
 ori r4,r4,0x3fff
 and r3,r3,r4
 sync
 mtspr hid0,r3 
 isync
 blr

 .text
 .align 2
 .global invalidate_and_enable_L1_dcache

invalidate_and_enable_L1_dcache:
 
 mfspr r5,hid0 
 ori r5,r5,0x4400 
 mfspr r4, pvr 
 srawi r3, r4, 16 
        cmpi  0, 0, r3, 0xC 
        bne   NotMax
 ori r5,r5,0x0040 
NotMax:
 addis r6,0,0xFFFF
 ori r6,r6,0xFBFF
 and r6,r5,r6 
 sync
 mtspr hid0,r5
 mtspr hid0,r6
 isync
 sync
 blr


 .text
 .align  2 
 .global fL1dc
 
fL1dc:
 
 lis r4,0x0 
fL1dc_head:
 cmpw r3,r4 
 ble fL1dc_done 
 lwz r5,0(r4) 
 addi r4,r4,0x4 
 b fL1dc_head 
fL1dc_done:
 blr


 .text
 .align  2 
 .global disable_L1_dcache
 
disable_L1_dcache:

 mfspr r5,hid0
 addis r6,0,0xFFFF
 ori r6,r6,0xBFFF
 and r5,r5,r6
 sync
 mtspr hid0,r5
 isync
 sync
 blr


 .text
 .align 2
 .global invalidate_and_enable_L1_icache

invalidate_and_enable_L1_icache:
 
 mfspr r5,hid0 
 ori r5,r5,0x8800 
 addis r6,0,0xFFFF
 ori r6,r6,0xF7FF
 and r6,r5,r6 
 sync
 mtspr hid0,r5
 mtspr hid0,r6
 isync
 sync
 blr

 .text
 .align 7
 .global disable_L1_icache

disable_L1_icache:

 mfspr r5,hid0
 addis r6,0,0xFFFF
 ori r6,r6,0x7FFF
 and r5,r5,r6
 sync
 mtspr hid0,r5
 isync
 sync
 blr


 .text
 .align 7
 .global srr1_read

srr1_read:

 mfspr r5,srr1
 lis r3,0x7
 ori r3,r3,0x0100
        stwx    r5,0,r3
 blr

cache_activate:

 mfspr r5,hid0 
 ori r5,r5,0xc000
 sync
 mtspr hid0,r5
 isync
 sync
 blr

data_translation_on:

 mfmsr r5
 ori r5,r5,0x30
 mtmsr r5
 isync
 blr

data_translation_off:

 mfmsr r5
 addis r6,0,0xffff
 ori r6,r6,0xffcf
 and r5,r5,r6
 mtmsr r5
 isync
 blr



 
switch_to_little_endian:

 
 mfmsr r4 

 
 ori r4,r4,0x1 



 mtspr srr1,r4


 
 mfspr r3,lr
 mtspr srr0,r3
#line 2696
 sync




 
 rfi

.text
.align 2
.global setup_bursted_mode

setup_bursted_mode:
#line 2714
 mflr r4 

 bl cache_inhibit
 bl data_translation_off




 andi. r0,r0,0
 addis r10,r0,0x0000
 addi r10,r10,0x01ff
 

 addis r11,r0,0x0000
 addi r11,r11,0x42 
 

 
 
 mtibatu 1,r10
 mtibatl 1,r11
 
 mtdbatu 1,r10
 mtdbatl 1,r11

 bl data_translation_on
 bl cache_activate

 mtlr r4

 blr 

.text
.align 2
.global put_ram_in_cb

put_ram_in_cb:

 mflr r4

 bl cache_inhibit

 bl data_translation_off 
 andi. r0,r0,0
 addis r10,r0,0x0000
 addi r10,r10,0x01ff 
 addis r11,r0,0x0000
 addi r11,r11,0x12 

 mtibatu 1,r10
 mtibatl 1,r11
 mtdbatu 1,r10
 mtdbatl 1,r11

 bl  data_translation_on

 bl cache_activate

 mtlr r4
 blr

.text
.align 2
.global put_ram_in_wt

put_ram_in_wt:

 mflr r4 

 bl cache_inhibit
 bl data_translation_off

 
 

 
 andi. r0,r0,0
 addis r10,r0,0x0000
 addi r10,r10,0x01ff
 
 addis r11,r0,0x0000
 addi r11,r11,0x52 

 mtibatu 1,r10
 mtibatl 1,r11
 
 mtdbatu 1,r10
 mtdbatl 1,r11

 bl data_translation_on
 bl cache_activate

 mtlr r4

 blr 
#line 2814
 .text
 .align  2
 .global global_L2backside_invalidate

global_L2backside_invalidate:

 mfspr r4, pvr 
 srawi r3, r4, 16 
        cmpi 0,0,r3,0x8 
        beq inval_L2Cache
        cmpi 0,0,r3,0xC 
        beq inval_L2Cache
 blr 

inval_L2Cache:
 sync 
 mfspr r3,l2cr
 lis r4,0x7FFF 
 ori r4,r4,0xFFFF
 andis. r3,r3,r4 
 mtspr l2cr,r3
 sync

 oris r3, r3, 0x0020 
 mtspr l2cr, r3 

invalidate_in_progress:
 sync 
 mfspr r3, l2cr
 andi. r3, r3, 0x1
 cmpwi r3,0x1
 beq invalidate_in_progress 

 sync 
 lis r4,0x7FDF 
 ori r4,r4,0xFFFF
 mfspr r3,l2cr
 and r3,r3,r4 
 mtspr l2cr, r3
 sync

 blr
#line 2869
 .text
 .align  2
 .global init_L2backside_value

init_L2backside_value:
 sync
 b init_L2_store

 .text
 .align  2
 .global init_L2backside_cache

init_L2backside_cache:
 
 andi.   r0,r0,0
 mfspr r4, sprg0 
 cmpi 0,0,r4,0x5
 beq init_L2_PPMC 



 addis r3,r0,0x2542 
 
 
 
 
 
 
 
 
 
 
 
 ori r3,r3,0x0000 
 
 
 
 b init_L2_store
#line 2916
init_L2_PPMC:
 mfspr r4, pvr 
 srawi r3, r4, 16 
        cmpi 0,0,r3,0x8 
        beq init_L2_PPMC_Cache
        cmpi 0,0,r3,0xC 
        beq init_L2_PPMC_Cache

 blr 

init_L2_PPMC_Cache:
 addis r3,r0,0x3D01 
 
 
 
 
 
 
 
 
 
 
 
 ori r3,r3,0x4000 
 
 
 

init_L2_store:
 mtspr l2cr, r3 
 sync 
#line 2953
 or r8,r0,r3

 or r3,r0,r8



 oris r3, r3, 0x8000 
 mtspr l2cr, r3 
 sync

 blr


il2c_loop:
 stw r12,0x0(r10)
 addi r10,r10,0x4
 addic. r11,r11,-0x4
 bne il2c_loop 
 blr


ct_delay_loop:

 andi. r0,r0,0
 addis  r10,r0,0x0001

ctdll:
 addic. r10,r10,-0x1
 bne ctdll

 blr


 .text
 .align  2
.global l2test

l2test:
        andi.   r0, r0, 0 
        addis   r3, r0, 0x8
        andis.  r4,r4,0
 addis r5, r0, 0x8

loop:
        stwx    r4, r4, r3
        addi    r4, r4, 0x20
        cmpl   cr0, r4, r5
        blt     loop

        stwx    r4, r4, r3
        blr 

 .text
 .align  2
 .global simple_leap
simple_leap:
 mfspr r3,hid0
 addis r4,0,0xffff
 ori r4,r4,0x3fff
 and r3,r3,r4
 sync
 mtspr hid0,r3
 isync
 sync 

 mfmsr r3
 addis r4,0,0xffff
 ori r4,r4,0xffcf
 and r3,r3,r4
 mtmsr r3
 isync
 sync 

 b 0xffc00100
#line 3032
 .text
 .align  2
 .global init_L2DM

init_L2DM:
 mtspr 1016,r3 
 sync

 blr
#line 3048
 .text
 .align 2
 .global flush_dcache_max

flush_dcache_max:




 
 mfspr r5,msscr0 
 ori     r7,r5,0 

 addis r6,0,C_dL1HWf 
 ori r6,r6,0xFFFF 
 and r7,r7,r6 

 addis   r6,0,dL1HWf 
 or r5,r5,r6 
 
 sync
 mtspr msscr0,r7 
 mtspr msscr0,r5 
 isync
 sync
 blr
#line 3081
 .text
 .align 2
 .global get_kahlua_pcsrbar

get_kahlua_pcsrbar:
 lis     r3,config_addr@h
 ori     r3,r3,config_addr@l
 lwz     r5,0(r3)
    sync

 lis     r3,config_data@h
 ori     r3,r3,config_data@l
 lwz     r6,0(r3)
    sync

 lis     r3,target_addr@h
 ori     r3,r3,target_addr@l
    lwz     r7,0(r3)
    sync

    ori     r7,r7,PCSRBAR
 stwbrx  r7, 0, r5
 sync

 lwbrx r3, 0, r6
 sync

    blr
 
#line 3120
 .text
 .align 2
 .global config_kahlua_agent

config_kahlua_agent:
 lis     r3,config_addr@h
 ori     r3,r3,config_addr@l
 lwz     r5,0(r3)
 sync

 lis     r3,config_data@h
 ori     r3,r3,config_data@l
 lwz     r6,0(r3)
    sync

 lis     r3,target_addr@h
 ori     r3,r3,target_addr@l
    lwz     r7,0(r3)
    sync

 
    ori     r3,r7,PCSRBAR
    lis     r4,PCSRBARVAL 
 
 
    stwbrx  r3,0,r5
    sync
    stwbrx  r4,0,r6
 sync

 
 
 
    ori     r3,r7,PCICMD
    li      r4,0x0006 

    stwbrx  r3,0,r5
    sync

    sthbrx  r4,0,r6 
    sync


    lis    r3, 0x0001
    mtctr   r3

wait_agent:
    bdnz    wait_agent
 
    blr
#line 3176
 .text
 .align 2
 .global mccr_update

mccr_update:
 mtspr sprg0,r3
 mtspr sprg1,r4
 mtspr sprg2,r5
 mtspr sprg3,r6

 lis     r4,config_addr@h
 ori     r4,r4,config_addr@l
 lwz     r5,0(r4) 
 sync

 lis     r4,config_data@h
 ori     r4,r4,config_data@l
 lwz     r6,0(r4) 
 sync

 lis r4,0x8000
 ori r4,r4,0x00F0 
 stwbrx r4,0,r5
 sync
 lwbrx r4,0,r6 
 lis r3,0xfff7 
 ori r3,r3,0xffff
 and r4,r3,r4 
 stwbrx r4,0,r6 




 lis r4,0x0110 
 mtctr   r4
mu_wait1: bdnz mu_wait1




 lis r4,0x8000
 ori r4,r4,0x00FC 
 stwbrx r4,0,(r5)
 sync
 lwbrx r4,0,(r6) 

 lis r3,0xffff 
 ori r3,r3,0x8fff

 and r4,r3,r4 

 mfspr r3,sprg0 
 slwi r3,r3,12

 or r4,r3,r4 

 stwbrx r4,0,(r6)




 lis r4,0x8000
 ori r4,r4,0x00F8 
 stwbrx r4,0,(r5)
 sync
 lwbrx r4,0,(r6) 

 lis r3,0xff0f 
 ori r3,r3,0xffff
 and r4,r3,r4 

 mfspr r3,sprg0 
 addi r3,r3,1 

 slwi r3,r3,20
 or r4,r3,r4 

 stwbrx r4,0,(r6)




 lis r4,0x8000
 ori r4,r4,0x00F0 
 stwbrx r4,0,(r5)
 sync

 lwbrx r4,0,(r6) 
 oris r4,r4,0x0008 
 stwbrx r4,0,(r6) 




 lis r4,0x0110
 mtctr   r4
mu_wait2: bdnz mu_wait2

 mfspr r6,sprg2
 mfspr r5,sprg1
 mfspr r4,sprg0
 blr
#line 3287
 .data
 .align 2
 
temp_sprg0:
 .global temp_sprg0
 .long 0


io_base_addr:
        .global io_base_addr
        .long   0

config_addr:
        .global config_addr
        .long   0

config_data:
        .global config_data
        .long   0
#line 3314
board_type:
 .global board_type
 .long 0



target_type:
 .global target_type
 .long 0



target_mode:
 .global target_mode
 .long   1


target_addr:
 .global target_addr
 .long   0

float_0:
 .double 0


temp_sprg1:
 .global temp_sprg1
 .long 0

temp_reg:
 .global temp_reg
 .long 0


temp_gpr2:
 .global temp_gpr2
 .long 0


ex_type:
 .global ex_type
 .long 0


ex_addr:
 .global ex_addr
 .long  0
 
in_which_code:
 .global in_which_code
 .long  0




usr_code_rtn:
 .global usr_code_rtn
 .long  0
 
#line 3381
dink_type:
 .global dink_type
 .long 0

temp_lr:
 .global temp_lr
 .long 0

        .align 4 
vector_register_memory:
 .global vector_register_memory
        .skip 1024