/* file: yellowknife.h and board.h */ /* This file contains defines for the YellowKnife CHRP-compliant board. This includes the 106, the WINBOND PCI-ISA bridge, and the National IO Controller. */ #include "config.h" #define BB_BE /* current values (_V) shown for r/w regs are those given at reset. */ /* value for PIC1 was suggested at meeting w/ Mike Becker. */ /* bytes for addresses and data values must be swapped before writing them */ /* to the 105. However, writes to go out over the PCI bus do not need any byte- */ /* swapping; they will go through just fine. */ #define VID 0x0000 #define DID 0x0200 #define PCI_CR 0x0400 #define PCI_CR_V 0x0600 /* 2 bytes */ #define PCI_SR 0x0600 #define RID 0x0800 #define SPINT 0x0900 #define SUBCLASSCODE 0x0a00 #define CLASSCODE 0x0b00 #define CACHELINESIZE 0x0c00 #define LATENCYTIMER 0x0d00 #define HEADERTYPE 0x0e00 #define BISTCONTROL 0x0f00 #define INTERRUPTLINE 0x3c00 #define INTERRUPTPIN 0x3d00 #define MINGNT 0x3e00 #define MAXGNT 0x3f00 #define BRIDGENUMBER 0x4000 #define SUBORDBUSNUM 0x4100 #define DISCONNECTCNT 0x4200 #define SPECIALCYCLEAR 0x4400 #define POWERMGMTCONF 0x0070 /* Power management config. 1 */ #define PMC_V 0x0000 /* 2 bytes */ #define OUTDRIVERCNTRL 0x0073 /* Output Driver Control Register */ /* need initial values for mem bank starts and ends and enable */ #define MEMSTARTADDR1 0x0080 /* Memory starting address-upper */ #define MSA1_V1 0x0000 /* X2 value of Mem. start addr. upper */ #define MSA1_V2 0x0000 #define MSA1_X4_V1 0xffff /* X4 value of Mem. start addr. upper */ #define MSA1_X4_V2 0xff00 #define MEMSTARTADDR2 0x0084 /* Memory starting address-lower */ #define MSA2_X4_V1 0xffff /* X4 value of mem. start addr. lower */ #define MSA2_X4_V2 0xffff #define XMEMSTARTADDR1 0x0088 /* Extended mem. starting addr.-upper*/ #define XMSA1_X4_V1 0x0303 #define XMSA1_X4_V2 0x0300 #define XMEMSTARTADDR2 0x008c /* Extended mem. starting addr.-lower*/ #define XMSA2_X4_V1 0x0303 #define XMSA2_X4_V2 0x0303 #define MEMENDADDR1 0x0090 /* Memory ending address-upper */ #define MEA1_V1 0x0000 /* X2 value */ #define MEA1_V2 0x0007 #define MEA1_X4_V1 0xffff /* X4 value */ #define MEA1_X4_V2 0xff10 #define MEMENDADDR2 0x0094 /* Memory ending address-lower */ #define MEA2_X4_V1 0xffff /* X4 value */ #define MEA2_X4_V2 0xffff #define XMEMENDADDR1 0x0098 /* Extended mem. ending address-upper*/ #define XMEA1_X4_V1 0x0303 /* X4 value */ #define XMEA1_X4_V2 0x0300 #define XMEMENDADDR2 0x009c /* Extended mem. ending address-lower*/ #define XMEA2_X4_V1 0x0303 #define XMEA2_X4_V2 0x0303 /* X4 value */ #define MEMENABLE 0x00a0 /* Memory bank enable */ #define ME_V 0x01 /* Set 1 byte for X2 */ #define ME_X4_V1 0x0008 /* value of Mem. page mode - 1 byte */ #define ME_X4_V2 0x0001 /* value of mem. enable - 1 byte */ #define PAGEMODE 0x00a3 #define PROCINTCONF1 0x00a8 /* Processor interface config. 1 */ #define PROCINTCONF2 0x00ac /* Processor interface config. 2 */ #ifdef L2CACHE /* Internal write back L2 cache with one processor...this code won't */ /* work with Arthur. This register just has the CF_L2_MP bits set to */ /* 10->uniprocessor, internal, write-back L2 cache (changed bits 0 */ /* and 1). Also, the CF_CBA_MASK is changed from default of FF to */ /* 3F because the tag ram is not wide enough for the FF mask */ /* */ #define PIC1_V1 0x3f90 #define PIC1_V2 0x0a1a /* Yes, L2 cache */ /* 512K Pipelined Burst SRAM, Sync. Tag RAM */ /* L2_UPDATE_EN = 1 (L2 can be updated with new data) */ /* CF_FAST_L2_MODE = 0...disabled for safety */ /* CF_DATA_RAM_TYPE = 01 for pipelined burst SRAM */ /* CF_WMODE = 00 for normal write timing w/o partial update */ /* CF_SNOOP_WS = 11 (3 wait states) */ /* CF_MOD_HIGH = 1 because TV and DIRTY_IN are active high on Yellowknife */ /* CF_HIT_HIGH = 1 because HIT Is active high on Yellowknife */ /* CF_HOLD = 0 because we're using sync. tag RAMs */ /* CF_L2_HIT_DELAY = 11 (3 wait states) */ /* CF_TWO_BANKS = 0 (only 1 SRAM bank) */ /* CF_L2_SIZE = 01 for 512K */ /* CF_APHASE_WS = 11 (3 wait states) */ /* CF_WDATA = 1 because TS is connected to ADSP on the L2 data RAM...this is IMPORTANT and */ /* specific to Yellowknife */ /* */ /* Writing this value to PICR2 = 0xC04F065D */ /* #define PIC2_V1 0x5d06 */ /* #define PIC2_V2 0x4fc0 */ /* Yes, L2 cache */ /* 512K Pipelined Burst SRAM, Sync. Tag RAM */ /* L2_UPDATE_EN = 1 (L2 can be updated with new data) */ /* CF_FAST_L2_MODE = 0...disabled for safety */ /* CF_DATA_RAM_TYPE = 01 for pipelined burst SRAM */ /* CF_WMODE = 00 for normal write timing w/o partial update */ /* CF_SNOOP_WS = 01 (1 wait states) */ /* CF_MOD_HIGH = 1 because TV and DIRTY_IN are active high on Yellowknife */ /* CF_HIT_HIGH = 1 because HIT Is active high on Yellowknife */ /* CF_HOLD = 0 because we're using sync. tag RAMs */ /* CF_L2_HIT_DELAY = 01 (1 wait states) */ /* CF_TWO_BANKS = 0 (only 1 SRAM bank) */ /* CF_L2_SIZE = 01 for 512K */ /* CF_APHASE_WS = 01 (1 wait states) */ /* CF_WDATA = 1 because TS is connected to ADSP on the L2 data RAM...this is IMPORTANT and */ /* specific to Yellowknife */ /* */ /* Writing this value to PICR2 = 0xC0470255 */ #define PIC2_V1 0xc047 #define PIC2_V2 0x0255 #else /* No L2 cache at all */ #define PIC1_V1 0x3f90 #define PIC1_V2 0x0a18 #define PIC2_V1 0x000c #define PIC2_V2 0x060c #define PIC1_X4_V1 0x3f04 #define PIC1_X4_V2 0x0400 #define PIC2_X4_V1 0x0047 #define PIC2_X4_V2 0x0215 #endif #define ERRORENABLE1 0x00c0 #define ERRORDETECT1 0x00c1 #define ERRORENABLE2 0x00c4 #define ERRORDETECT2 0x00c5 #define CPU_PCI_EAR 0x00c8 /* Winbond ISA Bridge Controller */ /* Programmable Interrupt Controller Registers */ #define PIC1_ICW1 0x20 /* Initialization write only */ #define PIC1_ICW2 0x21 /* Initialization write only */ #define PIC1_ICW3 0x21 /* Initialization write only (master) */ #define PIC1_ICW4 0x21 /* Initialization write only */ #define PIC1_OCW1 0x21 /* Operation */ #define PIC1_OCW2 0x20 /* Operation write only */ #define PIC1_OCW3 0x20 /* Operation */ #define PIC2_ICW1 0xA0 #define PIC2_ICW2 0xA1 #define PIC2_ICW3 0xA1 #define PIC2_ICW4 0xA1 #define PIC2_OCW1 0xA1 #define PIC2_OCW2 0xA0 #define PIC2_OCW3 0xA0 /* all values in BE. writes to go to Winbond part must set AD[11]. */ #define UM_BASE 0x8080 #define UM_VID 0x0800 /* 2 bytes */ #define UM_DID 0x0802 #define UM_CR 0x0804 #define UM_DSR 0x0806 #define UM_RID_CC 0x0808 /* 4 bytes */ #define UM_PCI_CR 0x0840 /* 1 byte */ #define UM_PCI_ACR 0x0841 #define UM_PCI_APCR 0x0842 #define UM_AB_RCR 0x0843 #define UM_CD_RCR 0x0844 #define UM_SGRB_ADDR 0x0845 #define UM_PCI_IRER 0x0846 #define UM_PROG_REG 0x0847 #define UM_PCI_BMCR 0x0850 #define UM_PCI_BTMR 0x0851 #define UM_NPCI_BMBSR 0x0852 #define UM_NPCI_BMB1SAR 0x0853 #define UM_NPCI_BMB2SAR 0x0854 #define UM_ISA_MPR 0x0855 #define UM_ISA_CDR 0x0856 #define UM_ISA_IORTR 0x0857 #define UM_PMU_OMCR 0x0870 /* 7 bytes */ #define UM_PMU_SMCR 0x0880 /* 2 bytes */ #define UM_PMU_ICR 0x0890 /* 3 bytes */ #define UM_PMU_ECR 0x08a0 /* 1 byte */ #define UM_PMU_MISC1 0x08a2 /* 3 bytes */ #define UM_PMU_MISC2 0x08a8 /* 1 byte */ /* NS SuperI/O */ #define COM1 0x03F8 #define COM2 0x02F8 #define IO_IND_ADDR 0x002E #define IO_DAT_ADDR 0x002F /* FER, PTR, and FAR have preset values on reset from CFG0-4. */ /* all I really care about is getting UART1 set up. */ #define IO_FER 0x0000 #define IO_FAR 0x0001 #define IO_PTR 0x0002 #define IO_FCR 0x0003 #define IO_FCR_V 0x00 #define IO_PCR 0x0004 #define IO_PCR_V 0x80 #define IO_KRR 0x0005 #define IO_KRR_V 0x00 #define IO_TUP 0x0007 #define IO_SID 0x0008 #define IO_ASC 0x0009 /* this stuff is important to initialize */ /* the DUART channels. */ #define Scale 0x01 /* distance between port addresses (error 0x01L - fix) */ #define Com1 0x000003f8 /* Keyboard */ #define Com2 0x000002f8 /* Host */ /* Port Definitions relative to base COM port addresses */ #define DataIn (0x00*Scale) /* data input port */ #define DataOut (0x00*Scale) /* data output port */ #define BaudLsb (0x00*Scale) /* baud rate divisor least significant byte */ #define BaudMsb (0x01*Scale) /* baud rate divisor most significant byte */ #define Ier (0x01*Scale) /* interrupt enable register */ #define Iir (0x02*Scale) /* interrupt identification register */ #define Fcr (0x02*Scale) /* FIFO control register (write) */ #define Lcr (0x03*Scale) /* line control register */ #define Mcr (0x04*Scale) /* modem control register */ #define Lsr (0x05*Scale) /* line status register */ #define Msr (0x06*Scale) /* modem status register */ /* Bit Definitions for above ports. */ #define LcrDlab 0x80 /* b7: enable baud rate divisor registers. */ #define LcrDflt 0x03 /* b6-0: no parity, 1 stop, 8 data */ #define McrRts 0x02 /* b1: request to send (I am ready to xmit) */ #define McrDtr 0x01 /* b0: data terminal ready (I am alive ready to rcv) */ #define McrDflt (McrRts|McrDtr) #define LsrTxD 0x6000 /* b5: transmit holding register empty (i.e. xmit OK) */ /* b6: transmitter empty */ #define LsrRxD 0x0100 /* b0: received data ready (i.e. got a byte) */ #define MsrRi 0x0040 /* b6: ring indicator (other guy is ready to rcv) */ #define MsrDsr 0x0020 /* b5: data set ready (other guy is alive ready to rcv */ #define MsrCts 0x0010 /* b4: clear to send (other guy is ready to rcv) */ /* YELLOWKNIFE DEFINITION TABLE */ /* PnP Register Definitions */ #define INDEX_ADDRESS 0x03 #define LDN 0x07 #define DEVICE_ID 0x20 #define SIO_CNFG1 0x21 #define SIO_CNFG2 0x22 #define CSCONFIG_INDX 0x23 #define CSCONFIG_DATA 0x24 #define ACTIVATE 0x30 #define IORANGECHK 0x31 #define PBASE_IO_ADDR_U 0x60 #define PBASE_IO_ADDR_L 0x61 #define PINTRPT_SEL 0x70 #define PINTRPT_TYPE 0x71 #define DMA_CHNL0_SEL 0x74 #define DMA_CHNL1_SEL 0x75 #define LDN_CNFG1REG 0xF0 /* Super I/O Logical Device Numbers */ #define LDN_0 0x0 /* Keyboard */ #define LDN_1 0x1 /* Mouse */ #define LDN_2 0x2 /* RTC */ #define LDN_3 0x3 /* FDC */ #define LDN_4 0x4 /* Parallel Port */ #define LDN_5 0x5 /* Serial Port Com 2 */ #define LDN_6 0x6 /* Serial Port Com 1 */ #define LDN_7 0x7 /* GPIO Ports */ #define LDN_8 0x8 /* Power Management */