GaAs FRISC Test Wafer

SiGe FRISC Test Reticle

SiGe FRISC Test Wafer

SiGe FPGA Test Die

World's Fastest FPGA is SiGe HBT BiCMOS

Fast-RISC (FRISC) & SiGe Home Page

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Faculty: [J. F. McDonald] [R. P. Kraft] [H. J. Greub]


[M. LeRoy] [S. Liu] [R. Clarke]

[T. Neogi (graduated 7/11)]

[P. Jacob (graduated 8/10)] [A. Zia (graduated 8/09)] [M. Chu (graduated 7/09)]

[J.-W. Kim (graduated 7/09)] [P. Belemjian (graduated 7/08)] [P. Jin (graduated 12/07)]

[O. Erdogan (graduated 12/06)] [J. Diao (graduated 12/06)] [Y. Yim (graduated 12/06)]

[J.-R. Guo (graduated 11/05)] [P. Curran (graduated 8/05)] [Y. Chao (graduated 5/05)]

[K. Zhou (graduated 8/04)] [R. Heikaus (graduated 8/04)] [J. Mayega (graduated 12/02)]

[M. Ernest (graduated 5/03)] [S. Steidl (graduated 5/01)] [B. Goda (graduated 5/01)]

[T. Krawczyk (graduated 12/00)] [S. Carlough (graduated 5/00)] [X. Ma (graduated 5/99)]

[A. Garg (graduated 8/97)] [P. M. Campbell (graduated 5/97)] [C. Maier (graduated 8/96)]

[K.-S. Nah (graduated 8/94)] [R. Philhower (graduated 12/93)] [J. Loy (graduated 8/93)]

  • H. J. Greub is now with Intel, OR.
  • J. Loy is with now Morgan Stanley Dean Wittier Securities, NY.
  • R. Philhower is now with IBM, Yorktown Heights, NY.
  • K.-S. Nah is now with Samasung, S. Korea.
  • C. Maier is now with AMD, CA.
  • P. M. Campbell is now with IBM, NY.
  • A. Garg is now with AMD, CA.
  • X. Ma is now with Intel, Hudson, MA.
  • S. Carlough is now with IBM, NY.
  • T. Krawczyk is now with Sierra Monolithics, CA.
  • B. Goda is now with the United States Military Academy, West Point, NY.
  • S. Steidl is now with Sierra Monolithics, CA.
  • M. Ernest is now with Intel, OR.
  • K. Zhou is now with Intel, OR.
  • Y. Chao is now with the University of South Dakota.
  • P. Curran is now with Sierra Monolithics, CA.
  • J.-R. Guo is now with IBM, NY.
  • J. Diao is now with Bear Stearns & Co. Inc.
  • P. Belemjian is now with Navel Research Laboratories.
  • J.-W. Kim is now with Samsung.
  • M. Chu is now on a post doc with Rensselaer.
  • A. Zia is now with Intel, OR.
  • P. Jacob is now with IBM, NY.
  • T. Neogi is now with Global Foundries, NY.

Cadence Design Systems Driven Layouts

Since 1998 all SiGe designs, simulations, layouts, and verifications have been done using Cadence tools. Starting with the fall 1999 semester, the Cadence packages have been the primary IC design tools utilized in the Introduction to VLSI Design and the VLSI Design Automation classes offered by the Electrical, Computer, & Systems Engineering Dept. at Rensselaer. (More Cadence tools are used in other ECSE classes.)

Cadence Design System's homepage                   Facilities & Equipment: Sun, Tektronix & more

Online Documents

DARPA Summary

 Introduction to FRISC Project
 Semiannual Reports
 Interim Reports
 Final Reports
 3-D Reports
 Teaching Reports
 Publications and Patents
 Clockless Asynchronous Logic Interests (CLASS)

AlGaAs/GaAs HBT chips designed so far

  • Test Reticle

  • SiGe HBT chips designed using IBM's process

    F-RISC Manuals...

    Useful Links

    Packaging and Interconnections Sites

    Interesting Articles

    Send your suggestions to Russell Kraft ( ).   (Last updated July 20, 2004)
    For more info, please contact:
    Prof. J. F. McDonald,
    Center for Integrated Electronics, Rensselaer Polytechnic Institute, Troy, NY 12180
    E-mail:, Phone: 518-276-2919 Fax: 518-276-8761