Standard Cell Test Chip
Principal Investigator: Prof. John F. McDonald
Center for Integrated Electronics
Electrical Computer and Systems Engineering Department
Rensselaer Polytechnic Institute
Troy, NY-12180
Designed by Cliff Maier and Bob Philhower
The Standard Cell / Boundary Scan test chip is designed to provide confirmation of the F-RISC standard cell library and the boundary scan scheme designed by Bob Philhower for use in all of the F-RISC chips except for the RAM.
The chip contains several buffer chains and a carry-chain which can be set into oscillation in order to allow speed characterization. A complete self-timed boundary scan testing capability is included to allow confirmation of boundary scan testing capabilities.
This page is still under construction. Send your suggestions to Cliff Maier.
(Last updated Mar 27, 1995)