CP_TO_SPICE Netlist Extractor

Originally developed by Robert Philhower, modified extensively by Peter M. Campbell

Last Modification

Overview

The Netlist Extractor is a tool originally written by Bob Philhower and significantly enhanced by Peter M. Campbell. This tool will take a VLSI Tools Composition Editor (cp) file and automatically extract a full netlist from the design. In addition, there are several options for controlling or guiding the extraction process, mostly to avoid known problems with the VLSI Tools extractor. This tool is written in the AWK language and uses AWK, the C Shell, and VLSI Tools to perform the extraction. The VLSI Tools extractor alone is not sufficient for extracting netlists from .cp files because it creates nested subcircuit definitions as well as other problems.

The extractor is called 'cp_to_spice' and is located in '/cie3/frisc/sw/extraction'. The first parameter on the command line is the name of the VLSI Tools .CP file (without the .cp extension) which is to be extracted. You may also include '-noseg' as the second parameter to tell the extractor not to create .SEG files again and thus save time. This is useful if the extractor has previously stopped early due to either errors or user intervention.

Command-line Parameters

There are several parameters which may be specified. The first parameter must always be the name of the VLSI Tools .CP file (without the .cp extension) to be extracted. The optional parameters (in any order) determine if .SEG files will be created and the level of messages that the extractor returns. Including 'noseg' as a parameter tells the extractor not to create .SEG files. This is useful if the necessary files already exist, presumably because extractor has previously stopped early due to either errors or user intervention.

The other available parameter indicates the number of messages which will be reported during the extraction (e.g. the "verbosity" of the extraction). This parameter is simply a number which specifies the relative amount of messsages which should be printed by the extractor. Currently, there are four levels available. If you specify a number higher than 3 the extractor operates at level 3. If you do not specify a verbosity level, it defaults to 3 (maximum).

Examples

Features

Global Subcircuit Library

The global subcircuit library contains common subcircuit definitions for the FRISC project. These include device definitions and models, resistor and capacitor definitions, and VDD/VEE/VSS settings. This library is called 'hbt.lib' and is in '/cie3/frisc/sw/extraction/hbt.lib'.

Local Subcircuit Library

The extractor looks in the local directory for a file called 'filename.lib' where filename is the name of the file being extracted. This file is identical in format to the global subcircuit library.

Cell-Exclude File

Cells listed in 'filename.exc' will not be extracted and may/may not be included in the final extracted netlist.

Cells should be excluded if they would cause the VLSI Tools extractor to crash (such as cells with either no devices or no interconnect, e.g. CSWTALLs, pad rows, etc).

Things to watch out for...

Common Problems

FATAL: UNIX Signal: Segmentation violation

Netlist error: Port mismatch for instance X...

Cells with Known Problems

The cells below have problems due to situations described above. You should probably include these cells in your exclude file.
CSWTALL2x
These cells contain two transistors but no interconnect. They should not be used in new designs and should be replaced in old designs (when possible).

ROWENDF
This cell contains only interconnect.

FEEDTHF
This cell contains only interconnect.