CP_TO_SPICE Netlist Extractor
Originally developed by Robert Philhower, modified extensively by
- 4/26/95 - Added cell-exclude capability to subcells
The Netlist Extractor is a tool originally written by Bob Philhower
and significantly enhanced by Peter M. Campbell. This tool will take a
VLSI Tools Composition Editor (cp) file and
automatically extract a full netlist from the design. In addition,
there are several options for controlling or guiding the extraction
process, mostly to avoid known problems with the VLSI Tools extractor.
This tool is written in the AWK language and uses AWK, the C Shell,
and VLSI Tools to perform the extraction. The VLSI Tools extractor
alone is not sufficient for extracting netlists from .cp files because
it creates nested subcircuit definitions as well as other problems.
The extractor is called 'cp_to_spice' and is located in
'/cie3/frisc/sw/extraction'. The first parameter on the command line
is the name of the VLSI Tools .CP file (without the .cp extension)
which is to be extracted. You may also include '-noseg' as the second
parameter to tell the extractor not to create .SEG files again and
thus save time. This is useful if the extractor has previously
stopped early due to either errors or user intervention.
There are several parameters which may be specified. The first
parameter must always be the name of the VLSI Tools .CP file (without
the .cp extension) to be extracted. The optional parameters (in any
order) determine if .SEG files will be created and the level of
messages that the extractor returns. Including 'noseg' as a parameter
tells the extractor not to create .SEG files. This is useful if the
necessary files already exist, presumably because extractor has
previously stopped early due to either errors or user intervention.
The other available parameter indicates the number of messages which
will be reported during the extraction (e.g. the "verbosity" of the
extraction). This parameter is simply a number which specifies the
relative amount of messsages which should be printed by the extractor.
Currently, there are four levels available.
If you specify a number higher than 3 the extractor operates at level
3. If you do not specify a verbosity level, it defaults to 3
- Level 0 consists of minimal messages, primarily start, stop and
- Level 1 consists of level 0 messages along with a bit more
information about what the extractor is doing.
- Level 2 includes levels 0 and 1 but it also will describe what
cell/subcircuit is currently being processed.
- Level 3 encompasses levels 0-2 but it descrbes every step and
operation in detail.
- "cp_to_spice dp verbose 2"
- "cp_to_spice dp noseg"
- "cp_to_spice dp noseg verbose 5"
- Follows file path used in the design in order to locate .cp files used
in the design but not located in the working directory.
- Node names are converted to names which are PSPICE compatible. Newer
versions of PSPICE may not need this feature but it is automatically
done anyway. All nested subcells/subcircuits are placed on the
top-level in the netlist, thereby avoiding nested SUBCKT definitions
(which would result in PSPICE error messages).
- Fully automated - needs no operator intervention
- Repeatable - extractions on same .cp file will produce the same netlist
- Unnesting of subcircuits. Designs with multiple levels of hierarchy
may be easily extracted.
Global Subcircuit Library
The global subcircuit library contains common subcircuit definitions
for the FRISC project. These include device definitions and models,
resistor and capacitor definitions, and VDD/VEE/VSS settings. This
library is called 'hbt.lib' and is in '/cie3/frisc/sw/extraction/hbt.lib'.
Local Subcircuit Library
The extractor looks in the local directory for a file called
'filename.lib' where filename is the name of the file being extracted.
This file is identical in format to the global subcircuit library.
Cells listed in 'filename.exc' will not be extracted and may/may not
be included in the final extracted netlist.
Cells should be excluded if they would cause the VLSI Tools extractor
to crash (such as cells with either no devices or no interconnect,
e.g. CSWTALLs, pad rows, etc).
- Cell names which are followed by 'all' (without quotation marks)
will not be included in the extracted netlist as either SUBCKT
definitions or as called subcircuits (i.e. XCKT1).
- A cell listed without 'all' will not be included as a SUBCKT
definition but will be included where needed as subcircuit calls.
- As of 4/26/95, the exclude file for the top-level circuit is used
throughout the extraction (i.e. in all sub-cell extractions also)
- Some cells you do not want at all because they have no
function electrically (e.g. ROWENDF, FEEDTHF), hence you should use
the 'all' spec to remove them completely and make the extracted
- Other cells are too large or are not useful, such as register file
or cache blocks.
- You may also want to exclude cells which are also defined in
HBT.LIB or the local library in order to avoid warning messages
stating that a .CP file and a .LIB definition exist for the same cell.
Things to watch out for...
Layout cells without interconnect (i.e. only devices)
The VLSI Tools extractor cannot handle cells without some
Layout cells without subcells or resistors (i.e. only wires)
The VLSI Tools extractor cannot handle cells without one or more
subcells or resistors. This is probably because a SPICE subcell must
contain one or more devices or elements.
Devices/resistor connectors without names or unique names
The VLSI Tools extractor gets confused when a device does not have
unique connector names. This causes a netlist mismatch error (see
FATAL: UNIX Signal: Segmentation violation
- This problem may be caused by the file descriptors limit
being set too low (typically 64), especially if you are extracting a
large cell. Type 'limit desc 256' and retry.
- Another cause may be due to lack of interconnect within a cell. If
a cell consists of only subcells and abutments with no interconnect
wires, the VLSI Tools extractor will crash. Your options are inserting
some interconnect or excluding the cell from the extraction.
- This problem may also occur if VLSI Tools crashes. Check the
filename.OUT file and compare it with the filename.1 and filename.2
files to see which cell causes the tools to crash. You will probably
have to place the offending cell into the 'FILENAME.exc' file.
Netlist error: Port mismatch for instance X...
- This problem usually occurs when the instance connectors are not
labelled or have the same name (presumably causing the port mismatch).
Edit the instance and change the connector names so each is unique.
Cells with Known Problems
The cells below have problems due to situations described above. You
should probably include these cells in your exclude file.
- These cells contain two transistors but no interconnect. They should
not be used in new designs and should be replaced in old designs (when
- This cell contains only interconnect.
- This cell contains only interconnect.