Matched Capacitance Layout of Differential Circuits

Developed by Peter M. Campbell


As the speed of circuits increases, the signal skew between each line in a differential signal can become significant. In order to reduce skew and increase the top-end speed, the parasitic capacitance of each signal half must be matched as closely as possible. For signal routing, this objective can be mostly achieved by routing each half of the signal in adjacent routing tracks. However, it is still important to ensure balanced skew within each cell on the critical path.

In order to achieve balanced delay within a cell, layout techniques may be employed which are designed specifically for this purpose. These techniques are specific to the design of differential circuits, primarily because these circuits exhibit a high degree of symmetry.


Specific Items

As with any process, there are numerous constraints under which a designer must operate. While these restrictions are usually process-specific, they do share a universal character with other processes. As a result, observations from a specific design-rule set may be extrapolated to a number of general restrictions and constraints.

General Restrictions and Assumptions

Extrapolation to universal constraints


Device positioning

Due to the IC process our foundry uses, the device orientation is restricted. More specifically, the emitter stripes for all devices must have the same orientation (North-South or East-West).

Common interconnect situations

Effect upon interconnect routing


Power/Ground rail design

Effect upon layout

Signal routing

"Usability" of each metal layer

Symmetric layout


Current F-RISC standard cell library

Symmetric layout

This section is still under construction.
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