Cadence Develops Software for ARPA High-Speed Circuit Design Program

Multi-million Dollar Project Targets Ultra High-Speed CMOS & Gallium Arsenide Processes for Dual-Use Military & Commercial ICs

San Jose, Calif., November 7, 1994 -- Cadence Design Systems, Inc. today announced a multi-year, multi-million dollar contract to enhance, integrate and deliver electronic design automation (EDA) software for the Advanced Research Projects Agency's (ARPA) High-Speed Circuit Design Program. Backed by the United States Department of Defense, the ARPA-funded project tackles the complex design and process requirements for 400MHz CMOS and 10GHz Gallium Arsenide (GaAs) heterojunction bipolar transistor (HBT) integrated circuits. Since these dual-use integrated circuits (ICs) will run 4-5x faster than today's 100 MHz CMOS and 2 GHz GaAs ICs, they target the next-generation military requirements for high-speed radar, signal processing and phased array radar. In addition, the ARPA ICs will meet commercial requirements for high-speed phone switches, satellites and the data/video communications networks. Drawing on the expertise of industry leaders in IC design software and processes, the ARPA High-Speed Circuit Design Program targets 1996 for volume production and commercial availability of the high-speed circuits, bringing together: Rockwell as the prime contractor for overall program management, GaAs HBT IC fabrication and 10GHz GaAs HBT test chips; IBM for design, CMOS fabrication and 400MHz CMOS test chips; Rensselaer Polytechnic Institute (RPI) for design services and expertise; University of California at San Diego (UCSD) for modeling and algorithms; Cadence Design Systems for an advanced design automation system based on Cadence's digital and analog design solutions, along with 3D extraction tools from OEA International. The far-reaching project includes advanced features in Cadence's software for digital and analog design, simulation, floorplanning, place and route, and verification. In addition, Cadence will develop new layout and analysis algorithms, consult in developing new design methodologies and model development, and will sponsor an Industrial Relations Board (IRB) to ensure that the CAD system meets emerging industry-wide requirements. Cadence will incorporate all advances developed under this contract into a standard commercial package for high-speed circuit design. In addition, any enhancements to individual tools will be included in the next commercial release of that tool, with initial offerings available as of late 1995. Rockwell & IBM To Fabricate Test Chips Given the economic imperative to leverage military development for commercial uses, a key provision of the High-Speed Circuit Design Program is to ensure volume, commercial IC production. ARPA ensures this commercial production readiness by requiring sample "test chips," a stipulation that encompasses all steps of a repeatable design and manufacturing process. Rockwell will leverage the design and modeling work of UCSD and RPI to fabricate HBT ICs that will operate in excess of 10GHz clock rates, refining a process to ensure volume production of large-scale cell and gate-array based design for HBT ICs. Specifically, Rockwell will manage the process of developing robust HBT model equations, device design and modeling, testing, data analysis, HBT test pattern generation, and successful wafer fabrication runs. IBM will provide the design and fabrication for the 400MHz CMOS circuits, drawing on their Yorktown engineering and manufacturing expertise for high-speed CMOS processes. Since correctly designing high-speed CMOS requires accurate analysis of parasitics including inductance, Cadence's integration of 2D and 3D parasitic extraction tools is critical to the project's success. As with Rockwell, IBM will produce test chips in order to verify the design and modeling algorithms, verify overall chip timing accuracy, and reduce the design and development time currently required for high-speed CMOS. Integrated EDA Solution for Signal Integrity & Advanced Routing To address the new high-speed circuit design challenges in timing analysis, electromagnetic coupling effects and I/O driver limitations, Cadence will optimize its software to ensure signal integrity; provide advanced place and route capabilities and new physical design algorithms; integrate 3D parasitic extraction; and provide an efficient design methodology and integrated design flow. In addition, Cadence will consult on modeling the new HBT processes, and will incorporate the resulting HBT model equations into Cadence's Spectre analog simulator. Specifically, Cadence will ensure signal integrity and critical path optimization throughout a design methodology that includes its Spectre advanced circuit simulator; Preview floorplanner; Cell3 Ensemble place & route system; verification technology; DF/Thermax thermal analysis system; and Analog Artist analog IC design solution. To address high-speed wire effects, Cadence will develop and utilize new place and route algorithms to calculate "flight" times; automatic electrical rules checking for loading, logic level, etc.; timing-driven delay management for critical paths; and thermal balance of critical circuits. Cadence will also provide advanced routing tools to balance routes for minimal skew, specify wire widths during floorplanning, and automatically route differential signals. Cadence & OEA Link 2 & 3D Extraction for Accurate Timing Analysis To meet the new timing analysis challenges of high-speed package design, Cadence will enhance and link its own 2D and 2 1/2D extraction tools with OEA International's 3D extraction tools, Metal 2D/3D Field Simulator and Henry 3D Inductance Simulator. This will allow designers to choose the appropriate level of analysis from 2D through full 3D as the design becomes fully implemented, accurately predicting and controlling resistance, capacitance and inductance in order to meet performance goals for critical functions. In addition to 3D tools, Cadence will integrate OEA International's Net-An and P-Grid products with the Cadence Framework, providing accurate analysis of critical nets and power networks. Since Net-An and P-Grid use OEA's fast "Cheetah" solver technology to solve millions of equations in minutes, they can provide very accurate 3D values previously impractical to obtain. Leveraging Advanced IC Design Technology OEA International, Inc. designs and licenses state-of-the-art signal integrity software for the electronic computer-aided (ECAD) industry. OEA's software is designed to be extremely high performance and handle very complex models with a high degree of accuracy. OEA products are used to substantially increase engineering productivity and first time success in the design of interconnect and packaging technologies for sophisticated electronic systems and integrated circuits. Cadence Design Systems, Inc. is the worldwide leader in the development and marketing of design automation software and services that accelerate and advance the process of designing electronic systems. Cadence combines leading-edge technology with a complementary set of services that enable customers to improve the quality and time-to-market performance of innovative electronic products. Cadence is based in San Jose, Calif. and employs approximately 2,400 people in research and development, sales and support locations worldwide. The Company is listed on the New York Stock Exchange under the symbol CDN. Metal, Henry, Net-An, P-Grid and Cheetah Solver are trademarks of OEA International, Inc. Spectre, Preview, Ensemble, DF/Thermax and Analog Artist are trademarks of Cadence Design Systems, Inc.