1. ARO PROPOSAL #: 37390-EL,
RPI proposal #: 159-97-101F, RPI internal Account # A10802.
2. PERIOD COVERED BY REPORT:
August 1, 1997 - December 31, 1997.
3. TITLE OF PROPOSAL:
"MCM Packaging for F-RISC/G- Subnanosecond
Fast RISC for TeraOPS Parallel Processing Applications"
4. CONTRACT OR GRANT NUMBER:
5. NAME OF INSTITUTION:
Rensselaer Polytechnic Institute
6. AUTHOR OF REPORT:
Professor J. F. McDonald
7. LIST OF MANUSCRIPTS SUBMITTED OR PUBLISHED UNDER ARO SPONSORSHIP
DURING THIS PERIOD, INCLUDING JOURNAL REFERENCES:
``A 16 GHz Fast RISC Engine using GaAs
and SiGe HBT Technology" S.
Carlough, S. Steidl. Kraft, A. Garg, C. Maier, P. Campbell, H.
J. Greub and J.F. McDonald, Proceedings of 1997 International
Conference on Innovative Systems in Silicon, ISIS97, L. LaForge,
H. Bolouri, D. Sciuto, and S. Tewksbury, October 8-10, 1997,
"A Very Wide Bandwidth Digital VCO using
Quadrature Frequency Multiplication/Division Implemented with
GaAs/AlGaAs HBT's," P. Campbell,
J. F. McDonald, H. Greub, S. Steidl, C. Maier, and A. Garg, I.E.E.E.
Transactions on VLSI Systems, December 1997.
Graduate Students supported during life of
Hans Greub (PhD awarded, Dec. 1990), Matthew Ernest,
Atul Garg (PhD awarded, December 1997), Sam Steidl, Steve Carlough,
Peter Campbell (AASERT PhD awarded, May 1997), Clifford Maier
(AASERT PhD awarded, May 1996), Tom Kryczak
J. F. McDonald (Full Professor), H. Greub (Assistant
Professor), R. Kraft (Adjunct Professor).
8. REPORT OF INVENTIONS (BY TITLE ONLY):
None to report in this period.
The goal of the F-RISC/G (Fast Reduced Instruction
Set Computer - version G) project at Rensselaer is to develop
a 32-bit GaAs/AlGaAs processor with a cycle time of 1.0 ns and
a peak performance of 1000 MIPS, utilizing a 2 GHz four phase
clock. A 5 chip set of GaAs integrated circuits has been developed
for this task. This contract is for the design and fabrication
of a GE/HDI MCM to permit integration of these integrated circuits.
The project is unique in the sense that the chips have an extremely
large number of GaAs/AlGaAs HBT's on each chip of the multichip
partition of the architecture For the GaAs/AlGaAs F-RISC/G effort
initial yield expectations for the Rockwell Newbury Park 50 GHz
1.4 micron baseline process were a mere 5K transistors at 20%
yield. However, during the lifetime of the contract that expectation
rose to 8K transistors at ~50% yield. The smallest of the FRISC
chips has ~10K HBT's. Hence, this project will test yields of
the Rockwell process on much larger chips than have been attempted
before. The key to integrating these circuits will be the Multichip
Module Package. This form of packaging permits integrating 25
GaAs/AlGaAs integrated circuits totaling more than a quarter of
a million HBT's. The submission of the fabrication run for these
integrated circuits has been delayed a great deal due to modeling
errors in the SPICE model for the HBT presented by Rockwell for
use in digital circuits. In addition, wire capacitances were
~30% larger due to undocumented anisotropy in the DuPont 2610/11
polyimides used as interlayer dielectrics in that process. However,
after extremely difficult and lengthy rework to overcome these
difficulties the integrated circuits are now, finally fully ready
for fabrication. This fabrication requires fulfillment of a Rensselaer
Purchase Order for $120K that was issued at the end of the first
contract for FRISC/G sponsored by DARPA/ARO. The funds for this
contract have been encumbered for an extremely long time awaiting
completion of the redesign effort. Essentially the modeling errors
proved very difficult to overcome in the redesign effort, and
in fact, require two non standard design rule changes in the Rockwell
standard 50 GHz process to overcome these deficiencies.
The work presented here may be considered preparatory
for eventual microprocessor integration at much higher HBT yield
levels. For example, IBM has developed a new silicon CMOS compatible
SiGe base HBT comparable in speed to the Rockwell 50 GHz baseline
process devices. SiGe HBT yields are much higher, at least at
the 40,000 HBT level, and no device specific yields have been
seen yet at IBM relative to a conventional Si bipolar process.
Hence, yields for these devices may range from 100K to over 1M
as this process matures. Work by one of the graduate students
[C. Maier] at EXPONENTIAL Inc. of San Jose subsequent to his graduation
in 1996, revealed that with a 25 GHz HITACHI 0.5 micron Si bipolar/CMOS
process there was enough yield to fabricate a 533 MHz three way
superscalar Power PC emulator for the new IBM 750 chip which
uses the same CML circuitry for all its logic that is used in
these GaAs integrated circuits. IBM's new 6 level 0.25 micron
Cu interconnect process will host 100 GHz SiGe HBT's. Between
the factor of 4 in improved device performance relative to the
HITACHI EXP process and the enhanced low resistance Cu interconnect
to be used in that process one can predict a factor of at least
16 improvement in clock rate relative to either the EXP chip or
the FRISC architecture. The FRISC architecture does not follow
the PowerPC architecture in the interest of achieving the highest
clock rate possible. This should give superior worst case timing
Specific accomplishments of the present packaging
contract include the completion of the entire design for the GE/HDI
MCM package. This work was conducted in conjunction with Glen
Forman who is the GE/HDI program manager at the nearby GE Corporate
Research and Development Center in Niskayuna, New York, a mere
30 miles from the campus. All of the artwork for the GE Cu/Polyimide
chip to chip wiring tape has been completed and design rule checked
in conjunction with GE. The Polyimide used in this process processed
by extrusion and does not exhibit the anisotropy seen in the chip
dielectrics. The fastest signals for the architecture (2GHz)
are transmitted with predictable attenuation due to slight resistance
in the lines up to the longest line in the system which is 5 cm.
The subcontract for this work will be let at the point when we
are certain the chip tape is accepted for fabrication at Rockwell
for the chips. This is being done to assure cost estimation done
at the start of the GE contract will not increase significantly
as the chips are being fabricated. The MCM houses 25 GaAs chips
of approximately 1cm die size.
The following figure is a screen capture of several
of the layers of the GE/HDI MCM tape as produced by the Mentor
At the edge of the GE/HDI tape one can see the U
shaped fixtures which provide access to SMA mini connectors shown
in the following figure
These adapters provide for the primary test lines to test the FRISC at the 2 GHz clock rate. One is the clock and the other two are for a serial test input/output port that can verify CPU activity at speed. Additional connectors are provided for SI/SO serial test leads of the overall boundary scan system to check the GE/HDI chip to chip wiring and to verify that chips under the tape have survived to that point in the packaging process.
The GE/HDI process is compatible with the construction
of an Al nitride ceramic base that can be interfaced to an IBM
Enterprise microfin array heat sink as shown in the following
figure. An exhaust plenum has been acquired to dissipate the heat
from the system.
A printed circuit board has been devised to provide
the serial driver/receiver interface to drive the SMA 2 GHz connectors
for testing either the individual chips after fabrication via
GGB or Cascade Microwave probe assemblies, for testing the chips
manually after insertion into the partially assembled GE/HDI package
at various stages, or for the finally assembled package.
This pin driver card will provide the shift in and
shift out clock signals needed by the GaAs HBT chips and the integrated
MCM system to assure adequate signal edge acuity for proper behavior
while interfacing to the IBM PC through an FPGA that provides
the hardware needed to personalize the patterns for each chip.
The parts under test also receive a direct 2GHz clock for at
speed boundary scan test after the test patterns are shifted in.
In addition to the nominal package research activity
undertaken on this contract, one significant development for the
future has taken place. Partially by support by DARPA and partially
by fellowship support at INTEL and IBM, one of the students in
the group [Sam Steidl] undertook a project to redesign the core
5 GHz register file of the Fast RISC/G into the newer IBM 50 GHz
SiGe HBT process at East Fishkill. This process involves cointegration
of the HBT with CMOS 5S, which is an 0.5 micron process, although
none of the design effort involved CMOS for this project. The
old register file was only 8 bits wide, and was singly ported
due to yield constraints in the GaAs process. The new register
file is a fully integrated 32 bit register file with three independent
ports, two for simultaneous reading and one for simultaneous writing.
Test circuitry for running the register file at the anticipated
7-8 GHz rate was cointegrated and submitted to Joel Goldberg at
MOSIS for inclusion into the first DARPA sponsored SiGe HBT shared
reticle. The chip finally fit into a space 2mm by 2.5mm, which
was comparable to the space for the first test chip built at Rockwell
for the GaAs HBT register file. This results from the fact that
the anticipated yield at the IBM foundry is more than 4 times
larger than that at the GaAs foundry.
This work is cited as technology transfer because
as one of the conditions for IBM making the SiGe HBT process available
to RPI, IBM is free to examine or sample any of the circuits that
are fabricated from RPI designs.
In addition to the register file a second small integrated
circuit was provided to MOSIS for fabrication under the same run.
This is a SiGe HBT version of the wideband VCO discussed in the
summary of publicatioins above, for the GaAs/AlGaAs VCO presented
there. This circuit is available for transfer to NSA, a collaborating
contributor to the same shared reticle.
The significance of this VCO is that it can be used to generate clock signals to 20 GHz for a great variety of projects. One of the functions to be driven by this oscillator is a set of "silicon slow wave" characterization test structures to examine attenuation of signals in various wiring environments in the presence of the lossy silicon substrate. Silicon slow wave attenuation represents a major gap in CAD support for design with SiGe HBT technology. Essentially attenuation can be quite drastic at 10 GHz clock rate unless there is mitigating screening by other nearby conductors. Unfortunately there is no CAD tool yet to help us predict the amount of attnuation that will remain, especially in light wiring congestion areas.
For example, consider a 8 GHz pulse propagating along
a line over silicon with no nearby screening conductors. After
propagating only 1cm the pulse will be nearly completely absorbed.