EDTN Network     September 20, 2001

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SiGe process pushes reconfigurable FPGA to 5 GHz

By Peter Clarke
EE Times
(09/10/01, 3:34 p.m. EST)

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BELFAST, Northern Ireland — One of the world's fastest FPGAs — capable of supporting reconfigurable computing at gigahertz clock frequencies — is being developed by researchers from Rensselaer Polytechnic Institute and the U.S. Military Academy (West Point, N.Y.).

The researchers, including engineers from IBM and Sierra Monolithics Inc. (Redondo Beach, Calif.), are making use of silicon germanium BiCMOS process technologies from IBM Microelectronics.

In a paper presented at the Field-Programmable Logic and Applications conference here last month, the researchers proposed a family of high-speed FPGAs that use the fast heterojunction bipolar transistor present within SiGe process technology. They discussed the results of test circuits with operating frequencies in the 5-GHz range, as compared with those for commercial FPGAs of typically 70 to 250 MHz, depending on the complexity of the logic applied. A two orders of magnitude improvement is envisaged.

Military demands

"The military has some very demanding real-time applications," said Russell Kraft, senior project manager at Rensselaer (Troy, N.Y.). "We decided to use the [Xilinx] XC6200 architecture so that we would have EDA software and a development environment available and could concentrate on developing the hardware."

Although the XC6200, with its support for partial reconfiguration, has been popular among leading programmable-logic researchers, development on that version of the product was suspended in 1998.

All the logic and routing in the new interpretation of the XC6200 is multiplexer-based, eliminating the need for pass transistors. "FPGAs typically use pass transistors in the switch block and that tends to drag down performance," said Kraft. "It does go faster but also draws more current. But at these frequencies pure CMOS would also be a problem."

Another innovation is the use of differential current mode logic. Although it requires additional interconnect — two wires per bit — results include small voltage swings of 250 millivolts as opposed to 3.3 V or 5 V, and a power savings, said Kraft.

So far the research team has used IBM's 50-GHz 5HP process technology defined at 0.5-micron minimum geometries to build an array of four configurable logic blocks, interconnect circuitry and I/O circuitry.

"IBM's 7HP 100-GHz 0.18-micron process should become available to us soon," said Kraft.

Also new is the proposed use of separate CMOS die to hold the routing configuration stacked above the BiCMOS SiGe. Kraft has proposed multiple CMOS configuration planes above the logic die so that the XC6200's partial reconfigurability could be used rapidly. This work blends into projects funded by the Defense Advanced Research Projects Agency on three-dimensional circuits, which are also being conducted at Rensselaer.

Kraft said the group's next step is to build a complete XC6200-style FPGA including a 16 x 16 array of configurable logic blocks, but it wasn't clear whether that would be built in the older or newer IBM silicon germanium process.

"We are holding back slightly; we want to get the new process," said Kraft. He estimated that the 100-GHz process should allow circuits to operate at up to about a 20-GHz clock frequency.


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