Room Temperature Supercomputing - 16 GHz SiGe HBT Fast-RISC - Computing at GHz Speeds DAAG 55-97-1-0316

10/22/98


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Table of Contents

Room Temperature Supercomputing - 16 GHz SiGe HBT Fast-RISC - Computing at GHz Speeds DAAG 55-97-1-0316

Why is HBT important for Computing?

Outline

Advanced Fast Reduced Instruction Set Computers

Cross section of Rockwell GaAs/AlGaAs npn HBT (fT = 50 GHz)

Sample Rockwell 50 GHz HBT and CML Circuit used in F-RISC

1.2 ?m GaAs MESFET/HBT Comparison of Delay vs. Wire Length

Architecture of 2 GHz Clock Fast RISC/G Showing 1024 bit L1/L2 path

Critical Paths

F-RISC/G Final Reticle

GE/HDI ́Mother-Daughter Boardî MCM for F-RISC/G with 3 Inserts

F-RISC/G MCM Chip Placement and Route

GE/HDI Showing (Orange) Wiring Tape

GaAs HSCD Wafer

GGB 6 Channel 14 GHz Probe

HSCD GaAs HBT Reticle

Test GaAs Reticle with Boundary Scan Circuit

Fabricated Pin Driver Testboard

Testboard Pin Driver High Rise Time Output

FRISC Pad Driver Test Verification

Register File Memory Cell

RPI HBT Tst Chip for 5 GHz Register File and Carry Chain Oscillator

Symmetric Frequency Multiplier

HF VCO Test Circuit

HBT F-RISC/G MCM Thermal Distribution

Thermal Management - CMOS

Comparison of 3 CMOS Generations

Cross Section of a Double Gate SOI FET at 0.19 microns

Outline

SiGe Test Wafer

IBM 50 GHz SiGe Base HBT (Polysilicon emitter)

SiGe Test Reticle

GaAs and SiGe HBT Minimum Emitter Size Comparison

FRISC/H VLIW Architecture (simplified)

fT vs. Ic Curves (50 and 113 IBM GHz SiGe HBTs)

SiGe fT versus Ic for various Emitter Areas

fT and Power versus Emitter Areas

Van der Ziel Lateral Base Pushout Effect

Outline

Hitachi Low Power, High Speed SiGe HBT

Hitachi Low Power, High Speed SiGe HBT

Hitachi SiGe HBT Process Flow

Hitachi SiGe HBT Base CVD Process

Detailed Cross Section of Hitachi HBT

SEM Cross Section of HITACHI HBT

Hitachi HBT Frequency Scaler Performance

Typical I-V Plot for Hitachi SiGe HBT

PPT Slide

PPT Slide

PPT Slide

Advanced Fast Reduced Instruction Set Computers

Outline

Improvement in Breakdown Voltage with C

SiGe HBT threshold sharpening at 84K

30% improvement for SiGe @ Cryo!

Outline

Comparison of Silicon Slow Wave attenuation & dispersion for pulses with different oxide layer thickness

Outline

RPI SiGe Triple Ported Register File Test Chip

RPI SiGe RF Design

Outline

16 GHz Adder Block

Outline

Conclusions

Author: Jack McDonald

Email: mcdonald@unix.cie.rpi.edu

Home Page: http://inp.cie.rpi.edu/research/mcdonald/frisc