Slide 4 of 64
This is the obligatory DARPA quad chart which shows a glimpse at one of the fast register file memory cells in our present GaAs HBT. It also lists some of the reasons why DARPA might have funded this work. The project is now in its 8th year of funding and is now in the last stages of the GE/HDI packaging effort. Future proposed work is with 100 GHz HBTs just now appearing in GaAs, and SiGe technologies with enough yield to implement quasi monolithic processors. These would be major building blocks in a VLIW architecture.