Slide 8 of 64
This slide shows the architecture of F-RISC/G, a 1000 MIPS integer demonstration computing engine with a 2GHz clock. It is a combination of the famous Berkeley RISC II and the so called Harvard Architecture which has two caches, one for data and one for instructions so that each can be accessed simultaneously. The L1 cache has to be extremely fast to keep up with the core processor, so it is made from HBT circuitry, but is very small (4KB). To compensate for the high miss rate, the transfer to and from L2 cache is one full line of cache per cycle, a line being 32 words, or 1024 bits. Clearly differential wiring is required to avoid simultaneous switching noise, so LVDS is required of L2, which can be CMOS 1K x 32 SRAM at 5 nanoseconds access time. This 1024 bit bus is also an opportune location for a 10 GHz I/O channel!