Slide 9 of 64
This slide shows the internal architecture of the Fast RISCG [G for GaAs] engine. The register file must be singly ported and the ALU must be byteslice organized to accommodate the relatively low experimental yields of 10,000 HBTs. This puts constraints on the circuit design that approximately cost a factor of 4 in clock rate. That is if the yields were high enough [say 50,000 HBTs] then the clock rate might rise to 8 GHz from 2GHz using the same speed devices. The register file could be triply ported, and an intermediate level of cache called L0 would have to be introduced.