Slide 10 of 64
This is the GDSII final artwork file for the F-RISC/G as sent to Rockwell for fabrication. The byteslice DataPath or DP chip is to be replicated 4 times for the 32 bit architecture. Only the Register Files (RFs) are handcrafted. The Instruction Decoder (ID) is shown on the lower right and has primarily standard cell layout. Modified RFs are used to form cache blocks, which run very hot (account for most of the processor heat dissipation) due to a lack of co-integrated CMOS for GaAs.